ddr_topology_def.h 4.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _DDR_TOPOLOGY_DEF_H
  6. #define _DDR_TOPOLOGY_DEF_H
  7. #include "ddr3_training_ip_def.h"
  8. #include "mv_ddr_topology.h"
  9. #include "mv_ddr_spd.h"
  10. #include "ddr3_logging_def.h"
  11. #define MV_DDR_MAX_BUS_NUM 9
  12. #define MV_DDR_MAX_IFACE_NUM 1
  13. enum mv_ddr_twin_die {
  14. COMBINED,
  15. NOT_COMBINED,
  16. };
  17. struct bus_params {
  18. /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
  19. u8 cs_bitmask;
  20. /*
  21. * mirror enable/disable
  22. * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
  23. */
  24. int mirror_enable_bitmask;
  25. /* DQS Swap (polarity) - true if enable */
  26. int is_dqs_swap;
  27. /* CK swap (polarity) - true if enable */
  28. int is_ck_swap;
  29. };
  30. struct if_params {
  31. /* bus configuration */
  32. struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM];
  33. /* Speed Bin Table */
  34. enum mv_ddr_speed_bin speed_bin_index;
  35. /* sdram device width */
  36. enum mv_ddr_dev_width bus_width;
  37. /* total sdram capacity per die, megabits */
  38. enum mv_ddr_die_capacity memory_size;
  39. /* The DDR frequency for each interfaces */
  40. enum mv_ddr_freq memory_freq;
  41. /* ddr twin-die */
  42. enum mv_ddr_twin_die twin_die_combined;
  43. /*
  44. * delay CAS Write Latency
  45. * - 0 for using default value (jedec suggested)
  46. */
  47. u8 cas_wl;
  48. /*
  49. * delay CAS Latency
  50. * - 0 for using default value (jedec suggested)
  51. */
  52. u8 cas_l;
  53. /* operation temperature */
  54. enum mv_ddr_temperature interface_temp;
  55. /* 2T vs 1T mode (by default computed from number of CSs) */
  56. enum mv_ddr_timing timing;
  57. };
  58. /* memory electrical configuration */
  59. struct mv_ddr_mem_edata {
  60. enum mv_ddr_rtt_nom_park_evalue rtt_nom;
  61. enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];
  62. enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];
  63. enum mv_ddr_dic_evalue dic;
  64. };
  65. /* phy electrical configuration */
  66. struct mv_ddr_phy_edata {
  67. enum mv_ddr_ohm_evalue drv_data_p;
  68. enum mv_ddr_ohm_evalue drv_data_n;
  69. enum mv_ddr_ohm_evalue drv_ctrl_p;
  70. enum mv_ddr_ohm_evalue drv_ctrl_n;
  71. enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];
  72. enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
  73. };
  74. /* mac electrical configuration */
  75. struct mv_ddr_mac_edata {
  76. enum mv_ddr_odt_cfg_evalue odt_cfg_pat;
  77. enum mv_ddr_odt_cfg_evalue odt_cfg_wr;
  78. enum mv_ddr_odt_cfg_evalue odt_cfg_rd;
  79. };
  80. struct mv_ddr_edata {
  81. struct mv_ddr_mem_edata mem_edata;
  82. struct mv_ddr_phy_edata phy_edata;
  83. struct mv_ddr_mac_edata mac_edata;
  84. };
  85. struct mv_ddr_topology_map {
  86. /* debug level configuration */
  87. enum mv_ddr_debug_level debug_level;
  88. /* Number of interfaces (default is 12) */
  89. u8 if_act_mask;
  90. /* Controller configuration per interface */
  91. struct if_params interface_params[MV_DDR_MAX_IFACE_NUM];
  92. /* Bit mask for active buses */
  93. u16 bus_act_mask;
  94. /* source of ddr configuration data */
  95. enum mv_ddr_cfg_src cfg_src;
  96. /* ddr twin-die */
  97. enum mv_ddr_twin_die twin_die_combined;
  98. /* raw spd data */
  99. union mv_ddr_spd_data spd_data;
  100. /* timing parameters */
  101. unsigned int timing_data[MV_DDR_TDATA_LAST];
  102. /* electrical configuration */
  103. struct mv_ddr_edata edata;
  104. /* electrical parameters */
  105. unsigned int electrical_data[MV_DDR_EDATA_LAST];
  106. /* ODT configuration */
  107. u32 odt_config;
  108. /* Clock enable mask */
  109. u32 clk_enable;
  110. /* Clock delay */
  111. int ck_delay;
  112. };
  113. enum mv_ddr_iface_mode {
  114. MV_DDR_RAR_ENA,
  115. MV_DDR_RAR_DIS,
  116. };
  117. enum mv_ddr_iface_state {
  118. MV_DDR_IFACE_NRDY, /* not ready */
  119. MV_DDR_IFACE_INIT, /* init'd */
  120. MV_DDR_IFACE_RDY, /* ready */
  121. MV_DDR_IFACE_DNE /* does not exist */
  122. };
  123. enum mv_ddr_validation {
  124. MV_DDR_VAL_DIS,
  125. MV_DDR_VAL_RX,
  126. MV_DDR_VAL_TX,
  127. MV_DDR_VAL_RX_TX,
  128. MV_DDR_MEMORY_CHECK
  129. };
  130. enum mv_ddr_sscg {
  131. SSCG_EN,
  132. SSCG_DIS,
  133. };
  134. struct mv_ddr_iface {
  135. /* base addr of ap ddr interface belongs to */
  136. unsigned int ap_base;
  137. /* ddr interface id */
  138. unsigned int id;
  139. /* ddr interface state */
  140. enum mv_ddr_iface_state state;
  141. /* ddr interface mode (rar enabled/disabled) */
  142. enum mv_ddr_iface_mode iface_mode;
  143. /* ddr interface base address */
  144. unsigned long long iface_base_addr;
  145. /* ddr interface size - ddr flow will update this parameter */
  146. unsigned long long iface_byte_size;
  147. /* ddr i2c spd data address */
  148. unsigned int spd_data_addr;
  149. /* ddr i2c spd page 0 select address */
  150. unsigned int spd_page_sel_addr;
  151. /* ddr interface validation mode */
  152. enum mv_ddr_validation validation;
  153. /* ddr interface validation mode */
  154. enum mv_ddr_sscg sscg;
  155. /* ddr interface topology map */
  156. struct mv_ddr_topology_map tm;
  157. };
  158. struct mv_ddr_iface *mv_ddr_iface_get(void);
  159. /* DDR3 training global configuration parameters */
  160. struct tune_train_params {
  161. u32 ck_delay;
  162. u32 phy_reg3_val;
  163. u32 g_zpri_data;
  164. u32 g_znri_data;
  165. u32 g_zpri_ctrl;
  166. u32 g_znri_ctrl;
  167. u32 g_zpodt_data;
  168. u32 g_znodt_data;
  169. u32 g_zpodt_ctrl;
  170. u32 g_znodt_ctrl;
  171. u32 g_dic;
  172. u32 g_odt_config;
  173. u32 g_rtt_nom;
  174. u32 g_rtt_wr;
  175. u32 g_rtt_park;
  176. };
  177. #endif /* _DDR_TOPOLOGY_DEF_H */