clearfog.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/soc.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include "../common/tlv_data.h"
  19. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  20. #include <../serdes/a38x/high_speed_env_spec.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /*
  23. * Those values and defines are taken from the Marvell U-Boot version
  24. * "u-boot-2013.01-15t1-clearfog"
  25. */
  26. #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
  27. #define BOARD_GPP_OUT_ENA_MID 0xffffffff
  28. #define BOARD_GPP_OUT_VAL_LOW 0x0
  29. #define BOARD_GPP_OUT_VAL_MID 0x0
  30. #define BOARD_GPP_POL_LOW 0x0
  31. #define BOARD_GPP_POL_MID 0x0
  32. static struct tlv_data cf_tlv_data;
  33. static void cf_read_tlv_data(void)
  34. {
  35. static bool read_once;
  36. if (read_once)
  37. return;
  38. read_once = true;
  39. read_tlv_data(&cf_tlv_data);
  40. }
  41. /* The starting board_serdes_map reflects original Clearfog Pro usage */
  42. static struct serdes_map board_serdes_map[] = {
  43. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  44. {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  45. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  46. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  47. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  48. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  49. };
  50. void config_cfbase_serdes_map(void)
  51. {
  52. board_serdes_map[4].serdes_type = USB3_HOST0;
  53. board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
  54. board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
  55. }
  56. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  57. {
  58. cf_read_tlv_data();
  59. /* Apply build configuration options before runtime configuration */
  60. if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
  61. board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
  62. if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
  63. board_serdes_map[4].serdes_type = SATA2;
  64. board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
  65. board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
  66. board_serdes_map[4].swap_rx = 1;
  67. }
  68. if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
  69. board_serdes_map[2].serdes_type = SATA1;
  70. board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
  71. board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
  72. board_serdes_map[2].swap_rx = 1;
  73. }
  74. /* Apply runtime detection changes */
  75. if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
  76. board_serdes_map[0].serdes_type = PEX0;
  77. board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
  78. board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
  79. } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
  80. /* handle recognized product as noop, no adjustment required */
  81. } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
  82. config_cfbase_serdes_map();
  83. } else {
  84. /*
  85. * Fallback to static default. EEPROM TLV support is not
  86. * enabled, runtime detection failed, hardware support is not
  87. * present, EEPROM is corrupt, or an unrecognized product name
  88. * is present.
  89. */
  90. if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
  91. puts("EEPROM TLV detection failed: ");
  92. puts("Using static config for ");
  93. if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
  94. puts("Clearfog Base.\n");
  95. config_cfbase_serdes_map();
  96. } else {
  97. puts("Clearfog Pro.\n");
  98. }
  99. }
  100. *serdes_map_array = board_serdes_map;
  101. *count = ARRAY_SIZE(board_serdes_map);
  102. return 0;
  103. }
  104. /*
  105. * Define the DDR layout / topology here in the board file. This will
  106. * be used by the DDR3 init code in the SPL U-Boot version to configure
  107. * the DDR3 controller.
  108. */
  109. static struct mv_ddr_topology_map board_topology_map = {
  110. DEBUG_LEVEL_ERROR,
  111. 0x1, /* active interfaces */
  112. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  113. { { { {0x1, 0, 0, 0},
  114. {0x1, 0, 0, 0},
  115. {0x1, 0, 0, 0},
  116. {0x1, 0, 0, 0},
  117. {0x1, 0, 0, 0} },
  118. SPEED_BIN_DDR_1600K, /* speed_bin */
  119. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  120. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  121. MV_DDR_FREQ_800, /* frequency */
  122. 0, 0, /* cas_wl cas_l */
  123. MV_DDR_TEMP_LOW, /* temperature */
  124. MV_DDR_TIM_DEFAULT} }, /* timing */
  125. BUS_MASK_32BIT, /* Busses mask */
  126. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  127. NOT_COMBINED, /* ddr twin-die combined */
  128. { {0} }, /* raw spd data */
  129. {0}, /* timing parameters */
  130. { {0} }, /* electrical configuration */
  131. {0,}, /* electrical parameters */
  132. 0x3, /* clock enable mask */
  133. };
  134. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  135. {
  136. struct if_params *ifp = &board_topology_map.interface_params[0];
  137. cf_read_tlv_data();
  138. switch (cf_tlv_data.ram_size) {
  139. case 4:
  140. default:
  141. ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
  142. break;
  143. case 8:
  144. ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
  145. break;
  146. }
  147. /* Return the board topology as defined in the board code */
  148. return &board_topology_map;
  149. }
  150. int board_early_init_f(void)
  151. {
  152. /* Configure MPP */
  153. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  154. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  155. writel(0x10400011, MVEBU_MPP_BASE + 0x08);
  156. writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
  157. writel(0x44400002, MVEBU_MPP_BASE + 0x10);
  158. writel(0x41144004, MVEBU_MPP_BASE + 0x14);
  159. writel(0x40333333, MVEBU_MPP_BASE + 0x18);
  160. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  161. /* Set GPP Out value */
  162. writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  163. writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  164. /* Set GPP Polarity */
  165. writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  166. writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  167. /* Set GPP Out Enable */
  168. writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  169. writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  170. return 0;
  171. }
  172. int board_init(void)
  173. {
  174. /* Address of boot parameters */
  175. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  176. /* Toggle GPIO41 to reset onboard switch and phy */
  177. clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  178. clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
  179. /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
  180. clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  181. clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
  182. mdelay(1);
  183. setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  184. setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  185. mdelay(10);
  186. return 0;
  187. }
  188. int checkboard(void)
  189. {
  190. char *board = "Clearfog Pro";
  191. if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
  192. board = "Clearfog Base";
  193. cf_read_tlv_data();
  194. if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
  195. board = cf_tlv_data.tlv_product_name[0];
  196. printf("Board: SolidRun %s", board);
  197. if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
  198. printf(", %s", cf_tlv_data.tlv_product_name[1]);
  199. puts("\n");
  200. return 0;
  201. }
  202. int board_eth_init(struct bd_info *bis)
  203. {
  204. cpu_eth_init(bis); /* Built in controller(s) come first */
  205. return pci_eth_init(bis);
  206. }
  207. int board_late_init(void)
  208. {
  209. if (env_get("fdtfile"))
  210. return 0;
  211. cf_read_tlv_data();
  212. if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
  213. env_set("fdtfile", "armada-388-clearfog-base.dtb");
  214. else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
  215. env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
  216. else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
  217. env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
  218. else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
  219. env_set("fdtfile", "armada-388-clearfog-base.dtb");
  220. else
  221. env_set("fdtfile", "armada-388-clearfog-pro.dtb");
  222. return 0;
  223. }