x530.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Allied Telesis Labs
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <dm.h>
  8. #include <env.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <wdt.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <linux/bitops.h>
  15. #include <linux/mbus.h>
  16. #include <linux/io.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include "../common/gpio_hog.h"
  20. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  21. #include <../serdes/a38x/high_speed_env_spec.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
  24. #define CONFIG_NVS_LOCATION 0xf4800000
  25. #define CONFIG_NVS_SIZE (512 << 10)
  26. static struct serdes_map board_serdes_map[] = {
  27. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  28. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  29. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  30. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  31. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  32. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  33. };
  34. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  35. {
  36. *serdes_map_array = board_serdes_map;
  37. *count = ARRAY_SIZE(board_serdes_map);
  38. return 0;
  39. }
  40. /*
  41. * Define the DDR layout / topology here in the board file. This will
  42. * be used by the DDR3 init code in the SPL U-Boot version to configure
  43. * the DDR3 controller.
  44. */
  45. static struct mv_ddr_topology_map board_topology_map = {
  46. DEBUG_LEVEL_ERROR,
  47. 0x1, /* active interfaces */
  48. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  49. { { { {0x1, 0, 0, 0},
  50. {0x1, 0, 0, 0},
  51. {0x1, 0, 0, 0},
  52. {0x1, 0, 0, 0},
  53. {0x1, 0, 0, 0} },
  54. SPEED_BIN_DDR_1866M, /* speed_bin */
  55. MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
  56. MV_DDR_DIE_CAP_4GBIT, /* die capacity */
  57. MV_DDR_FREQ_SAR, /* frequency */
  58. 0, 0, /* cas_l cas_wl */
  59. MV_DDR_TEMP_LOW, /* temperature */
  60. MV_DDR_TIM_2T} }, /* timing */
  61. BUS_MASK_32BIT_ECC, /* subphys mask */
  62. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  63. NOT_COMBINED, /* ddr twin-die combined */
  64. { {0} }, /* raw spd data */
  65. {0}, /* timing parameters */
  66. { {0} }, /* electrical configuration */
  67. {0}, /* electrical parameters */
  68. 0, /* Clock enable mask */
  69. 160 /* Clock delay */
  70. };
  71. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  72. {
  73. /* Return the board topology as defined in the board code */
  74. return &board_topology_map;
  75. }
  76. int board_early_init_f(void)
  77. {
  78. /* Configure MPP */
  79. writel(0x00001111, MVEBU_MPP_BASE + 0x00);
  80. writel(0x00000000, MVEBU_MPP_BASE + 0x04);
  81. writel(0x55000000, MVEBU_MPP_BASE + 0x08);
  82. writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
  83. writel(0x55555555, MVEBU_MPP_BASE + 0x10);
  84. writel(0x00100565, MVEBU_MPP_BASE + 0x14);
  85. writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  86. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  87. return 0;
  88. }
  89. void spl_board_init(void)
  90. {
  91. }
  92. int board_init(void)
  93. {
  94. /* address of boot parameters */
  95. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  96. /* window for NVS */
  97. mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
  98. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
  99. /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
  100. writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
  101. spl_board_init();
  102. return 0;
  103. }
  104. void arch_preboot_os(void)
  105. {
  106. #ifdef CONFIG_WATCHDOG
  107. wdt_stop(gd->watchdog_dev);
  108. #endif
  109. }
  110. static int led_7seg_init(unsigned int segments)
  111. {
  112. int node;
  113. int ret;
  114. int i;
  115. struct gpio_desc desc[8];
  116. node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
  117. "atl,of-led-7seg");
  118. if (node < 0)
  119. return -ENODEV;
  120. ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
  121. "segment-gpios", desc,
  122. ARRAY_SIZE(desc), GPIOD_IS_OUT);
  123. if (ret < 0)
  124. return ret;
  125. for (i = 0; i < ARRAY_SIZE(desc); i++) {
  126. ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
  127. if (ret)
  128. return ret;
  129. }
  130. return 0;
  131. }
  132. #ifdef CONFIG_MISC_INIT_R
  133. int misc_init_r(void)
  134. {
  135. static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
  136. led_en = {};
  137. gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
  138. gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
  139. gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
  140. gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
  141. #ifdef MTDPARTS_MTDOOPS
  142. env_set("mtdoops", MTDPARTS_MTDOOPS);
  143. #endif
  144. led_7seg_init(0xff);
  145. return 0;
  146. }
  147. #endif
  148. #ifdef CONFIG_DISPLAY_BOARDINFO
  149. int checkboard(void)
  150. {
  151. puts("Board: " CONFIG_SYS_BOARD "\n");
  152. return 0;
  153. }
  154. #endif