db-88f6820-gp.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include <linux/bitops.h>
  16. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  17. #include <../serdes/a38x/high_speed_env_spec.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * Those values and defines are taken from the Marvell U-Boot version
  21. * "u-boot-2013.01-2014_T3.0"
  22. */
  23. #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
  24. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  25. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  26. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  27. #define DB_GP_88F68XX_GPP_OUT_ENA_MID \
  28. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  29. BIT(16) | BIT(17) | BIT(18)))
  30. #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
  31. #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
  32. #define DB_GP_88F68XX_GPP_POL_LOW 0x0
  33. #define DB_GP_88F68XX_GPP_POL_MID 0x0
  34. /* IO expander on Marvell GP board includes e.g. fan enabling */
  35. struct marvell_io_exp {
  36. u8 chip;
  37. u8 addr;
  38. u8 val;
  39. };
  40. static struct marvell_io_exp io_exp[] = {
  41. { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  42. { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  43. { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  44. { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  45. { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  46. { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
  47. { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  48. { 0x21, 3, 0xC0 } /* Output Data, register#1 */
  49. };
  50. static struct serdes_map board_serdes_map[] = {
  51. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  52. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  53. {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  54. {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  55. {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  56. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  57. };
  58. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  59. {
  60. *serdes_map_array = board_serdes_map;
  61. *count = ARRAY_SIZE(board_serdes_map);
  62. return 0;
  63. }
  64. /*
  65. * Define the DDR layout / topology here in the board file. This will
  66. * be used by the DDR3 init code in the SPL U-Boot version to configure
  67. * the DDR3 controller.
  68. */
  69. static struct mv_ddr_topology_map board_topology_map = {
  70. DEBUG_LEVEL_ERROR,
  71. 0x1, /* active interfaces */
  72. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  73. { { { {0x1, 0, 0, 0},
  74. {0x1, 0, 0, 0},
  75. {0x1, 0, 0, 0},
  76. {0x1, 0, 0, 0},
  77. {0x1, 0, 0, 0} },
  78. SPEED_BIN_DDR_1866L, /* speed_bin */
  79. MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
  80. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  81. MV_DDR_FREQ_800, /* frequency */
  82. 0, 0, /* cas_wl cas_l */
  83. MV_DDR_TEMP_LOW, /* temperature */
  84. MV_DDR_TIM_DEFAULT} }, /* timing */
  85. BUS_MASK_32BIT, /* Busses mask */
  86. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  87. NOT_COMBINED, /* ddr twin-die combined */
  88. { {0} }, /* raw spd data */
  89. {0} /* timing parameters */
  90. };
  91. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  92. {
  93. /* Return the board topology as defined in the board code */
  94. return &board_topology_map;
  95. }
  96. int board_early_init_f(void)
  97. {
  98. /* Configure MPP */
  99. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  100. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  101. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  102. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  103. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  104. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  105. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  106. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  107. /* Set GPP Out value */
  108. writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  109. writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  110. /* Set GPP Polarity */
  111. writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  112. writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  113. /* Set GPP Out Enable */
  114. writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  115. writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  116. return 0;
  117. }
  118. int board_init(void)
  119. {
  120. int i;
  121. /* adress of boot parameters */
  122. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  123. /* Init I2C IO expanders */
  124. for (i = 0; i < ARRAY_SIZE(io_exp); i++)
  125. i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
  126. return 0;
  127. }
  128. int checkboard(void)
  129. {
  130. puts("Board: Marvell DB-88F6820-GP\n");
  131. return 0;
  132. }
  133. int board_eth_init(struct bd_info *bis)
  134. {
  135. cpu_eth_init(bis); /* Built in controller(s) come first */
  136. return pci_eth_init(bis);
  137. }