pci_mmc.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Google, Inc
  4. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <mapmem.h>
  12. #include <mmc.h>
  13. #include <sdhci.h>
  14. #include <acpi/acpigen.h>
  15. #include <acpi/acpi_device.h>
  16. #include <acpi/acpi_dp.h>
  17. #include <asm-generic/gpio.h>
  18. #include <dm/acpi.h>
  19. /* Type of MMC device */
  20. enum {
  21. TYPE_SD,
  22. TYPE_EMMC,
  23. };
  24. struct pci_mmc_plat {
  25. struct mmc_config cfg;
  26. struct mmc mmc;
  27. };
  28. struct pci_mmc_priv {
  29. struct sdhci_host host;
  30. void *base;
  31. struct gpio_desc cd_gpio;
  32. };
  33. static int pci_mmc_probe(struct udevice *dev)
  34. {
  35. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  36. struct pci_mmc_plat *plat = dev_get_plat(dev);
  37. struct pci_mmc_priv *priv = dev_get_priv(dev);
  38. struct sdhci_host *host = &priv->host;
  39. struct blk_desc *desc;
  40. int ret;
  41. ret = mmc_of_parse(dev, &plat->cfg);
  42. if (ret)
  43. return ret;
  44. desc = mmc_get_blk_desc(&plat->mmc);
  45. desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
  46. host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
  47. PCI_REGION_MEM);
  48. host->name = dev->name;
  49. host->cd_gpio = priv->cd_gpio;
  50. host->mmc = &plat->mmc;
  51. host->mmc->dev = dev;
  52. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  53. if (ret)
  54. return ret;
  55. host->mmc->priv = &priv->host;
  56. upriv->mmc = host->mmc;
  57. return sdhci_probe(dev);
  58. }
  59. static int pci_mmc_of_to_plat(struct udevice *dev)
  60. {
  61. if (CONFIG_IS_ENABLED(DM_GPIO)) {
  62. struct pci_mmc_priv *priv = dev_get_priv(dev);
  63. int ret;
  64. ret = gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  65. GPIOD_IS_IN);
  66. log_debug("cd-gpio %s done, ret=%d\n", dev->name, ret);
  67. }
  68. return 0;
  69. }
  70. static int pci_mmc_bind(struct udevice *dev)
  71. {
  72. struct pci_mmc_plat *plat = dev_get_plat(dev);
  73. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  74. }
  75. static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
  76. struct acpi_ctx *ctx)
  77. {
  78. struct pci_mmc_priv *priv = dev_get_priv(dev);
  79. char path[ACPI_PATH_MAX];
  80. struct acpi_gpio gpio;
  81. struct acpi_dp *dp;
  82. int ret;
  83. if (!dev_has_ofnode(dev))
  84. return 0;
  85. if (dev_get_driver_data(dev) == TYPE_EMMC)
  86. return 0;
  87. ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
  88. if (ret)
  89. return log_msg_ret("gpio", ret);
  90. gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
  91. gpio.pull = ACPI_GPIO_PULL_NONE;
  92. gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
  93. gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
  94. gpio.irq.shared = ACPI_IRQ_SHARED;
  95. gpio.irq.wake = ACPI_IRQ_WAKE;
  96. gpio.interrupt_debounce_timeout = 10000; /* 100ms */
  97. /* Use device path as the Scope for the SSDT */
  98. ret = acpi_device_path(dev, path, sizeof(path));
  99. if (ret)
  100. return log_msg_ret("path", ret);
  101. acpigen_write_scope(ctx, path);
  102. acpigen_write_name(ctx, "_CRS");
  103. /* Write GpioInt() as default (if set) or custom from devicetree */
  104. acpigen_write_resourcetemplate_header(ctx);
  105. acpi_device_write_gpio(ctx, &gpio);
  106. acpigen_write_resourcetemplate_footer(ctx);
  107. /* Bind the cd-gpio name to the GpioInt() resource */
  108. dp = acpi_dp_new_table("_DSD");
  109. if (!dp)
  110. return -ENOMEM;
  111. acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
  112. ret = acpi_dp_write(ctx, dp);
  113. if (ret)
  114. return log_msg_ret("cd", ret);
  115. acpigen_pop_len(ctx);
  116. return 0;
  117. }
  118. struct acpi_ops pci_mmc_acpi_ops = {
  119. .fill_ssdt = pci_mmc_acpi_fill_ssdt,
  120. };
  121. static const struct udevice_id pci_mmc_match[] = {
  122. { .compatible = "intel,apl-sd", .data = TYPE_SD },
  123. { .compatible = "intel,apl-emmc", .data = TYPE_EMMC },
  124. { }
  125. };
  126. U_BOOT_DRIVER(pci_mmc) = {
  127. .name = "pci_mmc",
  128. .id = UCLASS_MMC,
  129. .of_match = pci_mmc_match,
  130. .bind = pci_mmc_bind,
  131. .of_to_plat = pci_mmc_of_to_plat,
  132. .probe = pci_mmc_probe,
  133. .ops = &sdhci_ops,
  134. .priv_auto = sizeof(struct pci_mmc_priv),
  135. .plat_auto = sizeof(struct pci_mmc_plat),
  136. ACPI_OPS_PTR(&pci_mmc_acpi_ops)
  137. };
  138. static struct pci_device_id mmc_supported[] = {
  139. { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDHCI << 8, 0xffff00) },
  140. {},
  141. };
  142. U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);