g12a.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/clock-g12a.h>
  10. #include <asm/io.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <div64.h>
  16. #include <dt-bindings/clock/g12a-clkc.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. #include <linux/kernel.h>
  21. #include "clk_meson.h"
  22. /* This driver support only basic clock tree operations :
  23. * - Can calculate clock frequency on a limited tree
  24. * - Can Read muxes and basic dividers (0-based only)
  25. * - Can enable/disable gates with limited propagation
  26. * - Can reparent without propagation, only on muxes
  27. * - Can set rates without reparenting
  28. * This driver is adapted to what is actually supported by U-Boot
  29. */
  30. /* Only the clocks ids we don't want to expose, such as the internal muxes
  31. * and dividers of composite clocks, will remain defined here.
  32. */
  33. #define CLKID_MPEG_SEL 8
  34. #define CLKID_MPEG_DIV 9
  35. #define CLKID_SD_EMMC_A_CLK0_SEL 63
  36. #define CLKID_SD_EMMC_A_CLK0_DIV 64
  37. #define CLKID_SD_EMMC_B_CLK0_SEL 65
  38. #define CLKID_SD_EMMC_B_CLK0_DIV 66
  39. #define CLKID_SD_EMMC_C_CLK0_SEL 67
  40. #define CLKID_SD_EMMC_C_CLK0_DIV 68
  41. #define CLKID_MPLL0_DIV 69
  42. #define CLKID_MPLL1_DIV 70
  43. #define CLKID_MPLL2_DIV 71
  44. #define CLKID_MPLL3_DIV 72
  45. #define CLKID_MPLL_PREDIV 73
  46. #define CLKID_FCLK_DIV2_DIV 75
  47. #define CLKID_FCLK_DIV3_DIV 76
  48. #define CLKID_FCLK_DIV4_DIV 77
  49. #define CLKID_FCLK_DIV5_DIV 78
  50. #define CLKID_FCLK_DIV7_DIV 79
  51. #define CLKID_FCLK_DIV2P5_DIV 100
  52. #define CLKID_FIXED_PLL_DCO 101
  53. #define CLKID_SYS_PLL_DCO 102
  54. #define CLKID_GP0_PLL_DCO 103
  55. #define CLKID_HIFI_PLL_DCO 104
  56. #define CLKID_VPU_0_DIV 111
  57. #define CLKID_VPU_1_DIV 114
  58. #define CLKID_VAPB_0_DIV 118
  59. #define CLKID_VAPB_1_DIV 121
  60. #define CLKID_HDMI_PLL_DCO 125
  61. #define CLKID_HDMI_PLL_OD 126
  62. #define CLKID_HDMI_PLL_OD2 127
  63. #define CLKID_VID_PLL_SEL 130
  64. #define CLKID_VID_PLL_DIV 131
  65. #define CLKID_VCLK_SEL 132
  66. #define CLKID_VCLK2_SEL 133
  67. #define CLKID_VCLK_INPUT 134
  68. #define CLKID_VCLK2_INPUT 135
  69. #define CLKID_VCLK_DIV 136
  70. #define CLKID_VCLK2_DIV 137
  71. #define CLKID_VCLK_DIV2_EN 140
  72. #define CLKID_VCLK_DIV4_EN 141
  73. #define CLKID_VCLK_DIV6_EN 142
  74. #define CLKID_VCLK_DIV12_EN 143
  75. #define CLKID_VCLK2_DIV2_EN 144
  76. #define CLKID_VCLK2_DIV4_EN 145
  77. #define CLKID_VCLK2_DIV6_EN 146
  78. #define CLKID_VCLK2_DIV12_EN 147
  79. #define CLKID_CTS_ENCI_SEL 158
  80. #define CLKID_CTS_ENCP_SEL 159
  81. #define CLKID_CTS_VDAC_SEL 160
  82. #define CLKID_HDMI_TX_SEL 161
  83. #define CLKID_HDMI_SEL 166
  84. #define CLKID_HDMI_DIV 167
  85. #define CLKID_MALI_0_DIV 170
  86. #define CLKID_MALI_1_DIV 173
  87. #define CLKID_XTAL 0x10000000
  88. #define XTAL_RATE 24000000
  89. struct meson_clk {
  90. struct regmap *map;
  91. };
  92. static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  93. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  94. ulong current_rate);
  95. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  96. unsigned long parent_id);
  97. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  98. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  99. ulong rate, ulong current_rate);
  100. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  101. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  102. #define NUM_CLKS 178
  103. static struct meson_gate gates[NUM_CLKS] = {
  104. /* Everything Else (EE) domain gates */
  105. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  106. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  107. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  108. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
  109. MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
  110. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  111. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  112. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  113. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  114. MESON_GATE(CLKID_PCIE_COMB, HHI_GCLK_MPEG1, 24),
  115. MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
  116. MESON_GATE(CLKID_PCIE_PHY, HHI_GCLK_MPEG1, 27),
  117. MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
  118. MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
  119. MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
  120. /* Peripheral Gates */
  121. MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
  122. MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
  123. MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
  124. MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
  125. MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
  126. MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
  127. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  128. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  129. MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
  130. MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
  131. MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
  132. MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
  133. MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
  134. MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8),
  135. };
  136. static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
  137. {
  138. struct meson_clk *priv = dev_get_priv(clk->dev);
  139. struct meson_gate *gate;
  140. debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
  141. /* Propagate through muxes */
  142. switch (id) {
  143. case CLKID_VPU:
  144. return meson_set_gate_by_id(clk,
  145. meson_mux_get_parent(clk, CLKID_VPU), on);
  146. case CLKID_VAPB_SEL:
  147. return meson_set_gate_by_id(clk,
  148. meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
  149. }
  150. if (id >= ARRAY_SIZE(gates))
  151. return -ENOENT;
  152. gate = &gates[id];
  153. if (gate->reg == 0)
  154. return 0;
  155. debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
  156. regmap_update_bits(priv->map, gate->reg,
  157. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  158. /* Propagate to next gate(s) */
  159. switch (id) {
  160. case CLKID_VAPB:
  161. return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
  162. case CLKID_VAPB_0:
  163. return meson_set_gate_by_id(clk,
  164. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  165. case CLKID_VAPB_1:
  166. return meson_set_gate_by_id(clk,
  167. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  168. case CLKID_VPU_0:
  169. return meson_set_gate_by_id(clk,
  170. meson_mux_get_parent(clk, CLKID_VPU_0_SEL), on);
  171. case CLKID_VPU_1:
  172. return meson_set_gate_by_id(clk,
  173. meson_mux_get_parent(clk, CLKID_VPU_1_SEL), on);
  174. }
  175. return 0;
  176. }
  177. static int meson_clk_enable(struct clk *clk)
  178. {
  179. return meson_set_gate_by_id(clk, clk->id, true);
  180. }
  181. static int meson_clk_disable(struct clk *clk)
  182. {
  183. return meson_set_gate_by_id(clk, clk->id, false);
  184. }
  185. static struct parm meson_vpu_0_div_parm = {
  186. HHI_VPU_CLK_CNTL, 0, 7,
  187. };
  188. int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
  189. static struct parm meson_vpu_1_div_parm = {
  190. HHI_VPU_CLK_CNTL, 16, 7,
  191. };
  192. int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
  193. static struct parm meson_vapb_0_div_parm = {
  194. HHI_VAPBCLK_CNTL, 0, 7,
  195. };
  196. int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
  197. static struct parm meson_vapb_1_div_parm = {
  198. HHI_VAPBCLK_CNTL, 16, 7,
  199. };
  200. int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
  201. static struct parm meson_hdmi_div_parm = {
  202. HHI_HDMI_CLK_CNTL, 0, 7,
  203. };
  204. int meson_hdmi_div_parent = CLKID_HDMI_SEL;
  205. static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
  206. {
  207. struct meson_clk *priv = dev_get_priv(clk->dev);
  208. unsigned int rate, parent_rate;
  209. struct parm *parm;
  210. int parent;
  211. uint reg;
  212. switch (id) {
  213. case CLKID_VPU_0_DIV:
  214. parm = &meson_vpu_0_div_parm;
  215. parent = meson_vpu_0_div_parent;
  216. break;
  217. case CLKID_VPU_1_DIV:
  218. parm = &meson_vpu_1_div_parm;
  219. parent = meson_vpu_1_div_parent;
  220. break;
  221. case CLKID_VAPB_0_DIV:
  222. parm = &meson_vapb_0_div_parm;
  223. parent = meson_vapb_0_div_parent;
  224. break;
  225. case CLKID_VAPB_1_DIV:
  226. parm = &meson_vapb_1_div_parm;
  227. parent = meson_vapb_1_div_parent;
  228. break;
  229. case CLKID_HDMI_DIV:
  230. parm = &meson_hdmi_div_parm;
  231. parent = meson_hdmi_div_parent;
  232. break;
  233. default:
  234. return -ENOENT;
  235. }
  236. regmap_read(priv->map, parm->reg_off, &reg);
  237. reg = PARM_GET(parm->width, parm->shift, reg);
  238. debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
  239. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  240. if (IS_ERR_VALUE(parent_rate))
  241. return parent_rate;
  242. debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
  243. rate = parent_rate / (reg + 1);
  244. debug("%s: rate of %ld is %d\n", __func__, id, rate);
  245. return rate;
  246. }
  247. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  248. ulong current_rate)
  249. {
  250. struct meson_clk *priv = dev_get_priv(clk->dev);
  251. unsigned int new_div = -EINVAL;
  252. unsigned long parent_rate;
  253. struct parm *parm;
  254. int parent;
  255. int ret;
  256. if (current_rate == rate)
  257. return 0;
  258. debug("%s: setting rate of %ld from %ld to %ld\n",
  259. __func__, id, current_rate, rate);
  260. switch (id) {
  261. case CLKID_VPU_0_DIV:
  262. parm = &meson_vpu_0_div_parm;
  263. parent = meson_vpu_0_div_parent;
  264. break;
  265. case CLKID_VPU_1_DIV:
  266. parm = &meson_vpu_1_div_parm;
  267. parent = meson_vpu_1_div_parent;
  268. break;
  269. case CLKID_VAPB_0_DIV:
  270. parm = &meson_vapb_0_div_parm;
  271. parent = meson_vapb_0_div_parent;
  272. break;
  273. case CLKID_VAPB_1_DIV:
  274. parm = &meson_vapb_1_div_parm;
  275. parent = meson_vapb_1_div_parent;
  276. break;
  277. case CLKID_HDMI_DIV:
  278. parm = &meson_hdmi_div_parm;
  279. parent = meson_hdmi_div_parent;
  280. break;
  281. default:
  282. return -ENOENT;
  283. }
  284. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  285. if (IS_ERR_VALUE(parent_rate))
  286. return parent_rate;
  287. debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
  288. /* If can't divide, set parent instead */
  289. if (!parent_rate || rate > parent_rate)
  290. return meson_clk_set_rate_by_id(clk, parent, rate,
  291. current_rate);
  292. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  293. debug("%s: new div of %ld is %d\n", __func__, id, new_div);
  294. /* If overflow, try to set parent rate and retry */
  295. if (!new_div || new_div > (1 << parm->width)) {
  296. ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
  297. if (IS_ERR_VALUE(ret))
  298. return ret;
  299. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  300. if (IS_ERR_VALUE(parent_rate))
  301. return parent_rate;
  302. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  303. debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
  304. if (!new_div || new_div > (1 << parm->width))
  305. return -EINVAL;
  306. }
  307. debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
  308. regmap_update_bits(priv->map, parm->reg_off,
  309. SETPMASK(parm->width, parm->shift),
  310. (new_div - 1) << parm->shift);
  311. debug("%s: new rate of %ld is %ld\n",
  312. __func__, id, meson_div_get_rate(clk, id));
  313. return 0;
  314. }
  315. static struct parm meson_vpu_mux_parm = {
  316. HHI_VPU_CLK_CNTL, 31, 1,
  317. };
  318. int meson_vpu_mux_parents[] = {
  319. CLKID_VPU_0,
  320. CLKID_VPU_1,
  321. };
  322. static struct parm meson_vpu_0_mux_parm = {
  323. HHI_VPU_CLK_CNTL, 9, 3,
  324. };
  325. static struct parm meson_vpu_1_mux_parm = {
  326. HHI_VPU_CLK_CNTL, 25, 3,
  327. };
  328. static int meson_vpu_0_1_mux_parents[] = {
  329. CLKID_FCLK_DIV3,
  330. CLKID_FCLK_DIV4,
  331. CLKID_FCLK_DIV5,
  332. CLKID_FCLK_DIV7,
  333. -ENOENT,
  334. -ENOENT,
  335. -ENOENT,
  336. -ENOENT,
  337. };
  338. static struct parm meson_vapb_sel_mux_parm = {
  339. HHI_VAPBCLK_CNTL, 31, 1,
  340. };
  341. int meson_vapb_sel_mux_parents[] = {
  342. CLKID_VAPB_0,
  343. CLKID_VAPB_1,
  344. };
  345. static struct parm meson_vapb_0_mux_parm = {
  346. HHI_VAPBCLK_CNTL, 9, 2,
  347. };
  348. static struct parm meson_vapb_1_mux_parm = {
  349. HHI_VAPBCLK_CNTL, 25, 2,
  350. };
  351. static int meson_vapb_0_1_mux_parents[] = {
  352. CLKID_FCLK_DIV4,
  353. CLKID_FCLK_DIV3,
  354. CLKID_FCLK_DIV5,
  355. CLKID_FCLK_DIV7,
  356. };
  357. static struct parm meson_hdmi_mux_parm = {
  358. HHI_HDMI_CLK_CNTL, 9, 2,
  359. };
  360. static int meson_hdmi_mux_parents[] = {
  361. CLKID_XTAL,
  362. CLKID_FCLK_DIV4,
  363. CLKID_FCLK_DIV3,
  364. CLKID_FCLK_DIV5,
  365. };
  366. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
  367. {
  368. struct meson_clk *priv = dev_get_priv(clk->dev);
  369. struct parm *parm;
  370. int *parents;
  371. uint reg;
  372. switch (id) {
  373. case CLKID_VPU:
  374. parm = &meson_vpu_mux_parm;
  375. parents = meson_vpu_mux_parents;
  376. break;
  377. case CLKID_VPU_0_SEL:
  378. parm = &meson_vpu_0_mux_parm;
  379. parents = meson_vpu_0_1_mux_parents;
  380. break;
  381. case CLKID_VPU_1_SEL:
  382. parm = &meson_vpu_1_mux_parm;
  383. parents = meson_vpu_0_1_mux_parents;
  384. break;
  385. case CLKID_VAPB_SEL:
  386. parm = &meson_vapb_sel_mux_parm;
  387. parents = meson_vapb_sel_mux_parents;
  388. break;
  389. case CLKID_VAPB_0_SEL:
  390. parm = &meson_vapb_0_mux_parm;
  391. parents = meson_vapb_0_1_mux_parents;
  392. break;
  393. case CLKID_VAPB_1_SEL:
  394. parm = &meson_vapb_1_mux_parm;
  395. parents = meson_vapb_0_1_mux_parents;
  396. break;
  397. case CLKID_HDMI_SEL:
  398. parm = &meson_hdmi_mux_parm;
  399. parents = meson_hdmi_mux_parents;
  400. break;
  401. default:
  402. return -ENOENT;
  403. }
  404. regmap_read(priv->map, parm->reg_off, &reg);
  405. reg = PARM_GET(parm->width, parm->shift, reg);
  406. debug("%s: parent of %ld is %d (%d)\n",
  407. __func__, id, parents[reg], reg);
  408. return parents[reg];
  409. }
  410. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  411. unsigned long parent_id)
  412. {
  413. unsigned long cur_parent = meson_mux_get_parent(clk, id);
  414. struct meson_clk *priv = dev_get_priv(clk->dev);
  415. unsigned int new_index = -EINVAL;
  416. struct parm *parm;
  417. int *parents;
  418. int i;
  419. if (IS_ERR_VALUE(cur_parent))
  420. return cur_parent;
  421. debug("%s: setting parent of %ld from %ld to %ld\n",
  422. __func__, id, cur_parent, parent_id);
  423. if (cur_parent == parent_id)
  424. return 0;
  425. switch (id) {
  426. case CLKID_VPU:
  427. parm = &meson_vpu_mux_parm;
  428. parents = meson_vpu_mux_parents;
  429. break;
  430. case CLKID_VPU_0_SEL:
  431. parm = &meson_vpu_0_mux_parm;
  432. parents = meson_vpu_0_1_mux_parents;
  433. break;
  434. case CLKID_VPU_1_SEL:
  435. parm = &meson_vpu_1_mux_parm;
  436. parents = meson_vpu_0_1_mux_parents;
  437. break;
  438. case CLKID_VAPB_SEL:
  439. parm = &meson_vapb_sel_mux_parm;
  440. parents = meson_vapb_sel_mux_parents;
  441. break;
  442. case CLKID_VAPB_0_SEL:
  443. parm = &meson_vapb_0_mux_parm;
  444. parents = meson_vapb_0_1_mux_parents;
  445. break;
  446. case CLKID_VAPB_1_SEL:
  447. parm = &meson_vapb_1_mux_parm;
  448. parents = meson_vapb_0_1_mux_parents;
  449. break;
  450. case CLKID_HDMI_SEL:
  451. parm = &meson_hdmi_mux_parm;
  452. parents = meson_hdmi_mux_parents;
  453. break;
  454. default:
  455. /* Not a mux */
  456. return -ENOENT;
  457. }
  458. for (i = 0 ; i < (1 << parm->width) ; ++i) {
  459. if (parents[i] == parent_id)
  460. new_index = i;
  461. }
  462. if (IS_ERR_VALUE(new_index))
  463. return new_index;
  464. debug("%s: new index of %ld is %d\n", __func__, id, new_index);
  465. regmap_update_bits(priv->map, parm->reg_off,
  466. SETPMASK(parm->width, parm->shift),
  467. new_index << parm->shift);
  468. debug("%s: new parent of %ld is %ld\n",
  469. __func__, id, meson_mux_get_parent(clk, id));
  470. return 0;
  471. }
  472. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
  473. {
  474. int parent = meson_mux_get_parent(clk, id);
  475. if (IS_ERR_VALUE(parent))
  476. return parent;
  477. return meson_clk_get_rate_by_id(clk, parent);
  478. }
  479. static unsigned long meson_clk81_get_rate(struct clk *clk)
  480. {
  481. struct meson_clk *priv = dev_get_priv(clk->dev);
  482. unsigned long parent_rate;
  483. uint reg;
  484. int parents[] = {
  485. CLKID_XTAL,
  486. -1,
  487. CLKID_FCLK_DIV7,
  488. CLKID_MPLL1,
  489. CLKID_MPLL2,
  490. CLKID_FCLK_DIV4,
  491. CLKID_FCLK_DIV3,
  492. CLKID_FCLK_DIV5
  493. };
  494. /* mux */
  495. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  496. reg = (reg >> 12) & 7;
  497. switch (reg) {
  498. case 1:
  499. return -ENOENT;
  500. default:
  501. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  502. }
  503. /* divider */
  504. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  505. reg = reg & ((1 << 7) - 1);
  506. return parent_rate / reg;
  507. }
  508. static long mpll_rate_from_params(unsigned long parent_rate,
  509. unsigned long sdm,
  510. unsigned long n2)
  511. {
  512. unsigned long divisor = (SDM_DEN * n2) + sdm;
  513. if (n2 < N2_MIN)
  514. return -EINVAL;
  515. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  516. }
  517. static struct parm meson_mpll0_parm[2] = {
  518. {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
  519. {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
  520. };
  521. static struct parm meson_mpll1_parm[2] = {
  522. {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
  523. {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
  524. };
  525. static struct parm meson_mpll2_parm[2] = {
  526. {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
  527. {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
  528. };
  529. /*
  530. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  531. * scaling capabilities. MPLL rates are calculated as:
  532. *
  533. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  534. */
  535. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  536. {
  537. struct meson_clk *priv = dev_get_priv(clk->dev);
  538. struct parm *psdm, *pn2;
  539. unsigned long sdm, n2;
  540. unsigned long parent_rate;
  541. uint reg;
  542. switch (id) {
  543. case CLKID_MPLL0:
  544. psdm = &meson_mpll0_parm[0];
  545. pn2 = &meson_mpll0_parm[1];
  546. break;
  547. case CLKID_MPLL1:
  548. psdm = &meson_mpll1_parm[0];
  549. pn2 = &meson_mpll1_parm[1];
  550. break;
  551. case CLKID_MPLL2:
  552. psdm = &meson_mpll2_parm[0];
  553. pn2 = &meson_mpll2_parm[1];
  554. break;
  555. default:
  556. return -ENOENT;
  557. }
  558. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  559. if (IS_ERR_VALUE(parent_rate))
  560. return parent_rate;
  561. regmap_read(priv->map, psdm->reg_off, &reg);
  562. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  563. regmap_read(priv->map, pn2->reg_off, &reg);
  564. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  565. return mpll_rate_from_params(parent_rate, sdm, n2);
  566. }
  567. static struct parm meson_fixed_pll_parm[4] = {
  568. {HHI_FIX_PLL_CNTL0, 0, 9}, /* pm */
  569. {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
  570. {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
  571. {HHI_FIX_PLL_CNTL1, 0, 17}, /* pfrac */
  572. };
  573. static struct parm meson_sys_pll_parm[3] = {
  574. {HHI_SYS_PLL_CNTL0, 0, 9}, /* pm */
  575. {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
  576. {HHI_SYS_PLL_CNTL0, 16, 3}, /* pod */
  577. };
  578. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  579. {
  580. struct meson_clk *priv = dev_get_priv(clk->dev);
  581. struct parm *pm, *pn, *pod, *pfrac = NULL;
  582. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  583. u16 n, m, od, frac;
  584. ulong rate;
  585. uint reg;
  586. /*
  587. * FIXME: Between the unit conversion and the missing frac, we know
  588. * rate will be slightly off ...
  589. */
  590. switch (id) {
  591. case CLKID_FIXED_PLL:
  592. pm = &meson_fixed_pll_parm[0];
  593. pn = &meson_fixed_pll_parm[1];
  594. pod = &meson_fixed_pll_parm[2];
  595. pfrac = &meson_fixed_pll_parm[3];
  596. break;
  597. case CLKID_SYS_PLL:
  598. pm = &meson_sys_pll_parm[0];
  599. pn = &meson_sys_pll_parm[1];
  600. pod = &meson_sys_pll_parm[2];
  601. break;
  602. default:
  603. return -ENOENT;
  604. }
  605. regmap_read(priv->map, pn->reg_off, &reg);
  606. n = PARM_GET(pn->width, pn->shift, reg);
  607. regmap_read(priv->map, pm->reg_off, &reg);
  608. m = PARM_GET(pm->width, pm->shift, reg);
  609. regmap_read(priv->map, pod->reg_off, &reg);
  610. od = PARM_GET(pod->width, pod->shift, reg);
  611. rate = parent_rate_mhz * m;
  612. if (pfrac) {
  613. ulong frac_rate;
  614. regmap_read(priv->map, pfrac->reg_off, &reg);
  615. frac = PARM_GET(pfrac->width - 1, pfrac->shift, reg);
  616. frac_rate = DIV_ROUND_UP_ULL((u64)parent_rate_mhz * frac,
  617. 1 << (pfrac->width - 2));
  618. if (frac & BIT(pfrac->width - 1))
  619. rate -= frac_rate;
  620. else
  621. rate += frac_rate;
  622. }
  623. return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
  624. }
  625. static struct parm meson_pcie_pll_parm[3] = {
  626. {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
  627. {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
  628. {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
  629. };
  630. static ulong meson_pcie_pll_get_rate(struct clk *clk)
  631. {
  632. struct meson_clk *priv = dev_get_priv(clk->dev);
  633. struct parm *pm, *pn, *pod;
  634. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  635. u16 n, m, od;
  636. uint reg;
  637. pm = &meson_pcie_pll_parm[0];
  638. pn = &meson_pcie_pll_parm[1];
  639. pod = &meson_pcie_pll_parm[2];
  640. regmap_read(priv->map, pn->reg_off, &reg);
  641. n = PARM_GET(pn->width, pn->shift, reg);
  642. regmap_read(priv->map, pm->reg_off, &reg);
  643. m = PARM_GET(pm->width, pm->shift, reg);
  644. regmap_read(priv->map, pod->reg_off, &reg);
  645. od = PARM_GET(pod->width, pod->shift, reg);
  646. return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
  647. }
  648. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  649. {
  650. ulong rate;
  651. switch (id) {
  652. case CLKID_XTAL:
  653. rate = XTAL_RATE;
  654. break;
  655. case CLKID_FIXED_PLL:
  656. case CLKID_SYS_PLL:
  657. rate = meson_pll_get_rate(clk, id);
  658. break;
  659. case CLKID_FCLK_DIV2:
  660. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  661. break;
  662. case CLKID_FCLK_DIV3:
  663. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  664. break;
  665. case CLKID_FCLK_DIV4:
  666. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  667. break;
  668. case CLKID_FCLK_DIV5:
  669. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  670. break;
  671. case CLKID_FCLK_DIV7:
  672. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  673. break;
  674. case CLKID_MPLL0:
  675. case CLKID_MPLL1:
  676. case CLKID_MPLL2:
  677. rate = meson_mpll_get_rate(clk, id);
  678. break;
  679. case CLKID_CLK81:
  680. rate = meson_clk81_get_rate(clk);
  681. break;
  682. case CLKID_PCIE_PLL:
  683. rate = meson_pcie_pll_get_rate(clk);
  684. break;
  685. case CLKID_VPU_0:
  686. rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
  687. break;
  688. case CLKID_VPU_1:
  689. rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
  690. break;
  691. case CLKID_VAPB:
  692. rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
  693. break;
  694. case CLKID_VAPB_0:
  695. rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
  696. break;
  697. case CLKID_VAPB_1:
  698. rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
  699. break;
  700. case CLKID_HDMI:
  701. rate = meson_div_get_rate(clk, CLKID_HDMI_DIV);
  702. break;
  703. case CLKID_VPU_0_DIV:
  704. case CLKID_VPU_1_DIV:
  705. case CLKID_VAPB_0_DIV:
  706. case CLKID_VAPB_1_DIV:
  707. case CLKID_HDMI_DIV:
  708. rate = meson_div_get_rate(clk, id);
  709. break;
  710. case CLKID_VPU:
  711. case CLKID_VPU_0_SEL:
  712. case CLKID_VPU_1_SEL:
  713. case CLKID_VAPB_SEL:
  714. case CLKID_VAPB_0_SEL:
  715. case CLKID_VAPB_1_SEL:
  716. case CLKID_HDMI_SEL:
  717. rate = meson_mux_get_rate(clk, id);
  718. break;
  719. default:
  720. if (gates[id].reg != 0) {
  721. /* a clock gate */
  722. rate = meson_clk81_get_rate(clk);
  723. break;
  724. }
  725. return -ENOENT;
  726. }
  727. debug("clock %lu has rate %lu\n", id, rate);
  728. return rate;
  729. }
  730. static ulong meson_clk_get_rate(struct clk *clk)
  731. {
  732. return meson_clk_get_rate_by_id(clk, clk->id);
  733. }
  734. static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
  735. {
  736. struct meson_clk *priv = dev_get_priv(clk->dev);
  737. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
  738. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
  739. regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
  740. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
  741. regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
  742. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
  743. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
  744. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
  745. udelay(20);
  746. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
  747. udelay(10);
  748. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
  749. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
  750. udelay(10);
  751. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
  752. regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
  753. 0x1f << 16, 9 << 16);
  754. return 100000000;
  755. }
  756. static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
  757. {
  758. return meson_mux_set_parent(clk, clk->id, parent->id);
  759. }
  760. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  761. ulong rate, ulong current_rate)
  762. {
  763. if (current_rate == rate)
  764. return 0;
  765. switch (id) {
  766. /* Fixed clocks */
  767. case CLKID_FIXED_PLL:
  768. case CLKID_SYS_PLL:
  769. case CLKID_FCLK_DIV2:
  770. case CLKID_FCLK_DIV3:
  771. case CLKID_FCLK_DIV4:
  772. case CLKID_FCLK_DIV5:
  773. case CLKID_FCLK_DIV7:
  774. case CLKID_MPLL0:
  775. case CLKID_MPLL1:
  776. case CLKID_MPLL2:
  777. case CLKID_CLK81:
  778. if (current_rate != rate)
  779. return -EINVAL;
  780. case CLKID_PCIE_PLL:
  781. return meson_pcie_pll_set_rate(clk, rate);
  782. return 0;
  783. case CLKID_VPU:
  784. return meson_clk_set_rate_by_id(clk,
  785. meson_mux_get_parent(clk, CLKID_VPU), rate,
  786. current_rate);
  787. case CLKID_VAPB:
  788. case CLKID_VAPB_SEL:
  789. return meson_clk_set_rate_by_id(clk,
  790. meson_mux_get_parent(clk, CLKID_VAPB_SEL),
  791. rate, current_rate);
  792. case CLKID_VPU_0:
  793. return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
  794. current_rate);
  795. case CLKID_VPU_1:
  796. return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
  797. current_rate);
  798. case CLKID_VAPB_0:
  799. return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
  800. current_rate);
  801. case CLKID_VAPB_1:
  802. return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
  803. current_rate);
  804. case CLKID_VPU_0_DIV:
  805. case CLKID_VPU_1_DIV:
  806. case CLKID_VAPB_0_DIV:
  807. case CLKID_VAPB_1_DIV:
  808. case CLKID_HDMI_DIV:
  809. return meson_div_set_rate(clk, id, rate, current_rate);
  810. case CLKID_HDMI:
  811. return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV,
  812. rate, current_rate);
  813. default:
  814. return -ENOENT;
  815. }
  816. return -EINVAL;
  817. }
  818. static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
  819. {
  820. ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
  821. int ret;
  822. if (IS_ERR_VALUE(current_rate))
  823. return current_rate;
  824. debug("%s: setting rate of %ld from %ld to %ld\n",
  825. __func__, clk->id, current_rate, rate);
  826. ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
  827. if (IS_ERR_VALUE(ret))
  828. return ret;
  829. debug("clock %lu has new rate %lu\n", clk->id,
  830. meson_clk_get_rate_by_id(clk, clk->id));
  831. return 0;
  832. }
  833. static int meson_clk_probe(struct udevice *dev)
  834. {
  835. struct meson_clk *priv = dev_get_priv(dev);
  836. priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
  837. if (IS_ERR(priv->map))
  838. return PTR_ERR(priv->map);
  839. /*
  840. * Depending on the boot src, the state of the MMC clock might
  841. * be different. Reset it to make sure we won't get stuck
  842. */
  843. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  844. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  845. debug("meson-clk-g12a: probed\n");
  846. return 0;
  847. }
  848. static struct clk_ops meson_clk_ops = {
  849. .disable = meson_clk_disable,
  850. .enable = meson_clk_enable,
  851. .get_rate = meson_clk_get_rate,
  852. .set_parent = meson_clk_set_parent,
  853. .set_rate = meson_clk_set_rate,
  854. };
  855. static const struct udevice_id meson_clk_ids[] = {
  856. { .compatible = "amlogic,g12a-clkc" },
  857. { .compatible = "amlogic,g12b-clkc" },
  858. { .compatible = "amlogic,sm1-clkc" },
  859. { }
  860. };
  861. U_BOOT_DRIVER(meson_clk_g12a) = {
  862. .name = "meson_clk_g12a",
  863. .id = UCLASS_CLK,
  864. .of_match = meson_clk_ids,
  865. .priv_auto = sizeof(struct meson_clk),
  866. .ops = &meson_clk_ops,
  867. .probe = meson_clk_probe,
  868. };