eth_b4860qds.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. * Author: Sandeep Kumar Singh <sandeep@freescale.com>
  5. */
  6. /* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
  7. /*
  8. * This file handles the board muxing between the Fman Ethernet MACs and
  9. * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
  10. * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
  11. * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
  12. * one Fman device on B4860. The SERDES configuration is used to determine
  13. * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
  14. * to which PHYs. So for a given Fman MAC, there is one and only PHY it
  15. * connects to. MACs cannot be routed to PHYs dynamically. This configuration
  16. * is done at boot time by reading SERDES protocol from RCW.
  17. */
  18. #include <common.h>
  19. #include <log.h>
  20. #include <net.h>
  21. #include <netdev.h>
  22. #include <asm/fsl_serdes.h>
  23. #include <fm_eth.h>
  24. #include <fsl_mdio.h>
  25. #include <malloc.h>
  26. #include <fdt_support.h>
  27. #include <fsl_dtsec.h>
  28. #include "../common/ngpixis.h"
  29. #include "../common/fman.h"
  30. #include "../common/qixis.h"
  31. #include "b4860qds_qixis.h"
  32. #define EMI_NONE 0xFFFFFFFF
  33. #ifdef CONFIG_FMAN_ENET
  34. /*
  35. * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
  36. * lane at index is mapped to slot number n. A value of '0' will mean
  37. * that the mapping must be determined dynamically, or that the lane maps to
  38. * something other than a board slot
  39. */
  40. static u8 lane_to_slot[] = {
  41. 0, 0, 0, 0,
  42. 0, 0, 0, 0,
  43. 1, 1, 1, 1,
  44. 0, 0, 0, 0
  45. };
  46. /*
  47. * This function initializes the lane_to_slot[] array. It reads RCW to check
  48. * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
  49. * lane_to_slot[] accordingly
  50. */
  51. static void initialize_lane_to_slot(void)
  52. {
  53. unsigned int serdes2_prtcl;
  54. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  55. serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  56. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  57. serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  58. debug("Initializing lane to slot: Serdes2 protocol: %x\n",
  59. serdes2_prtcl);
  60. switch (serdes2_prtcl) {
  61. case 0x17:
  62. case 0x18:
  63. /*
  64. * Configuration:
  65. * SERDES: 2
  66. * Lanes: A,B,C,D: SGMII
  67. * Lanes: E,F: Aur
  68. * Lanes: G,H: SRIO
  69. */
  70. case 0x91:
  71. /*
  72. * Configuration:
  73. * SERDES: 2
  74. * Lanes: A,B: SGMII
  75. * Lanes: C,D: SRIO2
  76. * Lanes: E,F,G,H: XAUI2
  77. */
  78. case 0x93:
  79. /*
  80. * Configuration:
  81. * SERDES: 2
  82. * Lanes: A,B,C,D: SGMII
  83. * Lanes: E,F,G,H: XAUI2
  84. */
  85. case 0x98:
  86. /*
  87. * Configuration:
  88. * SERDES: 2
  89. * Lanes: A,B,C,D: XAUI2
  90. * Lanes: E,F,G,H: XAUI2
  91. */
  92. case 0x9a:
  93. /*
  94. * Configuration:
  95. * SERDES: 2
  96. * Lanes: A,B: PCI
  97. * Lanes: C,D: SGMII
  98. * Lanes: E,F,G,H: XAUI2
  99. */
  100. case 0x9e:
  101. /*
  102. * Configuration:
  103. * SERDES: 2
  104. * Lanes: A,B,C,D: PCI
  105. * Lanes: E,F,G,H: XAUI2
  106. */
  107. case 0xb1:
  108. case 0xb2:
  109. case 0x8c:
  110. case 0x8d:
  111. /*
  112. * Configuration:
  113. * SERDES: 2
  114. * Lanes: A,B,C,D: PCI
  115. * Lanes: E,F: SGMII 3&4
  116. * Lanes: G,H: XFI
  117. */
  118. case 0xc2:
  119. /*
  120. * Configuration:
  121. * SERDES: 2
  122. * Lanes: A,B: SGMII
  123. * Lanes: C,D: SRIO2
  124. * Lanes: E,F,G,H: XAUI2
  125. */
  126. lane_to_slot[12] = 2;
  127. lane_to_slot[13] = lane_to_slot[12];
  128. lane_to_slot[14] = lane_to_slot[12];
  129. lane_to_slot[15] = lane_to_slot[12];
  130. break;
  131. default:
  132. printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
  133. serdes2_prtcl);
  134. break;
  135. }
  136. return;
  137. }
  138. #endif /* #ifdef CONFIG_FMAN_ENET */
  139. int board_eth_init(bd_t *bis)
  140. {
  141. #ifdef CONFIG_FMAN_ENET
  142. struct memac_mdio_info memac_mdio_info;
  143. struct memac_mdio_info tg_memac_mdio_info;
  144. unsigned int i;
  145. unsigned int serdes1_prtcl, serdes2_prtcl;
  146. int qsgmii;
  147. struct mii_dev *bus;
  148. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  149. serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
  150. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  151. if (!serdes1_prtcl) {
  152. printf("SERDES1 is not enabled\n");
  153. return 0;
  154. }
  155. serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  156. debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
  157. serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  158. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  159. if (!serdes2_prtcl) {
  160. printf("SERDES2 is not enabled\n");
  161. return 0;
  162. }
  163. serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  164. debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
  165. printf("Initializing Fman\n");
  166. initialize_lane_to_slot();
  167. memac_mdio_info.regs =
  168. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  169. memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  170. /* Register the real 1G MDIO bus */
  171. fm_memac_mdio_init(bis, &memac_mdio_info);
  172. tg_memac_mdio_info.regs =
  173. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  174. tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  175. /* Register the real 10G MDIO bus */
  176. fm_memac_mdio_init(bis, &tg_memac_mdio_info);
  177. /*
  178. * Program the two on board DTSEC PHY addresses assuming that they are
  179. * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
  180. * 6 to on board SGMII phys
  181. */
  182. fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
  183. fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
  184. switch (serdes1_prtcl) {
  185. case 0x29:
  186. case 0x2a:
  187. /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
  188. debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
  189. CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
  190. CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
  191. fm_info_set_phy_address(FM1_DTSEC5,
  192. CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
  193. fm_info_set_phy_address(FM1_DTSEC6,
  194. CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
  195. break;
  196. #ifdef CONFIG_ARCH_B4420
  197. case 0x17:
  198. case 0x18:
  199. /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
  200. debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
  201. CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
  202. CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
  203. /* Fixing Serdes clock by programming FPGA register */
  204. QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
  205. fm_info_set_phy_address(FM1_DTSEC3,
  206. CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
  207. fm_info_set_phy_address(FM1_DTSEC4,
  208. CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
  209. break;
  210. #endif
  211. default:
  212. printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
  213. serdes1_prtcl);
  214. break;
  215. }
  216. switch (serdes2_prtcl) {
  217. case 0x17:
  218. case 0x18:
  219. debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
  220. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  221. fm_info_set_phy_address(FM1_DTSEC1,
  222. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  223. fm_info_set_phy_address(FM1_DTSEC2,
  224. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
  225. fm_info_set_phy_address(FM1_DTSEC3,
  226. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
  227. fm_info_set_phy_address(FM1_DTSEC4,
  228. CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
  229. break;
  230. case 0x48:
  231. case 0x49:
  232. debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
  233. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  234. fm_info_set_phy_address(FM1_DTSEC1,
  235. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  236. fm_info_set_phy_address(FM1_DTSEC2,
  237. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
  238. fm_info_set_phy_address(FM1_DTSEC3,
  239. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
  240. break;
  241. case 0xb1:
  242. case 0xb2:
  243. case 0x8c:
  244. case 0x8d:
  245. debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
  246. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  247. fm_info_set_phy_address(FM1_DTSEC3,
  248. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
  249. fm_info_set_phy_address(FM1_DTSEC4,
  250. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
  251. /*
  252. * XFI does not need a PHY to work, but to make U-Boot
  253. * happy, assign a fake PHY address for a XFI port.
  254. */
  255. fm_info_set_phy_address(FM1_10GEC1, 0);
  256. fm_info_set_phy_address(FM1_10GEC2, 1);
  257. break;
  258. case 0x98:
  259. /* XAUI in Slot1 and Slot2 */
  260. debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
  261. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  262. fm_info_set_phy_address(FM1_10GEC1,
  263. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  264. debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
  265. CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
  266. fm_info_set_phy_address(FM1_10GEC2,
  267. CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
  268. break;
  269. case 0x9E:
  270. /* XAUI in Slot2 */
  271. debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
  272. CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
  273. fm_info_set_phy_address(FM1_10GEC2,
  274. CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
  275. break;
  276. default:
  277. printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
  278. serdes2_prtcl);
  279. break;
  280. }
  281. /*set PHY address for QSGMII Riser Card on slot2*/
  282. bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  283. qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
  284. if (qsgmii) {
  285. switch (serdes2_prtcl) {
  286. case 0xb2:
  287. case 0x8d:
  288. fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
  289. fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
  290. break;
  291. default:
  292. break;
  293. }
  294. }
  295. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  296. int idx = i - FM1_DTSEC1;
  297. switch (fm_info_get_enet_if(i)) {
  298. case PHY_INTERFACE_MODE_SGMII:
  299. fm_info_set_mdio(i,
  300. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  301. break;
  302. case PHY_INTERFACE_MODE_NONE:
  303. fm_info_set_phy_address(i, 0);
  304. break;
  305. default:
  306. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  307. idx + 1, fm_info_get_enet_if(i));
  308. fm_info_set_phy_address(i, 0);
  309. break;
  310. }
  311. }
  312. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  313. int idx = i - FM1_10GEC1;
  314. switch (fm_info_get_enet_if(i)) {
  315. case PHY_INTERFACE_MODE_XGMII:
  316. fm_info_set_mdio(i,
  317. miiphy_get_dev_by_name
  318. (DEFAULT_FM_TGEC_MDIO_NAME));
  319. break;
  320. case PHY_INTERFACE_MODE_NONE:
  321. fm_info_set_phy_address(i, 0);
  322. break;
  323. default:
  324. printf("Fman1: TGEC%u set to unknown interface %i\n",
  325. idx + 1, fm_info_get_enet_if(i));
  326. fm_info_set_phy_address(i, 0);
  327. break;
  328. }
  329. }
  330. cpu_eth_init(bis);
  331. #endif
  332. return pci_eth_init(bis);
  333. }
  334. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  335. enum fm_port port, int offset)
  336. {
  337. int phy;
  338. char alias[32];
  339. struct fixed_link f_link;
  340. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  341. u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  342. prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  343. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  344. phy = fm_info_get_phy_address(port);
  345. sprintf(alias, "phy_sgmii_%x", phy);
  346. fdt_set_phy_handle(fdt, compat, addr, alias);
  347. fdt_status_okay_by_alias(fdt, alias);
  348. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  349. /* check if it's XFI interface for 10g */
  350. switch (prtcl2) {
  351. case 0x80:
  352. case 0x81:
  353. case 0x82:
  354. case 0x83:
  355. case 0x84:
  356. case 0x85:
  357. case 0x86:
  358. case 0x87:
  359. case 0x88:
  360. case 0x89:
  361. case 0x8a:
  362. case 0x8b:
  363. case 0x8c:
  364. case 0x8d:
  365. case 0x8e:
  366. case 0xb1:
  367. case 0xb2:
  368. f_link.phy_id = port;
  369. f_link.duplex = 1;
  370. f_link.link_speed = 10000;
  371. f_link.pause = 0;
  372. f_link.asym_pause = 0;
  373. fdt_delprop(fdt, offset, "phy-handle");
  374. fdt_setprop(fdt, offset, "fixed-link", &f_link,
  375. sizeof(f_link));
  376. break;
  377. case 0x98: /* XAUI interface */
  378. strcpy(alias, "phy_xaui_slot1");
  379. fdt_status_okay_by_alias(fdt, alias);
  380. strcpy(alias, "phy_xaui_slot2");
  381. fdt_status_okay_by_alias(fdt, alias);
  382. break;
  383. case 0x9e: /* XAUI interface */
  384. case 0x9a:
  385. case 0x93:
  386. case 0x91:
  387. strcpy(alias, "phy_xaui_slot1");
  388. fdt_status_okay_by_alias(fdt, alias);
  389. break;
  390. case 0x97: /* XAUI interface */
  391. case 0xc3:
  392. strcpy(alias, "phy_xaui_slot2");
  393. fdt_status_okay_by_alias(fdt, alias);
  394. break;
  395. default:
  396. break;
  397. }
  398. }
  399. }
  400. /*
  401. * Set status to disabled for unused ethernet node
  402. */
  403. void fdt_fixup_board_enet(void *fdt)
  404. {
  405. int i;
  406. char alias[32];
  407. for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
  408. switch (fm_info_get_enet_if(i)) {
  409. case PHY_INTERFACE_MODE_NONE:
  410. sprintf(alias, "ethernet%u", i);
  411. fdt_status_disabled_by_alias(fdt, alias);
  412. break;
  413. default:
  414. break;
  415. }
  416. }
  417. }