ddr.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <fsl_ddr.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/mmu.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. dimm_params_t ddr_raw_timing = {
  17. .n_ranks = 2,
  18. .rank_density = 2147483648u,
  19. .capacity = 4294967296u,
  20. .primary_sdram_width = 64,
  21. .ec_sdram_width = 8,
  22. .registered_dimm = 0,
  23. .mirrored_dimm = 1,
  24. .n_row_addr = 15,
  25. .n_col_addr = 10,
  26. .n_banks_per_sdram_device = 8,
  27. .edc_config = 2, /* ECC */
  28. .burst_lengths_bitmask = 0x0c,
  29. .tckmin_x_ps = 1071,
  30. .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
  31. .taa_ps = 13910,
  32. .twr_ps = 15000,
  33. .trcd_ps = 13910,
  34. .trrd_ps = 6000,
  35. .trp_ps = 13910,
  36. .tras_ps = 34000,
  37. .trc_ps = 48910,
  38. .trfc_ps = 260000,
  39. .twtr_ps = 7500,
  40. .trtp_ps = 7500,
  41. .refresh_rate_ps = 7800000,
  42. .tfaw_ps = 35000,
  43. };
  44. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  45. unsigned int controller_number,
  46. unsigned int dimm_number)
  47. {
  48. const char dimm_model[] = "RAW timing DDR";
  49. if ((controller_number == 0) && (dimm_number == 0)) {
  50. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  51. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  52. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  53. }
  54. return 0;
  55. }
  56. struct board_specific_parameters {
  57. u32 n_ranks;
  58. u32 datarate_mhz_high;
  59. u32 clk_adjust;
  60. u32 wrlvl_start;
  61. u32 wrlvl_ctl_2;
  62. u32 wrlvl_ctl_3;
  63. u32 cpo;
  64. u32 write_data_delay;
  65. u32 force_2t;
  66. };
  67. /*
  68. * This table contains all valid speeds we want to override with board
  69. * specific parameters. datarate_mhz_high values need to be in ascending order
  70. * for each n_ranks group.
  71. */
  72. static const struct board_specific_parameters udimm0[] = {
  73. /*
  74. * memory controller 0
  75. * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  76. * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
  77. */
  78. {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
  79. {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
  80. {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
  81. {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
  82. {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
  83. {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
  84. {}
  85. };
  86. static const struct board_specific_parameters *udimms[] = {
  87. udimm0,
  88. };
  89. void fsl_ddr_board_options(memctl_options_t *popts,
  90. dimm_params_t *pdimm,
  91. unsigned int ctrl_num)
  92. {
  93. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  94. ulong ddr_freq;
  95. if (ctrl_num > 2) {
  96. printf("Not supported controller number %d\n", ctrl_num);
  97. return;
  98. }
  99. if (!pdimm->n_ranks)
  100. return;
  101. pbsp = udimms[0];
  102. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  103. * freqency and n_banks specified in board_specific_parameters table.
  104. */
  105. ddr_freq = get_ddr_freq(0) / 1000000;
  106. while (pbsp->datarate_mhz_high) {
  107. if (pbsp->n_ranks == pdimm->n_ranks) {
  108. if (ddr_freq <= pbsp->datarate_mhz_high) {
  109. popts->cpo_override = pbsp->cpo;
  110. popts->write_data_delay =
  111. pbsp->write_data_delay;
  112. popts->clk_adjust = pbsp->clk_adjust;
  113. popts->wrlvl_start = pbsp->wrlvl_start;
  114. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  115. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  116. popts->twot_en = pbsp->force_2t;
  117. goto found;
  118. }
  119. pbsp_highest = pbsp;
  120. }
  121. pbsp++;
  122. }
  123. if (pbsp_highest) {
  124. printf("Error: board specific timing not found "
  125. "for data rate %lu MT/s\n"
  126. "Trying to use the highest speed (%u) parameters\n",
  127. ddr_freq, pbsp_highest->datarate_mhz_high);
  128. popts->cpo_override = pbsp_highest->cpo;
  129. popts->write_data_delay = pbsp_highest->write_data_delay;
  130. popts->clk_adjust = pbsp_highest->clk_adjust;
  131. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  132. popts->twot_en = pbsp_highest->force_2t;
  133. } else {
  134. panic("DIMM is not supported by this board");
  135. }
  136. found:
  137. /*
  138. * Factors to consider for half-strength driver enable:
  139. * - number of DIMMs installed
  140. */
  141. popts->half_strength_driver_enable = 0;
  142. /*
  143. * Write leveling override
  144. */
  145. popts->wrlvl_override = 1;
  146. popts->wrlvl_sample = 0xf;
  147. /*
  148. * Rtt and Rtt_WR override
  149. */
  150. popts->rtt_override = 0;
  151. /* Enable ZQ calibration */
  152. popts->zq_en = 1;
  153. /* DHC_EN =1, ODT = 75 Ohm */
  154. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  155. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  156. /* optimize cpo for erratum A-009942 */
  157. popts->cpo_sample = 0x3e;
  158. }
  159. int dram_init(void)
  160. {
  161. phys_size_t dram_size;
  162. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  163. puts("Initializing....using SPD\n");
  164. dram_size = fsl_ddr_sdram();
  165. #else
  166. dram_size = fsl_ddr_sdram_size();
  167. #endif
  168. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  169. dram_size *= 0x100000;
  170. gd->ram_size = dram_size;
  171. return 0;
  172. }
  173. unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
  174. unsigned int dbw_cap_adj[])
  175. {
  176. int i, j;
  177. unsigned long long total_mem, current_mem_base, total_ctlr_mem;
  178. unsigned long long rank_density, ctlr_density = 0;
  179. current_mem_base = 0ull;
  180. total_mem = 0;
  181. /*
  182. * This board has soldered DDR chips. DDRC1 has two rank.
  183. * DDRC2 has only one rank.
  184. * Assigning DDRC2 to lower address and DDRC1 to higher address.
  185. */
  186. if (pinfo->memctl_opts[0].memctl_interleaving) {
  187. rank_density = pinfo->dimm_params[0][0].rank_density >>
  188. dbw_cap_adj[0];
  189. ctlr_density = rank_density;
  190. debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
  191. rank_density, ctlr_density);
  192. for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
  193. switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
  194. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  195. case FSL_DDR_PAGE_INTERLEAVING:
  196. case FSL_DDR_BANK_INTERLEAVING:
  197. case FSL_DDR_SUPERBANK_INTERLEAVING:
  198. total_ctlr_mem = 2 * ctlr_density;
  199. break;
  200. default:
  201. panic("Unknown interleaving mode");
  202. }
  203. pinfo->common_timing_params[i].base_address =
  204. current_mem_base;
  205. pinfo->common_timing_params[i].total_mem =
  206. total_ctlr_mem;
  207. total_mem = current_mem_base + total_ctlr_mem;
  208. debug("ctrl %d base 0x%llx\n", i, current_mem_base);
  209. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  210. }
  211. } else {
  212. /*
  213. * Simple linear assignment if memory
  214. * controllers are not interleaved.
  215. */
  216. for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
  217. total_ctlr_mem = 0;
  218. pinfo->common_timing_params[i].base_address =
  219. current_mem_base;
  220. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  221. /* Compute DIMM base addresses. */
  222. unsigned long long cap =
  223. pinfo->dimm_params[i][j].capacity;
  224. pinfo->dimm_params[i][j].base_address =
  225. current_mem_base;
  226. debug("ctrl %d dimm %d base 0x%llx\n",
  227. i, j, current_mem_base);
  228. current_mem_base += cap;
  229. total_ctlr_mem += cap;
  230. }
  231. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  232. pinfo->common_timing_params[i].total_mem =
  233. total_ctlr_mem;
  234. total_mem += total_ctlr_mem;
  235. }
  236. }
  237. debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
  238. return total_mem;
  239. }