pcie_starfive.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Starfive PLDA PCIe host controller driver
  4. *
  5. * Copyright (c) 2023 Starfive, Inc.
  6. * Author: Mason Huo <mason.huo@starfivetech.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <asm/global_data.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/pinctrl.h>
  15. #include <generic-phy.h>
  16. #include <pci.h>
  17. #include <power-domain.h>
  18. #include <power/regulator.h>
  19. #include <regmap.h>
  20. #include <reset.h>
  21. #include <syscon.h>
  22. #include <asm/io.h>
  23. #include <asm-generic/gpio.h>
  24. #include <linux/delay.h>
  25. #include <linux/iopoll.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define GEN_SETTINGS 0x80
  28. #define PCIE_PCI_IDS 0x9C
  29. #define PCIE_WINROM 0xFC
  30. #define PMSG_SUPPORT_RX 0x3F0
  31. #define PCI_MISC 0xB4
  32. #define PLDA_EP_ENABLE 0
  33. #define PLDA_RP_ENABLE 1
  34. #define IDS_REVISION_ID 0x02
  35. #define IDS_PCI_TO_PCI_BRIDGE 0x060400
  36. #define IDS_CLASS_CODE_SHIFT 8
  37. #define PLDA_LINK_UP 1
  38. #define PLDA_LINK_DOWN 0
  39. #define PLDA_DATA_LINK_ACTIVE BIT(5)
  40. #define PREF_MEM_WIN_64_SUPPORT BIT(3)
  41. #define PMSG_LTR_SUPPORT BIT(2)
  42. #define PLDA_FUNCTION_DIS BIT(15)
  43. #define PLDA_FUNC_NUM 4
  44. #define PLDA_PHY_FUNC_SHIFT 9
  45. #define XR3PCI_ATR_AXI4_SLV0 0x800
  46. #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
  47. #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
  48. #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
  49. #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
  50. #define XR3PCI_ATR_TRSL_PARAM 0x10
  51. #define XR3PCI_ATR_TABLE_OFFSET 0x20
  52. #define XR3PCI_ATR_MAX_TABLE_NUM 8
  53. #define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
  54. #define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
  55. #define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
  56. #define XR3_PCI_ECAM_SIZE 28
  57. #define XR3PCI_ATR_TRSL_DIR BIT(22)
  58. /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  59. #define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
  60. #define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
  61. #define ECAM_BUS_SHIFT 20
  62. #define ECAM_DEV_SHIFT 15
  63. #define ECAM_FUNC_SHIFT 12
  64. /* Secondary bus number offset in config space */
  65. #define PCI_SECONDARY_BUS 0x19
  66. /* system control */
  67. #define STG_SYSCON_K_RP_NEP_SHIFT 0x8
  68. #define STG_SYSCON_K_RP_NEP_MASK 0x100
  69. #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
  70. #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
  71. #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
  72. #define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
  73. #define STG_SYSCON_CLKREQ_SHIFT 0x16
  74. #define STG_SYSCON_CLKREQ_MASK 0x400000
  75. #define STG_SYSCON_CKREF_SRC_SHIFT 0x12
  76. #define STG_SYSCON_CKREF_SRC_MASK 0xC0000
  77. struct starfive_pcie {
  78. struct udevice *dev;
  79. void __iomem *reg_base;
  80. void __iomem *cfg_base;
  81. struct regmap *regmap;
  82. u32 stg_arfun;
  83. u32 stg_awfun;
  84. u32 stg_rp_nep;
  85. u32 stg_lnksta;
  86. struct clk_bulk clks;
  87. struct reset_ctl_bulk rsts;
  88. int atr_table_num;
  89. int first_busno;
  90. };
  91. static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
  92. {
  93. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  94. return 0;
  95. if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
  96. return 0;
  97. return 1;
  98. }
  99. static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset, int first_busno)
  100. {
  101. unsigned int bus = PCI_BUS(bdf) - first_busno;
  102. unsigned int dev = PCI_DEV(bdf);
  103. unsigned int func = PCI_FUNC(bdf);
  104. return (bus << ECAM_BUS_SHIFT) | (dev << ECAM_DEV_SHIFT) |
  105. (func << ECAM_FUNC_SHIFT) | (offset & ~0x3);
  106. }
  107. static bool plda_pcie_hide_rc_bar(pci_dev_t bdf, int offset, int first_busno)
  108. {
  109. if ((PCI_BUS(bdf) == first_busno) &&
  110. (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
  111. return true;
  112. return false;
  113. }
  114. static int starfive_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
  115. uint offset, ulong *valuep,
  116. enum pci_size_t size)
  117. {
  118. void __iomem *addr;
  119. ulong value;
  120. struct starfive_pcie *priv = dev_get_priv(udev);
  121. int where = starfive_pcie_off_conf(bdf, offset, priv->first_busno);
  122. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  123. pr_debug("Out of range\n");
  124. *valuep = pci_get_ff(size);
  125. return 0;
  126. }
  127. addr = priv->cfg_base;
  128. addr += where;
  129. if (!addr)
  130. return -1;
  131. /* Make sure the LAST TLP is finished, before reading vendor ID. */
  132. if (offset == PCI_VENDOR_ID)
  133. mdelay(20);
  134. value = readl(addr);
  135. *valuep = pci_conv_32_to_size(value, offset, size);
  136. return 0;
  137. }
  138. int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
  139. uint offset, ulong value,
  140. enum pci_size_t size)
  141. {
  142. void __iomem *addr;
  143. ulong old;
  144. struct starfive_pcie *priv = dev_get_priv(udev);
  145. int where = starfive_pcie_off_conf(bdf, offset, priv->first_busno);
  146. if (plda_pcie_hide_rc_bar(bdf, offset, priv->first_busno))
  147. return -1;
  148. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  149. pr_debug("Out of range\n");
  150. return 0;
  151. }
  152. addr = priv->cfg_base;
  153. addr += where;
  154. if (!addr)
  155. return -1;
  156. old = readl(addr);
  157. value = pci_conv_size_to_32(old, value, offset, size);
  158. writel(value, addr);
  159. return 0;
  160. }
  161. static void starfive_pcie_set_atr_entry(struct starfive_pcie *priv, phys_addr_t src_addr,
  162. phys_addr_t trsl_addr, size_t window_size,
  163. int trsl_param)
  164. {
  165. void __iomem *base =
  166. priv->reg_base + XR3PCI_ATR_AXI4_SLV0;
  167. /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
  168. if (priv->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
  169. priv->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
  170. base += XR3PCI_ATR_TABLE_OFFSET * priv->atr_table_num;
  171. priv->atr_table_num++;
  172. /* X3PCI_ATR_SRC_ADDR_LOW:
  173. * - bit 0: enable entry,
  174. * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  175. * - bits 7-11: reserved
  176. * - bits 12-31: start of source address
  177. */
  178. writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
  179. (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
  180. base + XR3PCI_ATR_SRC_ADDR_LOW);
  181. writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  182. writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
  183. base + XR3PCI_ATR_TRSL_ADDR_LOW);
  184. writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  185. writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  186. dev_info(priv->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
  187. src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
  188. trsl_addr, (u64)window_size, trsl_param);
  189. }
  190. static int starfive_pcie_atr_init(struct starfive_pcie *priv)
  191. {
  192. struct udevice *ctlr = pci_get_controller(priv->dev);
  193. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  194. int i;
  195. /* As the two host bridges in JH7110 soc have the same default
  196. * address translation table, this cause the second root port can't
  197. * access it's host bridge config space correctly.
  198. * To workaround, config the ATR of host bridge config space by SW.
  199. */
  200. starfive_pcie_set_atr_entry(priv,
  201. (phys_addr_t)priv->cfg_base,
  202. 0,
  203. 1 << XR3_PCI_ECAM_SIZE,
  204. XR3PCI_ATR_TRSLID_PCIE_CONFIG);
  205. for (i = 0; i < hose->region_count; i++) {
  206. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  207. continue;
  208. /* Only support identity mappings. */
  209. if (hose->regions[i].bus_start !=
  210. hose->regions[i].phys_start)
  211. return -EINVAL;
  212. starfive_pcie_set_atr_entry(priv,
  213. hose->regions[i].phys_start,
  214. hose->regions[i].bus_start,
  215. hose->regions[i].size,
  216. XR3PCI_ATR_TRSLID_PCIE_MEMORY);
  217. }
  218. return 0;
  219. }
  220. static int starfive_pcie_get_syscon(struct udevice *dev)
  221. {
  222. struct starfive_pcie *priv = dev_get_priv(dev);
  223. struct udevice *syscon;
  224. struct ofnode_phandle_args syscfg_phandle;
  225. u32 cells[5];
  226. int ret;
  227. /* get corresponding syscon phandle */
  228. ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
  229. &syscfg_phandle);
  230. if (ret < 0) {
  231. dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
  232. return ret;
  233. }
  234. ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
  235. &syscon);
  236. if (ret) {
  237. dev_err(dev, "Unable to find syscon device (%d)\n", ret);
  238. return ret;
  239. }
  240. priv->regmap = syscon_get_regmap(syscon);
  241. if (!priv->regmap) {
  242. dev_err(dev, "Unable to find regmap\n");
  243. return -ENODEV;
  244. }
  245. /* get syscon register offset */
  246. ret = dev_read_u32_array(dev, "starfive,stg-syscon",
  247. cells, ARRAY_SIZE(cells));
  248. if (ret) {
  249. dev_err(dev, "Get syscon register count err %d\n", ret);
  250. return -EINVAL;
  251. }
  252. dev_dbg(dev, "Get syscon values: %x, %x, %x, %x\n",
  253. cells[1], cells[2], cells[3], cells[4]);
  254. priv->stg_arfun = cells[1];
  255. priv->stg_awfun = cells[2];
  256. priv->stg_rp_nep = cells[3];
  257. priv->stg_lnksta = cells[4];
  258. return 0;
  259. }
  260. static int starfive_pcie_parse_dt(struct udevice *dev)
  261. {
  262. struct starfive_pcie *priv = dev_get_priv(dev);
  263. int ret;
  264. priv->reg_base = (void *)dev_read_addr_name(dev, "reg");
  265. if (priv->reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  266. dev_err(dev, "Missing required reg address range\n");
  267. return -EINVAL;
  268. }
  269. priv->cfg_base = (void *)dev_read_addr_name(dev, "config");
  270. if (priv->cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  271. dev_err(dev, "Missing required config address range");
  272. return -EINVAL;
  273. }
  274. ret = starfive_pcie_get_syscon(dev);
  275. if (ret) {
  276. dev_err(dev, "Can't get syscon: %d\n", ret);
  277. return ret;
  278. }
  279. ret = reset_get_bulk(dev, &priv->rsts);
  280. if (ret) {
  281. dev_err(dev, "Can't get reset: %d\n", ret);
  282. return ret;
  283. }
  284. ret = clk_get_bulk(dev, &priv->clks);
  285. if (ret) {
  286. dev_err(dev, "Can't get clock: %d\n", ret);
  287. return ret;
  288. }
  289. return 0;
  290. }
  291. static int starfive_pcie_init_port(struct udevice *dev)
  292. {
  293. int ret, i;
  294. unsigned int value;
  295. struct starfive_pcie *priv = dev_get_priv(dev);
  296. ret = clk_enable_bulk(&priv->clks);
  297. if (ret) {
  298. dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
  299. return ret;
  300. }
  301. ret = reset_deassert_bulk(&priv->rsts);
  302. if (ret) {
  303. dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
  304. goto err_deassert_clk;
  305. }
  306. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  307. ret = pinctrl_select_state(dev, "power-active");
  308. if (ret) {
  309. dev_err(dev, "Set power-acvtive pinctrl failed: %d\n", ret);
  310. goto err_deassert_reset;
  311. }
  312. #endif
  313. ret = pinctrl_select_state(dev, "perst-active");
  314. if (ret) {
  315. dev_err(dev, "Set perst-active pinctrl failed: %d\n", ret);
  316. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  317. goto err_release_power_pin;
  318. #else
  319. goto err_deassert_reset;
  320. #endif
  321. }
  322. /* Disable physical functions except #0 */
  323. for (i = 1; i < PLDA_FUNC_NUM; i++) {
  324. regmap_update_bits(priv->regmap,
  325. priv->stg_arfun,
  326. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  327. (i << PLDA_PHY_FUNC_SHIFT) <<
  328. STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  329. regmap_update_bits(priv->regmap,
  330. priv->stg_awfun,
  331. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  332. (i << PLDA_PHY_FUNC_SHIFT) <<
  333. STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  334. value = readl(priv->reg_base + PCI_MISC);
  335. value |= PLDA_FUNCTION_DIS;
  336. writel(value, priv->reg_base + PCI_MISC);
  337. }
  338. regmap_update_bits(priv->regmap,
  339. priv->stg_arfun,
  340. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  341. 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  342. regmap_update_bits(priv->regmap,
  343. priv->stg_awfun,
  344. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  345. 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  346. /* Enable root port*/
  347. value = readl(priv->reg_base + GEN_SETTINGS);
  348. value |= PLDA_RP_ENABLE;
  349. writel(value, priv->reg_base + GEN_SETTINGS);
  350. /* PCIe PCI Standard Configuration Identification Settings. */
  351. value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
  352. writel(value, priv->reg_base + PCIE_PCI_IDS);
  353. /* The LTR message forwarding of PCIe Message Reception was set by core
  354. * as default, but the forward id & addr are also need to be reset.
  355. * If we do not disable LTR message forwarding here, or set a legal
  356. * forwarding address, the kernel will get stuck after this driver probe.
  357. * To workaround, disable the LTR message forwarding support on
  358. * PCIe Message Reception.
  359. */
  360. value = readl(priv->reg_base + PMSG_SUPPORT_RX);
  361. value &= ~PMSG_LTR_SUPPORT;
  362. writel(value, priv->reg_base + PMSG_SUPPORT_RX);
  363. /* Prefetchable memory window 64-bit addressing support */
  364. value = readl(priv->reg_base + PCIE_WINROM);
  365. value |= PREF_MEM_WIN_64_SUPPORT;
  366. writel(value, priv->reg_base + PCIE_WINROM);
  367. starfive_pcie_atr_init(priv);
  368. /* Ensure that PERST has been asserted for at least 300 ms */
  369. mdelay(100);
  370. ret = pinctrl_select_state(dev, "perst-default");
  371. if (ret) {
  372. dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
  373. return ret;
  374. }
  375. return 0;
  376. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  377. err_release_power_pin:
  378. pinctrl_select_state(dev, "power-default");
  379. #endif
  380. err_deassert_reset:
  381. reset_assert_bulk(&priv->rsts);
  382. err_deassert_clk:
  383. clk_disable_bulk(&priv->clks);
  384. return ret;
  385. }
  386. static int plda_pcie_is_link_up(struct udevice *dev)
  387. {
  388. struct starfive_pcie *priv = dev_get_priv(dev);
  389. int ret;
  390. u32 stg_reg_val;
  391. /* 100ms timeout value should be enough for Gen1/2 training */
  392. ret = regmap_read_poll_timeout(priv->regmap,
  393. priv->stg_lnksta,
  394. stg_reg_val,
  395. stg_reg_val & PLDA_DATA_LINK_ACTIVE,
  396. 10 * 1000, 100);
  397. /* If the link is down (no device in slot), then exit. */
  398. if (ret == -ETIMEDOUT) {
  399. dev_err(dev, "Port link down.\n");
  400. return PLDA_LINK_DOWN;
  401. } else if (ret == 0) {
  402. dev_err(dev, "Port link up.\n");
  403. return PLDA_LINK_UP;
  404. }
  405. dev_warn(dev, "Read stg_linksta failed.\n");
  406. return ret;
  407. }
  408. static int starfive_pcie_probe(struct udevice *dev)
  409. {
  410. struct starfive_pcie *priv = dev_get_priv(dev);
  411. int ret;
  412. priv->atr_table_num = 0;
  413. priv->dev = dev;
  414. priv->first_busno = dev_seq(dev);
  415. ret = starfive_pcie_parse_dt(dev);
  416. if (ret)
  417. return ret;
  418. regmap_update_bits(priv->regmap,
  419. priv->stg_rp_nep,
  420. STG_SYSCON_K_RP_NEP_MASK,
  421. 1 << STG_SYSCON_K_RP_NEP_SHIFT);
  422. regmap_update_bits(priv->regmap,
  423. priv->stg_awfun,
  424. STG_SYSCON_CKREF_SRC_MASK,
  425. 2 << STG_SYSCON_CKREF_SRC_SHIFT);
  426. regmap_update_bits(priv->regmap,
  427. priv->stg_awfun,
  428. STG_SYSCON_CLKREQ_MASK,
  429. 1 << STG_SYSCON_CLKREQ_SHIFT);
  430. ret = starfive_pcie_init_port(dev);
  431. if (ret)
  432. return ret;
  433. if (plda_pcie_is_link_up(dev) == PLDA_LINK_UP) {
  434. /* As the requirement in PCIe base spec r6.0, system (<=5GT/s) must
  435. * wait a minimum of 100 ms following exit from a conventional reset
  436. * before sending a configuration request to the device.
  437. */
  438. mdelay(100);
  439. }
  440. dev_err(dev, "Starfive PCIe bus probed.\n");
  441. return 0;
  442. }
  443. static const struct dm_pci_ops starfive_pcie_ops = {
  444. .read_config = starfive_pcie_config_read,
  445. .write_config = starfive_pcie_config_write,
  446. };
  447. static const struct udevice_id starfive_pcie_ids[] = {
  448. { .compatible = "starfive,jh7110-pcie" },
  449. { }
  450. };
  451. U_BOOT_DRIVER(starfive_pcie_drv) = {
  452. .name = "starfive_pcie",
  453. .id = UCLASS_PCI,
  454. .of_match = starfive_pcie_ids,
  455. .ops = &starfive_pcie_ops,
  456. .probe = starfive_pcie_probe,
  457. .priv_auto = sizeof(struct starfive_pcie),
  458. };