netarm_ser_module.h 11 KB

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  1. /*
  2. * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
  3. *
  4. * Copyright (C) 2000 NETsilicon, Inc.
  5. * Copyright (C) 2000 Red Hat, Inc.
  6. *
  7. * This software is copyrighted by Red Hat. LICENSEE agrees that
  8. * it will not delete this copyright notice, trademarks or protective
  9. * notices from any copy made by LICENSEE.
  10. *
  11. * This software is provided "AS-IS" and any express or implied
  12. * warranties or conditions, including but not limited to any
  13. * implied warranties of merchantability and fitness for a particular
  14. * purpose regarding this software. In no event shall Red Hat
  15. * be liable for any indirect, consequential, or incidental damages,
  16. * loss of profits or revenue, loss of use or data, or interruption
  17. * of business, whether the alleged damages are labeled in contract,
  18. * tort, or indemnity.
  19. *
  20. * This program is free software; you can redistribute it and/or modify
  21. * it under the terms of the GNU General Public License as published by
  22. * the Free Software Foundation; either version 2 of the License, or
  23. * (at your option) any later version.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28. *
  29. * author(s) : Joe deBlaquiere
  30. * Clark Williams
  31. */
  32. #ifndef __NETARM_SER_MODULE_REGISTERS_H
  33. #define __NETARM_SER_MODULE_REGISTERS_H
  34. #ifndef __ASSEMBLER__
  35. /* (--sub)#include "types.h" */
  36. /* serial channel control structure */
  37. typedef struct {
  38. u32 ctrl_a;
  39. u32 ctrl_b;
  40. u32 status_a;
  41. u32 bitrate;
  42. u32 fifo;
  43. u32 rx_buf_timer;
  44. u32 rx_char_timer;
  45. u32 rx_match;
  46. u32 rx_match_mask;
  47. u32 ctrl_c;
  48. u32 status_b;
  49. u32 status_c;
  50. u32 fifo_last;
  51. u32 unused[3];
  52. } netarm_serial_channel_t;
  53. #endif
  54. /* SER unit register offsets */
  55. /* #ifdef CONFIG_ARCH_NETARM */
  56. #define NETARM_SER_MODULE_BASE (0xFFD00000)
  57. /* #else */
  58. /* extern serial_channel_t netarm_dummy_registers[]; */
  59. /* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */
  60. /* #ifndef NETARM_XTAL_FREQ */
  61. /* #define NETARM_XTAL_FREQ 18432000 */
  62. /* #endif */
  63. /* #endif */
  64. /* calculate the sysclk value from the pll setting */
  65. #define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \
  66. ( NETARM_PLL_COUNT_VAL + 3 ))
  67. #define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
  68. #define NETARM_SER_CH1_CTRL_A (0x00)
  69. #define NETARM_SER_CH1_CTRL_B (0x04)
  70. #define NETARM_SER_CH1_STATUS_A (0x08)
  71. #define NETARM_SER_CH1_BITRATE (0x0C)
  72. #define NETARM_SER_CH1_FIFO (0x10)
  73. #define NETARM_SER_CH1_RX_BUF_TMR (0x14)
  74. #define NETARM_SER_CH1_RX_CHAR_TMR (0x18)
  75. #define NETARM_SER_CH1_RX_MATCH (0x1c)
  76. #define NETARM_SER_CH1_RX_MATCH_MASK (0x20)
  77. #define NETARM_SER_CH1_CTRL_C (0x24)
  78. #define NETARM_SER_CH1_STATUS_B (0x28)
  79. #define NETARM_SER_CH1_STATUS_C (0x2c)
  80. #define NETARM_SER_CH1_FIFO_LAST (0x30)
  81. #define NETARM_SER_CH2_CTRL_A (0x40)
  82. #define NETARM_SER_CH2_CTRL_B (0x44)
  83. #define NETARM_SER_CH2_STATUS_A (0x48)
  84. #define NETARM_SER_CH2_BITRATE (0x4C)
  85. #define NETARM_SER_CH2_FIFO (0x50)
  86. #define NETARM_SER_CH2_RX_BUF_TMR (0x54)
  87. #define NETARM_SER_CH2_RX_CHAR_TMR (0x58)
  88. #define NETARM_SER_CH2_RX_MATCH (0x5c)
  89. #define NETARM_SER_CH2_RX_MATCH_MASK (0x60)
  90. #define NETARM_SER_CH2_CTRL_C (0x64)
  91. #define NETARM_SER_CH2_STATUS_B (0x68)
  92. #define NETARM_SER_CH2_STATUS_C (0x6c)
  93. #define NETARM_SER_CH2_FIFO_LAST (0x70)
  94. /* select bitfield defintions */
  95. /* Control Register A */
  96. #define NETARM_SER_CTLA_ENABLE (0x80000000)
  97. #define NETARM_SER_CTLA_BRK (0x40000000)
  98. #define NETARM_SER_CTLA_STICKP (0x20000000)
  99. #define NETARM_SER_CTLA_P_EVEN (0x18000000)
  100. #define NETARM_SER_CTLA_P_ODD (0x08000000)
  101. #define NETARM_SER_CTLA_P_NONE (0x00000000)
  102. /* if you read the errata, you will find that the STOP bits don't work right */
  103. #define NETARM_SER_CTLA_2STOP (0x00000000)
  104. #define NETARM_SER_CTLA_3STOP (0x04000000)
  105. #define NETARM_SER_CTLA_5BITS (0x00000000)
  106. #define NETARM_SER_CTLA_6BITS (0x01000000)
  107. #define NETARM_SER_CTLA_7BITS (0x02000000)
  108. #define NETARM_SER_CTLA_8BITS (0x03000000)
  109. #define NETARM_SER_CTLA_CTSTX (0x00800000)
  110. #define NETARM_SER_CTLA_RTSRX (0x00400000)
  111. #define NETARM_SER_CTLA_LOOP_REM (0x00200000)
  112. #define NETARM_SER_CTLA_LOOP_LOC (0x00100000)
  113. #define NETARM_SER_CTLA_GPIO2 (0x00080000)
  114. #define NETARM_SER_CTLA_GPIO1 (0x00040000)
  115. #define NETARM_SER_CTLA_DTR_EN (0x00020000)
  116. #define NETARM_SER_CTLA_RTS_EN (0x00010000)
  117. #define NETARM_SER_CTLA_IE_RX_BRK (0x00008000)
  118. #define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000)
  119. #define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000)
  120. #define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000)
  121. #define NETARM_SER_CTLA_IE_RX_RDY (0x00000800)
  122. #define NETARM_SER_CTLA_IE_RX_HALF (0x00000400)
  123. #define NETARM_SER_CTLA_IE_RX_FULL (0x00000200)
  124. #define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100)
  125. #define NETARM_SER_CTLA_IE_RX_DCD (0x00000080)
  126. #define NETARM_SER_CTLA_IE_RX_RI (0x00000040)
  127. #define NETARM_SER_CTLA_IE_RX_DSR (0x00000020)
  128. #define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \
  129. |NETARM_SER_CTLA_IE_RX_FRMERR \
  130. |NETARM_SER_CTLA_IE_RX_PARERR \
  131. |NETARM_SER_CTLA_IE_RX_OVERRUN \
  132. |NETARM_SER_CTLA_IE_RX_RDY \
  133. |NETARM_SER_CTLA_IE_RX_HALF \
  134. |NETARM_SER_CTLA_IE_RX_FULL \
  135. |NETARM_SER_CTLA_IE_RX_DMAEN \
  136. |NETARM_SER_CTLA_IE_RX_DCD \
  137. |NETARM_SER_CTLA_IE_RX_RI \
  138. |NETARM_SER_CTLA_IE_RX_DSR)
  139. #define NETARM_SER_CTLA_IE_TX_CTS (0x00000010)
  140. #define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008)
  141. #define NETARM_SER_CTLA_IE_TX_HALF (0x00000004)
  142. #define NETARM_SER_CTLA_IE_TX_FULL (0x00000002)
  143. #define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001)
  144. #define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \
  145. |NETARM_SER_CTLA_IE_TX_EMPTY \
  146. |NETARM_SER_CTLA_IE_TX_HALF \
  147. |NETARM_SER_CTLA_IE_TX_FULL \
  148. |NETARM_SER_CTLA_IE_TX_DMAEN)
  149. /* Control Register B */
  150. #define NETARM_SER_CTLB_MATCH1_EN (0x80000000)
  151. #define NETARM_SER_CTLB_MATCH2_EN (0x40000000)
  152. #define NETARM_SER_CTLB_MATCH3_EN (0x20000000)
  153. #define NETARM_SER_CTLB_MATCH4_EN (0x10000000)
  154. #define NETARM_SER_CTLB_RBGT_EN (0x08000000)
  155. #define NETARM_SER_CTLB_RCGT_EN (0x04000000)
  156. #define NETARM_SER_CTLB_UART_MODE (0x00000000)
  157. #define NETARM_SER_CTLB_HDLC_MODE (0x00100000)
  158. #define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000)
  159. #define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000)
  160. #define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000)
  161. #define NETARM_SER_CTLB_MAM1 (0x00040000)
  162. #define NETARM_SER_CTLB_MAM2 (0x00020000)
  163. /* Status Register A */
  164. #define NETARM_SER_STATA_MATCH1 (0x80000000)
  165. #define NETARM_SER_STATA_MATCH2 (0x40000000)
  166. #define NETARM_SER_STATA_MATCH3 (0x20000000)
  167. #define NETARM_SER_STATA_MATCH4 (0x10000000)
  168. #define NETARM_SER_STATA_BGAP (0x80000000)
  169. #define NETARM_SER_STATA_CGAP (0x40000000)
  170. #define NETARM_SER_STATA_RX_1B (0x00100000)
  171. #define NETARM_SER_STATA_RX_2B (0x00200000)
  172. #define NETARM_SER_STATA_RX_3B (0x00300000)
  173. #define NETARM_SER_STATA_RX_4B (0x00000000)
  174. /* downshifted values */
  175. #define NETARM_SER_STATA_RXFDB_1BYTES (0x001)
  176. #define NETARM_SER_STATA_RXFDB_2BYTES (0x002)
  177. #define NETARM_SER_STATA_RXFDB_3BYTES (0x003)
  178. #define NETARM_SER_STATA_RXFDB_4BYTES (0x000)
  179. #define NETARM_SER_STATA_RXFDB_MASK (0x00300000)
  180. #define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \
  181. >> 20)
  182. #define NETARM_SER_STATA_DCD (0x00080000)
  183. #define NETARM_SER_STATA_RI (0x00040000)
  184. #define NETARM_SER_STATA_DSR (0x00020000)
  185. #define NETARM_SER_STATA_CTS (0x00010000)
  186. #define NETARM_SER_STATA_RX_BRK (0x00008000)
  187. #define NETARM_SER_STATA_RX_FRMERR (0x00004000)
  188. #define NETARM_SER_STATA_RX_PARERR (0x00002000)
  189. #define NETARM_SER_STATA_RX_OVERRUN (0x00001000)
  190. #define NETARM_SER_STATA_RX_RDY (0x00000800)
  191. #define NETARM_SER_STATA_RX_HALF (0x00000400)
  192. #define NETARM_SER_STATA_RX_CLOSED (0x00000200)
  193. #define NETARM_SER_STATA_RX_FULL (0x00000100)
  194. #define NETARM_SER_STATA_RX_DCD (0x00000080)
  195. #define NETARM_SER_STATA_RX_RI (0x00000040)
  196. #define NETARM_SER_STATA_RX_DSR (0x00000020)
  197. #define NETARM_SER_STATA_TX_CTS (0x00000010)
  198. #define NETARM_SER_STATA_TX_RDY (0x00000008)
  199. #define NETARM_SER_STATA_TX_HALF (0x00000004)
  200. #define NETARM_SER_STATA_TX_FULL (0x00000002)
  201. #define NETARM_SER_STATA_TX_DMAEN (0x00000001)
  202. /* you have to clear all receive signals to get the fifo to move forward */
  203. #define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \
  204. NETARM_SER_STATA_RX_FRMERR | \
  205. NETARM_SER_STATA_RX_PARERR | \
  206. NETARM_SER_STATA_RX_OVERRUN | \
  207. NETARM_SER_STATA_RX_HALF | \
  208. NETARM_SER_STATA_RX_CLOSED | \
  209. NETARM_SER_STATA_RX_FULL | \
  210. NETARM_SER_STATA_RX_DCD | \
  211. NETARM_SER_STATA_RX_RI | \
  212. NETARM_SER_STATA_RX_DSR | \
  213. NETARM_SER_STATA_TX_CTS )
  214. /* Bit Rate Registers */
  215. #define NETARM_SER_BR_EN (0x80000000)
  216. #define NETARM_SER_BR_TMODE (0x40000000)
  217. #define NETARM_SER_BR_RX_CLK_INT (0x00000000)
  218. #define NETARM_SER_BR_RX_CLK_EXT (0x20000000)
  219. #define NETARM_SER_BR_TX_CLK_INT (0x00000000)
  220. #define NETARM_SER_BR_TX_CLK_EXT (0x10000000)
  221. #define NETARM_SER_BR_RX_CLK_DRV (0x08000000)
  222. #define NETARM_SER_BR_TX_CLK_DRV (0x04000000)
  223. #define NETARM_SER_BR_CLK_EXT_5 (0x00000000)
  224. #define NETARM_SER_BR_CLK_SYSTEM (0x01000000)
  225. #define NETARM_SER_BR_CLK_OUT1A (0x02000000)
  226. #define NETARM_SER_BR_CLK_OUT2A (0x03000000)
  227. #define NETARM_SER_BR_TX_CLK_INV (0x00800000)
  228. #define NETARM_SER_BR_RX_CLK_INV (0x00400000)
  229. /* complete settings assuming system clock input is 18MHz */
  230. #define NETARM_SER_BR_MASK (0x000007FF)
  231. /* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
  232. /* from section 7.5.4 of HW Ref Guide */
  233. /* #ifdef CONFIG_NETARM_PLL_BYPASS */
  234. #define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
  235. NETARM_SER_BR_RX_CLK_INT | \
  236. NETARM_SER_BR_TX_CLK_INT | \
  237. NETARM_SER_BR_CLK_EXT_5 | \
  238. ( ( ( ( NETARM_XTAL_FREQ / \
  239. ( x * 10 ) ) - 1 ) / 16 ) & \
  240. NETARM_SER_BR_MASK ) )
  241. /*
  242. #else
  243. #define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
  244. NETARM_SER_BR_RX_CLK_INT | \
  245. NETARM_SER_BR_TX_CLK_INT | \
  246. NETARM_SER_BR_CLK_SYSTEM | \
  247. ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
  248. ( x * 2 ) ) - 1 ) / 16 ) & \
  249. NETARM_SER_BR_MASK ) )
  250. #endif
  251. */
  252. /* Receive Buffer Gap Timer */
  253. #define NETARM_SER_RX_GAP_TIMER_EN (0x80000000)
  254. #define NETARM_SER_RX_GAP_MASK (0x00003FFF)
  255. /* rx gap is a function of bit rate x */
  256. /* #ifdef CONFIG_NETARM_PLL_BYPASS */
  257. #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
  258. ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
  259. ( x * 5 * 512 ) ) - 1 ) & \
  260. NETARM_SER_RX_GAP_MASK ) )
  261. /*
  262. #else
  263. #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
  264. ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
  265. ( x * 512 ) ) - 1 ) & \
  266. NETARM_SER_RX_GAP_MASK ) )
  267. #endif
  268. */
  269. #if 0
  270. #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
  271. ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
  272. ( x * 5 * 512 ) ) - 1 ) & \
  273. NETARM_SER_RX_GAP_MASK ) )
  274. #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
  275. ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
  276. ( x * 512 ) ) - 1 ) & \
  277. NETARM_SER_RX_GAP_MASK ) )
  278. #endif
  279. #define MIN_BAUD_RATE 600
  280. #define MAX_BAUD_RATE 115200
  281. /* the default BAUD rate for the BOOTLOADER, there is a separate */
  282. /* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
  283. #define DEFAULT_BAUD_RATE 9600
  284. #define NETARM_SER_FIFO_SIZE 32
  285. #define MIN_GAP 0
  286. #endif