cfi_flash.c 32 KB

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  1. /*
  2. * (C) Copyright 2002-2004
  3. * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
  4. *
  5. * Copyright (C) 2003 Arabella Software Ltd.
  6. * Yuli Barcohen <yuli@arabellasw.com>
  7. * Modified to work with AMD flashes
  8. *
  9. * Copyright (C) 2004
  10. * Ed Okerson
  11. * Modified to work with little-endian systems.
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. *
  31. * History
  32. * 01/20/2004 - combined variants of original driver.
  33. * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
  34. * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
  35. * 01/27/2004 - Little endian support Ed Okerson
  36. *
  37. * Tested Architectures
  38. * Port Width Chip Width # of banks Flash Chip Board
  39. * 32 16 1 28F128J3 seranoa/eagle
  40. * 64 16 1 28F128J3 seranoa/falcon
  41. *
  42. */
  43. /* The DEBUG define must be before common to enable debugging */
  44. /* #define DEBUG */
  45. #include <common.h>
  46. #include <asm/processor.h>
  47. #ifdef CFG_FLASH_CFI_DRIVER
  48. /*
  49. * This file implements a Common Flash Interface (CFI) driver for U-Boot.
  50. * The width of the port and the width of the chips are determined at initialization.
  51. * These widths are used to calculate the address for access CFI data structures.
  52. * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
  53. *
  54. * References
  55. * JEDEC Standard JESD68 - Common Flash Interface (CFI)
  56. * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
  57. * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
  58. * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
  59. *
  60. * TODO
  61. *
  62. * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
  63. * Table (ALT) to determine if protection is available
  64. *
  65. * Add support for other command sets Use the PRI and ALT to determine command set
  66. * Verify erase and program timeouts.
  67. */
  68. #ifndef CFG_FLASH_BANKS_LIST
  69. #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  70. #endif
  71. #define FLASH_CMD_CFI 0x98
  72. #define FLASH_CMD_READ_ID 0x90
  73. #define FLASH_CMD_RESET 0xff
  74. #define FLASH_CMD_BLOCK_ERASE 0x20
  75. #define FLASH_CMD_ERASE_CONFIRM 0xD0
  76. #define FLASH_CMD_WRITE 0x40
  77. #define FLASH_CMD_PROTECT 0x60
  78. #define FLASH_CMD_PROTECT_SET 0x01
  79. #define FLASH_CMD_PROTECT_CLEAR 0xD0
  80. #define FLASH_CMD_CLEAR_STATUS 0x50
  81. #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
  82. #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
  83. #define FLASH_STATUS_DONE 0x80
  84. #define FLASH_STATUS_ESS 0x40
  85. #define FLASH_STATUS_ECLBS 0x20
  86. #define FLASH_STATUS_PSLBS 0x10
  87. #define FLASH_STATUS_VPENS 0x08
  88. #define FLASH_STATUS_PSS 0x04
  89. #define FLASH_STATUS_DPS 0x02
  90. #define FLASH_STATUS_R 0x01
  91. #define FLASH_STATUS_PROTECT 0x01
  92. #define AMD_CMD_RESET 0xF0
  93. #define AMD_CMD_WRITE 0xA0
  94. #define AMD_CMD_ERASE_START 0x80
  95. #define AMD_CMD_ERASE_SECTOR 0x30
  96. #define AMD_STATUS_TOGGLE 0x40
  97. #define AMD_STATUS_ERROR 0x20
  98. #define FLASH_OFFSET_CFI 0x55
  99. #define FLASH_OFFSET_CFI_RESP 0x10
  100. #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
  101. #define FLASH_OFFSET_WTOUT 0x1F
  102. #define FLASH_OFFSET_WBTOUT 0x20
  103. #define FLASH_OFFSET_ETOUT 0x21
  104. #define FLASH_OFFSET_CETOUT 0x22
  105. #define FLASH_OFFSET_WMAX_TOUT 0x23
  106. #define FLASH_OFFSET_WBMAX_TOUT 0x24
  107. #define FLASH_OFFSET_EMAX_TOUT 0x25
  108. #define FLASH_OFFSET_CEMAX_TOUT 0x26
  109. #define FLASH_OFFSET_SIZE 0x27
  110. #define FLASH_OFFSET_INTERFACE 0x28
  111. #define FLASH_OFFSET_BUFFER_SIZE 0x2A
  112. #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
  113. #define FLASH_OFFSET_ERASE_REGIONS 0x2D
  114. #define FLASH_OFFSET_PROTECT 0x02
  115. #define FLASH_OFFSET_USER_PROTECTION 0x85
  116. #define FLASH_OFFSET_INTEL_PROTECTION 0x81
  117. #define FLASH_MAN_CFI 0x01000000
  118. #define CFI_CMDSET_NONE 0
  119. #define CFI_CMDSET_INTEL_EXTENDED 1
  120. #define CFI_CMDSET_AMD_STANDARD 2
  121. #define CFI_CMDSET_INTEL_STANDARD 3
  122. #define CFI_CMDSET_AMD_EXTENDED 4
  123. #define CFI_CMDSET_MITSU_STANDARD 256
  124. #define CFI_CMDSET_MITSU_EXTENDED 257
  125. #define CFI_CMDSET_SST 258
  126. typedef union {
  127. unsigned char c;
  128. unsigned short w;
  129. unsigned long l;
  130. unsigned long long ll;
  131. } cfiword_t;
  132. typedef union {
  133. volatile unsigned char *cp;
  134. volatile unsigned short *wp;
  135. volatile unsigned long *lp;
  136. volatile unsigned long long *llp;
  137. } cfiptr_t;
  138. #define NUM_ERASE_REGIONS 4
  139. static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
  140. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  141. /*-----------------------------------------------------------------------
  142. * Functions
  143. */
  144. typedef unsigned long flash_sect_t;
  145. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
  146. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
  147. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
  148. uint offset, uchar cmd);
  149. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
  150. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset,
  151. uchar cmd);
  152. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset,
  153. uchar cmd);
  154. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset,
  155. uchar cmd);
  156. static int flash_detect_cfi (flash_info_t * info);
  157. static ulong flash_get_size (ulong base, int banknum);
  158. static int flash_write_cfiword (flash_info_t * info, ulong dest,
  159. cfiword_t cword);
  160. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  161. ulong tout, char *prompt);
  162. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  163. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
  164. int len);
  165. #endif
  166. /*-----------------------------------------------------------------------
  167. * create an address based on the offset and the port width
  168. */
  169. inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect,
  170. uint offset)
  171. {
  172. return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
  173. }
  174. #ifdef DEBUG
  175. /*-----------------------------------------------------------------------
  176. * Debug support
  177. */
  178. void print_longlong (char *str, unsigned long long data)
  179. {
  180. int i;
  181. char *cp;
  182. cp = (unsigned char *) &data;
  183. for (i = 0; i < 8; i++)
  184. sprintf (&str[i * 2], "%2.2x", *cp++);
  185. }
  186. static void flash_printqry (flash_info_t * info, flash_sect_t sect)
  187. {
  188. cfiptr_t cptr;
  189. int x, y;
  190. for (x = 0; x < 0x40; x += 16 / info->portwidth) {
  191. cptr.cp =
  192. flash_make_addr (info, sect,
  193. x + FLASH_OFFSET_CFI_RESP);
  194. debug ("%p : ", cptr.cp);
  195. for (y = 0; y < 16; y++) {
  196. debug ("%2.2x ", cptr.cp[y]);
  197. }
  198. debug (" ");
  199. for (y = 0; y < 16; y++) {
  200. if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
  201. debug ("%c", cptr.cp[y]);
  202. } else {
  203. debug (".");
  204. }
  205. }
  206. debug ("\n");
  207. }
  208. }
  209. #endif
  210. /*-----------------------------------------------------------------------
  211. * read a character at a port width address
  212. */
  213. inline uchar flash_read_uchar (flash_info_t * info, uint offset)
  214. {
  215. uchar *cp;
  216. cp = flash_make_addr (info, 0, offset);
  217. #if defined(__LITTLE_ENDIAN)
  218. return (cp[0]);
  219. #else
  220. return (cp[info->portwidth - 1]);
  221. #endif
  222. }
  223. /*-----------------------------------------------------------------------
  224. * read a short word by swapping for ppc format.
  225. */
  226. ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
  227. {
  228. uchar *addr;
  229. ushort retval;
  230. #ifdef DEBUG
  231. int x;
  232. #endif
  233. addr = flash_make_addr (info, sect, offset);
  234. #ifdef DEBUG
  235. debug ("ushort addr is at %p info->portwidth = %d\n", addr,
  236. info->portwidth);
  237. for (x = 0; x < 2 * info->portwidth; x++) {
  238. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  239. }
  240. #endif
  241. #if defined(__LITTLE_ENDIAN)
  242. retval = ((addr[(info->portwidth)] << 8) | addr[0]);
  243. #else
  244. retval = ((addr[(2 * info->portwidth) - 1] << 8) |
  245. addr[info->portwidth - 1]);
  246. #endif
  247. debug ("retval = 0x%x\n", retval);
  248. return retval;
  249. }
  250. /*-----------------------------------------------------------------------
  251. * read a long word by picking the least significant byte of each maiximum
  252. * port size word. Swap for ppc format.
  253. */
  254. ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
  255. {
  256. uchar *addr;
  257. ulong retval;
  258. #ifdef DEBUG
  259. int x;
  260. #endif
  261. addr = flash_make_addr (info, sect, offset);
  262. #ifdef DEBUG
  263. debug ("long addr is at %p info->portwidth = %d\n", addr,
  264. info->portwidth);
  265. for (x = 0; x < 4 * info->portwidth; x++) {
  266. debug ("addr[%x] = 0x%x\n", x, addr[x]);
  267. }
  268. #endif
  269. #if defined(__LITTLE_ENDIAN)
  270. retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
  271. (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)]
  272. << 8);
  273. #else
  274. retval = (addr[(2 * info->portwidth) - 1] << 24) |
  275. (addr[(info->portwidth) - 1] << 16) |
  276. (addr[(4 * info->portwidth) - 1] << 8) |
  277. addr[(3 * info->portwidth) - 1];
  278. #endif
  279. return retval;
  280. }
  281. /*-----------------------------------------------------------------------
  282. */
  283. unsigned long flash_init (void)
  284. {
  285. unsigned long size = 0;
  286. int i;
  287. /* Init: no FLASHes known */
  288. for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  289. flash_info[i].flash_id = FLASH_UNKNOWN;
  290. size += flash_info[i].size = flash_get_size (bank_base[i], i);
  291. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  292. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, flash_info[i].size, flash_info[i].size << 20);
  293. }
  294. }
  295. /* Monitor protection ON by default */
  296. #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
  297. flash_protect (FLAG_PROTECT_SET,
  298. CFG_MONITOR_BASE,
  299. CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
  300. &flash_info[0]);
  301. #endif
  302. return (size);
  303. }
  304. /*-----------------------------------------------------------------------
  305. */
  306. int flash_erase (flash_info_t * info, int s_first, int s_last)
  307. {
  308. int rcode = 0;
  309. int prot;
  310. flash_sect_t sect;
  311. if (info->flash_id != FLASH_MAN_CFI) {
  312. printf ("Can't erase unknown flash type - aborted\n");
  313. return 1;
  314. }
  315. if ((s_first < 0) || (s_first > s_last)) {
  316. printf ("- no sectors to erase\n");
  317. return 1;
  318. }
  319. prot = 0;
  320. for (sect = s_first; sect <= s_last; ++sect) {
  321. if (info->protect[sect]) {
  322. prot++;
  323. }
  324. }
  325. if (prot) {
  326. printf ("- Warning: %d protected sectors will not be erased!\n", prot);
  327. } else {
  328. printf ("\n");
  329. }
  330. for (sect = s_first; sect <= s_last; sect++) {
  331. if (info->protect[sect] == 0) { /* not protected */
  332. switch (info->vendor) {
  333. case CFI_CMDSET_INTEL_STANDARD:
  334. case CFI_CMDSET_INTEL_EXTENDED:
  335. flash_write_cmd (info, sect, 0,
  336. FLASH_CMD_CLEAR_STATUS);
  337. flash_write_cmd (info, sect, 0,
  338. FLASH_CMD_BLOCK_ERASE);
  339. flash_write_cmd (info, sect, 0,
  340. FLASH_CMD_ERASE_CONFIRM);
  341. break;
  342. case CFI_CMDSET_AMD_STANDARD:
  343. case CFI_CMDSET_AMD_EXTENDED:
  344. flash_unlock_seq (info, sect);
  345. flash_write_cmd (info, sect, 0x555,
  346. AMD_CMD_ERASE_START);
  347. flash_unlock_seq (info, sect);
  348. flash_write_cmd (info, sect, 0,
  349. AMD_CMD_ERASE_SECTOR);
  350. break;
  351. default:
  352. debug ("Unkown flash vendor %d\n",
  353. info->vendor);
  354. break;
  355. }
  356. if (flash_full_status_check
  357. (info, sect, info->erase_blk_tout, "erase")) {
  358. rcode = 1;
  359. } else
  360. printf (".");
  361. }
  362. }
  363. printf (" done\n");
  364. return rcode;
  365. }
  366. /*-----------------------------------------------------------------------
  367. */
  368. void flash_print_info (flash_info_t * info)
  369. {
  370. int i;
  371. if (info->flash_id != FLASH_MAN_CFI) {
  372. printf ("missing or unknown FLASH type\n");
  373. return;
  374. }
  375. printf ("CFI conformant FLASH (%d x %d)",
  376. (info->portwidth << 3), (info->chipwidth << 3));
  377. printf (" Size: %ld MB in %d Sectors\n",
  378. info->size >> 20, info->sector_count);
  379. printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
  380. printf (" Sector Start Addresses:");
  381. for (i = 0; i < info->sector_count; ++i) {
  382. #ifdef CFG_FLASH_EMPTY_INFO
  383. int k;
  384. int size;
  385. int erased;
  386. volatile unsigned long *flash;
  387. /*
  388. * Check if whole sector is erased
  389. */
  390. if (i != (info->sector_count - 1))
  391. size = info->start[i + 1] - info->start[i];
  392. else
  393. size = info->start[0] + info->size - info->start[i];
  394. erased = 1;
  395. flash = (volatile unsigned long *) info->start[i];
  396. size = size >> 2; /* divide by 4 for longword access */
  397. for (k = 0; k < size; k++) {
  398. if (*flash++ != 0xffffffff) {
  399. erased = 0;
  400. break;
  401. }
  402. }
  403. if ((i % 5) == 0)
  404. printf ("\n");
  405. /* print empty and read-only info */
  406. printf (" %08lX%s%s",
  407. info->start[i],
  408. erased ? " E" : " ",
  409. info->protect[i] ? "RO " : " ");
  410. #else
  411. if ((i % 5) == 0)
  412. printf ("\n ");
  413. printf (" %08lX%s",
  414. info->start[i], info->protect[i] ? " (RO)" : " ");
  415. #endif
  416. }
  417. printf ("\n");
  418. return;
  419. }
  420. /*-----------------------------------------------------------------------
  421. * Copy memory to flash, returns:
  422. * 0 - OK
  423. * 1 - write timeout
  424. * 2 - Flash not erased
  425. */
  426. int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  427. {
  428. ulong wp;
  429. ulong cp;
  430. int aln;
  431. cfiword_t cword;
  432. int i, rc;
  433. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  434. int buffered_size;
  435. #endif
  436. int x8mode = 0;
  437. /* special handling of 16 bit devices in 8 bit mode */
  438. if ((info->interface == FLASH_CFI_X8X16)
  439. && (info->chipwidth == FLASH_CFI_BY8)) {
  440. switch (info->vendor) {
  441. case CFI_CMDSET_INTEL_STANDARD:
  442. case CFI_CMDSET_INTEL_EXTENDED:
  443. x8mode = info->portwidth;
  444. info->portwidth >>= 1; /* XXX - Need to test on x9/x16 in parallel. */
  445. /*info->portwidth = FLASH_CFI_8BIT; */ /* XXX - Need to test on x9/x16 in parallel. */
  446. break;
  447. case CFI_CMDSET_AMD_STANDARD:
  448. case CFI_CMDSET_AMD_EXTENDED:
  449. default:
  450. break;
  451. }
  452. }
  453. /* get lower aligned address */
  454. /* get lower aligned address */
  455. wp = (addr & ~(info->portwidth - 1));
  456. /* handle unaligned start */
  457. if ((aln = addr - wp) != 0) {
  458. cword.l = 0;
  459. cp = wp;
  460. for (i = 0; i < aln; ++i, ++cp)
  461. flash_add_byte (info, &cword, (*(uchar *) cp));
  462. for (; (i < info->portwidth) && (cnt > 0); i++) {
  463. flash_add_byte (info, &cword, *src++);
  464. cnt--;
  465. cp++;
  466. }
  467. for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
  468. flash_add_byte (info, &cword, (*(uchar *) cp));
  469. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  470. return rc;
  471. wp = cp;
  472. }
  473. /* handle the aligned part */
  474. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  475. buffered_size = (info->portwidth / info->chipwidth);
  476. buffered_size *= info->buffer_size;
  477. while (cnt >= info->portwidth) {
  478. i = buffered_size > cnt ? cnt : buffered_size;
  479. if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
  480. return rc;
  481. wp += i;
  482. src += i;
  483. cnt -= i;
  484. }
  485. #else
  486. while (cnt >= info->portwidth) {
  487. cword.l = 0;
  488. for (i = 0; i < info->portwidth; i++) {
  489. flash_add_byte (info, &cword, *src++);
  490. }
  491. if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
  492. return rc;
  493. wp += info->portwidth;
  494. cnt -= info->portwidth;
  495. }
  496. #endif /* CFG_FLASH_USE_BUFFER_WRITE */
  497. if (cnt == 0) {
  498. return (0);
  499. }
  500. /*
  501. * handle unaligned tail bytes
  502. */
  503. cword.l = 0;
  504. for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
  505. flash_add_byte (info, &cword, *src++);
  506. --cnt;
  507. }
  508. for (; i < info->portwidth; ++i, ++cp) {
  509. flash_add_byte (info, &cword, (*(uchar *) cp));
  510. }
  511. /* special handling of 16 bit devices in 8 bit mode */
  512. if (x8mode) {
  513. info->portwidth = x8mode;;
  514. }
  515. return flash_write_cfiword (info, wp, cword);
  516. }
  517. /*-----------------------------------------------------------------------
  518. */
  519. #ifdef CFG_FLASH_PROTECTION
  520. int flash_real_protect (flash_info_t * info, long sector, int prot)
  521. {
  522. int retcode = 0;
  523. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  524. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
  525. if (prot)
  526. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
  527. else
  528. flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
  529. if ((retcode =
  530. flash_full_status_check (info, sector, info->erase_blk_tout,
  531. prot ? "protect" : "unprotect")) == 0) {
  532. info->protect[sector] = prot;
  533. /* Intel's unprotect unprotects all locking */
  534. if (prot == 0) {
  535. flash_sect_t i;
  536. for (i = 0; i < info->sector_count; i++) {
  537. if (info->protect[i])
  538. flash_real_protect (info, i, 1);
  539. }
  540. }
  541. }
  542. return retcode;
  543. }
  544. /*-----------------------------------------------------------------------
  545. * flash_read_user_serial - read the OneTimeProgramming cells
  546. */
  547. void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
  548. int len)
  549. {
  550. uchar *src;
  551. uchar *dst;
  552. dst = buffer;
  553. src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
  554. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  555. memcpy (dst, src + offset, len);
  556. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  557. }
  558. /*
  559. * flash_read_factory_serial - read the device Id from the protection area
  560. */
  561. void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
  562. int len)
  563. {
  564. uchar *src;
  565. src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
  566. flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
  567. memcpy (buffer, src + offset, len);
  568. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  569. }
  570. #endif /* CFG_FLASH_PROTECTION */
  571. /*
  572. * flash_is_busy - check to see if the flash is busy
  573. * This routine checks the status of the chip and returns true if the chip is busy
  574. */
  575. static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
  576. {
  577. int retval;
  578. switch (info->vendor) {
  579. case CFI_CMDSET_INTEL_STANDARD:
  580. case CFI_CMDSET_INTEL_EXTENDED:
  581. retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
  582. break;
  583. case CFI_CMDSET_AMD_STANDARD:
  584. case CFI_CMDSET_AMD_EXTENDED:
  585. retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
  586. break;
  587. default:
  588. retval = 0;
  589. }
  590. debug ("flash_is_busy: %d\n", retval);
  591. return retval;
  592. }
  593. /*-----------------------------------------------------------------------
  594. * wait for XSR.7 to be set. Time out with an error if it does not.
  595. * This routine does not set the flash to read-array mode.
  596. */
  597. static int flash_status_check (flash_info_t * info, flash_sect_t sector,
  598. ulong tout, char *prompt)
  599. {
  600. ulong start;
  601. /* Wait for command completion */
  602. start = get_timer (0);
  603. while (flash_is_busy (info, sector)) {
  604. if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
  605. printf ("Flash %s timeout at address %lx data %lx\n",
  606. prompt, info->start[sector],
  607. flash_read_long (info, sector, 0));
  608. flash_write_cmd (info, sector, 0, info->cmd_reset);
  609. return ERR_TIMOUT;
  610. }
  611. }
  612. return ERR_OK;
  613. }
  614. /*-----------------------------------------------------------------------
  615. * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
  616. * This routine sets the flash to read-array mode.
  617. */
  618. static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  619. ulong tout, char *prompt)
  620. {
  621. int retcode;
  622. retcode = flash_status_check (info, sector, tout, prompt);
  623. switch (info->vendor) {
  624. case CFI_CMDSET_INTEL_EXTENDED:
  625. case CFI_CMDSET_INTEL_STANDARD:
  626. if ((retcode != ERR_OK)
  627. && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
  628. retcode = ERR_INVAL;
  629. printf ("Flash %s error at address %lx\n", prompt,
  630. info->start[sector]);
  631. if (flash_isset
  632. (info, sector, 0,
  633. FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
  634. printf ("Command Sequence Error.\n");
  635. } else if (flash_isset
  636. (info, sector, 0, FLASH_STATUS_ECLBS)) {
  637. printf ("Block Erase Error.\n");
  638. retcode = ERR_NOT_ERASED;
  639. } else if (flash_isset
  640. (info, sector, 0, FLASH_STATUS_PSLBS)) {
  641. printf ("Locking Error\n");
  642. }
  643. if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
  644. printf ("Block locked.\n");
  645. retcode = ERR_PROTECTED;
  646. }
  647. if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
  648. printf ("Vpp Low Error.\n");
  649. }
  650. flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
  651. break;
  652. default:
  653. break;
  654. }
  655. return retcode;
  656. }
  657. /*-----------------------------------------------------------------------
  658. */
  659. static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
  660. {
  661. switch (info->portwidth) {
  662. case FLASH_CFI_8BIT:
  663. cword->c = c;
  664. break;
  665. case FLASH_CFI_16BIT:
  666. cword->w = (cword->w << 8) | c;
  667. break;
  668. case FLASH_CFI_32BIT:
  669. cword->l = (cword->l << 8) | c;
  670. break;
  671. case FLASH_CFI_64BIT:
  672. cword->ll = (cword->ll << 8) | c;
  673. break;
  674. }
  675. }
  676. /*-----------------------------------------------------------------------
  677. * make a proper sized command based on the port and chip widths
  678. */
  679. static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
  680. {
  681. int i;
  682. #if defined(__LITTLE_ENDIAN)
  683. ushort stmp;
  684. #endif
  685. uchar *cp = (uchar *) cmdbuf;
  686. for (i = 0; i < info->portwidth; i++)
  687. *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
  688. #if defined(__LITTLE_ENDIAN)
  689. if (info->portwidth == 2) {
  690. stmp = *(ushort *) cmdbuf;
  691. *(ushort *) cmdbuf = swab16 (stmp);
  692. }
  693. #endif
  694. }
  695. /*
  696. * Write a proper sized command to the correct address
  697. */
  698. static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
  699. uint offset, uchar cmd)
  700. {
  701. volatile cfiptr_t addr;
  702. cfiword_t cword;
  703. addr.cp = flash_make_addr (info, sect, offset);
  704. flash_make_cmd (info, cmd, &cword);
  705. switch (info->portwidth) {
  706. case FLASH_CFI_8BIT:
  707. debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
  708. cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  709. *addr.cp = cword.c;
  710. break;
  711. case FLASH_CFI_16BIT:
  712. debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
  713. cmd, cword.w,
  714. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  715. *addr.wp = cword.w;
  716. break;
  717. case FLASH_CFI_32BIT:
  718. debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
  719. cmd, cword.l,
  720. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  721. *addr.lp = cword.l;
  722. break;
  723. case FLASH_CFI_64BIT:
  724. #ifdef DEBUG
  725. {
  726. char str[20];
  727. print_longlong (str, cword.ll);
  728. debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
  729. addr.llp, cmd, str,
  730. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  731. }
  732. #endif
  733. *addr.llp = cword.ll;
  734. break;
  735. }
  736. }
  737. static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
  738. {
  739. flash_write_cmd (info, sect, 0x555, 0xAA);
  740. flash_write_cmd (info, sect, 0x2AA, 0x55);
  741. }
  742. /*-----------------------------------------------------------------------
  743. */
  744. static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset,
  745. uchar cmd)
  746. {
  747. cfiptr_t cptr;
  748. cfiword_t cword;
  749. int retval;
  750. cptr.cp = flash_make_addr (info, sect, offset);
  751. flash_make_cmd (info, cmd, &cword);
  752. debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
  753. switch (info->portwidth) {
  754. case FLASH_CFI_8BIT:
  755. debug ("is= %x %x\n", cptr.cp[0], cword.c);
  756. retval = (cptr.cp[0] == cword.c);
  757. break;
  758. case FLASH_CFI_16BIT:
  759. debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
  760. retval = (cptr.wp[0] == cword.w);
  761. break;
  762. case FLASH_CFI_32BIT:
  763. debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
  764. retval = (cptr.lp[0] == cword.l);
  765. break;
  766. case FLASH_CFI_64BIT:
  767. #ifdef DEBUG
  768. {
  769. char str1[20];
  770. char str2[20];
  771. print_longlong (str1, cptr.llp[0]);
  772. print_longlong (str2, cword.ll);
  773. debug ("is= %s %s\n", str1, str2);
  774. }
  775. #endif
  776. retval = (cptr.llp[0] == cword.ll);
  777. break;
  778. default:
  779. retval = 0;
  780. break;
  781. }
  782. return retval;
  783. }
  784. /*-----------------------------------------------------------------------
  785. */
  786. static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset,
  787. uchar cmd)
  788. {
  789. cfiptr_t cptr;
  790. cfiword_t cword;
  791. int retval;
  792. cptr.cp = flash_make_addr (info, sect, offset);
  793. flash_make_cmd (info, cmd, &cword);
  794. switch (info->portwidth) {
  795. case FLASH_CFI_8BIT:
  796. retval = ((cptr.cp[0] & cword.c) == cword.c);
  797. break;
  798. case FLASH_CFI_16BIT:
  799. retval = ((cptr.wp[0] & cword.w) == cword.w);
  800. break;
  801. case FLASH_CFI_32BIT:
  802. retval = ((cptr.lp[0] & cword.l) == cword.l);
  803. break;
  804. case FLASH_CFI_64BIT:
  805. retval = ((cptr.llp[0] & cword.ll) == cword.ll);
  806. break;
  807. default:
  808. retval = 0;
  809. break;
  810. }
  811. return retval;
  812. }
  813. /*-----------------------------------------------------------------------
  814. */
  815. static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset,
  816. uchar cmd)
  817. {
  818. cfiptr_t cptr;
  819. cfiword_t cword;
  820. int retval;
  821. cptr.cp = flash_make_addr (info, sect, offset);
  822. flash_make_cmd (info, cmd, &cword);
  823. switch (info->portwidth) {
  824. case FLASH_CFI_8BIT:
  825. retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
  826. break;
  827. case FLASH_CFI_16BIT:
  828. retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
  829. break;
  830. case FLASH_CFI_32BIT:
  831. retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
  832. break;
  833. case FLASH_CFI_64BIT:
  834. retval = ((cptr.llp[0] & cword.ll) !=
  835. (cptr.llp[0] & cword.ll));
  836. break;
  837. default:
  838. retval = 0;
  839. break;
  840. }
  841. return retval;
  842. }
  843. /*-----------------------------------------------------------------------
  844. * detect if flash is compatible with the Common Flash Interface (CFI)
  845. * http://www.jedec.org/download/search/jesd68.pdf
  846. *
  847. */
  848. static int flash_detect_cfi (flash_info_t * info)
  849. {
  850. debug ("flash detect cfi\n");
  851. for (info->portwidth = FLASH_CFI_8BIT;
  852. info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
  853. for (info->chipwidth = FLASH_CFI_BY8;
  854. info->chipwidth <= info->portwidth;
  855. info->chipwidth <<= 1) {
  856. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  857. flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
  858. FLASH_CMD_CFI);
  859. if (flash_isequal
  860. (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
  861. && flash_isequal (info, 0,
  862. FLASH_OFFSET_CFI_RESP + 1, 'R')
  863. && flash_isequal (info, 0,
  864. FLASH_OFFSET_CFI_RESP + 2,
  865. 'Y')) {
  866. info->interface =
  867. flash_read_ushort (info, 0,
  868. FLASH_OFFSET_INTERFACE);
  869. debug ("device interface is %d\n",
  870. info->interface);
  871. debug ("found port %d chip %d ",
  872. info->portwidth, info->chipwidth);
  873. debug ("port %d bits chip %d bits\n",
  874. info->
  875. portwidth << CFI_FLASH_SHIFT_WIDTH,
  876. info->
  877. chipwidth << CFI_FLASH_SHIFT_WIDTH);
  878. return 1;
  879. }
  880. }
  881. }
  882. debug ("not found\n");
  883. return 0;
  884. }
  885. /*
  886. * The following code cannot be run from FLASH!
  887. *
  888. */
  889. static ulong flash_get_size (ulong base, int banknum)
  890. {
  891. flash_info_t *info = &flash_info[banknum];
  892. int i, j;
  893. flash_sect_t sect_cnt;
  894. unsigned long sector;
  895. unsigned long tmp;
  896. int size_ratio;
  897. uchar num_erase_regions;
  898. int erase_region_size;
  899. int erase_region_count;
  900. info->start[0] = base;
  901. if (flash_detect_cfi (info)) {
  902. info->vendor =
  903. flash_read_ushort (info, 0,
  904. FLASH_OFFSET_PRIMARY_VENDOR);
  905. #ifdef DEBUG
  906. flash_printqry (info, 0);
  907. #endif
  908. switch (info->vendor) {
  909. case CFI_CMDSET_INTEL_STANDARD:
  910. case CFI_CMDSET_INTEL_EXTENDED:
  911. default:
  912. info->cmd_reset = FLASH_CMD_RESET;
  913. break;
  914. case CFI_CMDSET_AMD_STANDARD:
  915. case CFI_CMDSET_AMD_EXTENDED:
  916. info->cmd_reset = AMD_CMD_RESET;
  917. break;
  918. }
  919. debug ("manufacturer is %d\n", info->vendor);
  920. size_ratio = info->portwidth / info->chipwidth;
  921. /* if the chip is x8/x16 reduce the ratio by half */
  922. if ((info->interface == FLASH_CFI_X8X16)
  923. && (info->chipwidth == FLASH_CFI_BY8)) {
  924. size_ratio >>= 1;
  925. }
  926. num_erase_regions =
  927. flash_read_uchar (info,
  928. FLASH_OFFSET_NUM_ERASE_REGIONS);
  929. debug ("size_ratio %d port %d bits chip %d bits\n",
  930. size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  931. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  932. debug ("found %d erase regions\n", num_erase_regions);
  933. sect_cnt = 0;
  934. sector = base;
  935. for (i = 0; i < num_erase_regions; i++) {
  936. if (i > NUM_ERASE_REGIONS) {
  937. printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
  938. break;
  939. }
  940. tmp = flash_read_long (info, 0,
  941. FLASH_OFFSET_ERASE_REGIONS +
  942. i * 4);
  943. erase_region_size =
  944. (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
  945. tmp >>= 16;
  946. erase_region_count = (tmp & 0xffff) + 1;
  947. printf ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size);
  948. for (j = 0; j < erase_region_count; j++) {
  949. info->start[sect_cnt] = sector;
  950. sector += (erase_region_size * size_ratio);
  951. info->protect[sect_cnt] =
  952. flash_isset (info, sect_cnt,
  953. FLASH_OFFSET_PROTECT,
  954. FLASH_STATUS_PROTECT);
  955. sect_cnt++;
  956. }
  957. }
  958. info->sector_count = sect_cnt;
  959. /* multiply the size by the number of chips */
  960. info->size =
  961. (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
  962. size_ratio;
  963. info->buffer_size =
  964. (1 <<
  965. flash_read_ushort (info, 0,
  966. FLASH_OFFSET_BUFFER_SIZE));
  967. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
  968. info->erase_blk_tout =
  969. (tmp *
  970. (1 <<
  971. flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
  972. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
  973. info->buffer_write_tout =
  974. (tmp *
  975. (1 <<
  976. flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
  977. tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
  978. info->write_tout =
  979. (tmp *
  980. (1 <<
  981. flash_read_uchar (info,
  982. FLASH_OFFSET_WMAX_TOUT))) / 1000;
  983. info->flash_id = FLASH_MAN_CFI;
  984. }
  985. flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
  986. return (info->size);
  987. }
  988. /*-----------------------------------------------------------------------
  989. */
  990. static int flash_write_cfiword (flash_info_t * info, ulong dest,
  991. cfiword_t cword)
  992. {
  993. cfiptr_t ctladdr;
  994. cfiptr_t cptr;
  995. int flag;
  996. ctladdr.cp = flash_make_addr (info, 0, 0);
  997. cptr.cp = (uchar *) dest;
  998. /* Check if Flash is (sufficiently) erased */
  999. switch (info->portwidth) {
  1000. case FLASH_CFI_8BIT:
  1001. flag = ((cptr.cp[0] & cword.c) == cword.c);
  1002. break;
  1003. case FLASH_CFI_16BIT:
  1004. flag = ((cptr.wp[0] & cword.w) == cword.w);
  1005. break;
  1006. case FLASH_CFI_32BIT:
  1007. flag = ((cptr.lp[0] & cword.l) == cword.l);
  1008. break;
  1009. case FLASH_CFI_64BIT:
  1010. flag = ((cptr.lp[0] & cword.ll) == cword.ll);
  1011. break;
  1012. default:
  1013. return 2;
  1014. }
  1015. if (!flag)
  1016. return 2;
  1017. /* Disable interrupts which might cause a timeout here */
  1018. flag = disable_interrupts ();
  1019. switch (info->vendor) {
  1020. case CFI_CMDSET_INTEL_EXTENDED:
  1021. case CFI_CMDSET_INTEL_STANDARD:
  1022. flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
  1023. flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
  1024. break;
  1025. case CFI_CMDSET_AMD_EXTENDED:
  1026. case CFI_CMDSET_AMD_STANDARD:
  1027. flash_unlock_seq (info, 0);
  1028. flash_write_cmd (info, 0, 0x555, AMD_CMD_WRITE);
  1029. break;
  1030. }
  1031. switch (info->portwidth) {
  1032. case FLASH_CFI_8BIT:
  1033. cptr.cp[0] = cword.c;
  1034. break;
  1035. case FLASH_CFI_16BIT:
  1036. cptr.wp[0] = cword.w;
  1037. break;
  1038. case FLASH_CFI_32BIT:
  1039. cptr.lp[0] = cword.l;
  1040. break;
  1041. case FLASH_CFI_64BIT:
  1042. cptr.llp[0] = cword.ll;
  1043. break;
  1044. }
  1045. /* re-enable interrupts if necessary */
  1046. if (flag)
  1047. enable_interrupts ();
  1048. return flash_full_status_check (info, 0, info->write_tout, "write");
  1049. }
  1050. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  1051. /* loop through the sectors from the highest address
  1052. * when the passed address is greater or equal to the sector address
  1053. * we have a match
  1054. */
  1055. static flash_sect_t find_sector (flash_info_t * info, ulong addr)
  1056. {
  1057. flash_sect_t sector;
  1058. for (sector = info->sector_count - 1; sector >= 0; sector--) {
  1059. if (addr >= info->start[sector])
  1060. break;
  1061. }
  1062. return sector;
  1063. }
  1064. static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
  1065. int len)
  1066. {
  1067. flash_sect_t sector;
  1068. int cnt;
  1069. int retcode;
  1070. volatile cfiptr_t src;
  1071. volatile cfiptr_t dst;
  1072. src.cp = cp;
  1073. dst.cp = (uchar *) dest;
  1074. sector = find_sector (info, dest);
  1075. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1076. flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
  1077. if ((retcode =
  1078. flash_status_check (info, sector, info->buffer_write_tout,
  1079. "write to buffer")) == ERR_OK) {
  1080. /* reduce the number of loops by the width of the port */
  1081. switch (info->portwidth) {
  1082. case FLASH_CFI_8BIT:
  1083. cnt = len;
  1084. break;
  1085. case FLASH_CFI_16BIT:
  1086. cnt = len >> 1;
  1087. break;
  1088. case FLASH_CFI_32BIT:
  1089. cnt = len >> 2;
  1090. break;
  1091. case FLASH_CFI_64BIT:
  1092. cnt = len >> 3;
  1093. break;
  1094. default:
  1095. return ERR_INVAL;
  1096. break;
  1097. }
  1098. flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
  1099. while (cnt-- > 0) {
  1100. switch (info->portwidth) {
  1101. case FLASH_CFI_8BIT:
  1102. *dst.cp++ = *src.cp++;
  1103. break;
  1104. case FLASH_CFI_16BIT:
  1105. *dst.wp++ = *src.wp++;
  1106. break;
  1107. case FLASH_CFI_32BIT:
  1108. *dst.lp++ = *src.lp++;
  1109. break;
  1110. case FLASH_CFI_64BIT:
  1111. *dst.llp++ = *src.llp++;
  1112. break;
  1113. default:
  1114. return ERR_INVAL;
  1115. break;
  1116. }
  1117. }
  1118. flash_write_cmd (info, sector, 0,
  1119. FLASH_CMD_WRITE_BUFFER_CONFIRM);
  1120. retcode =
  1121. flash_full_status_check (info, sector,
  1122. info->buffer_write_tout,
  1123. "buffer write");
  1124. }
  1125. flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  1126. return retcode;
  1127. }
  1128. #endif /* CFG_USE_FLASH_BUFFER_WRITE */
  1129. #endif /* CFG_FLASH_CFI */