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  1. /*
  2. * armboot - Startup Code for ARM720 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <config.h>
  26. #include <version.h>
  27. #ifdef CONFIG_NETARM
  28. #include <asm/arch/netarm_registers.h>
  29. #endif
  30. /*
  31. *************************************************************************
  32. *
  33. * Jump vector table as in table 3.1 in [1]
  34. *
  35. *************************************************************************
  36. */
  37. .globl _start
  38. _start: b reset
  39. ldr pc, _undefined_instruction
  40. ldr pc, _software_interrupt
  41. ldr pc, _prefetch_abort
  42. ldr pc, _data_abort
  43. ldr pc, _not_used
  44. ldr pc, _irq
  45. ldr pc, _fiq
  46. _undefined_instruction: .word undefined_instruction
  47. _software_interrupt: .word software_interrupt
  48. _prefetch_abort: .word prefetch_abort
  49. _data_abort: .word data_abort
  50. _not_used: .word not_used
  51. _irq: .word irq
  52. _fiq: .word fiq
  53. .balignl 16,0xdeadbeef
  54. /*
  55. *************************************************************************
  56. *
  57. * Startup Code (reset vector)
  58. *
  59. * do important init only if we don't start from RAM!
  60. * relocate armboot to ram
  61. * setup stack
  62. * jump to second stage
  63. *
  64. *************************************************************************
  65. */
  66. _TEXT_BASE:
  67. .word TEXT_BASE
  68. .globl _armboot_start
  69. _armboot_start:
  70. .word _start
  71. /*
  72. * These are defined in the board-specific linker script.
  73. */
  74. .globl _bss_start
  75. _bss_start:
  76. .word __bss_start
  77. .globl _bss_end
  78. _bss_end:
  79. .word _end
  80. #ifdef CONFIG_USE_IRQ
  81. /* IRQ stack memory (calculated at run-time) */
  82. .globl IRQ_STACK_START
  83. IRQ_STACK_START:
  84. .word 0x0badc0de
  85. /* IRQ stack memory (calculated at run-time) */
  86. .globl FIQ_STACK_START
  87. FIQ_STACK_START:
  88. .word 0x0badc0de
  89. #endif
  90. /*
  91. * the actual reset code
  92. */
  93. reset:
  94. /*
  95. * set the cpu to SVC32 mode
  96. */
  97. mrs r0,cpsr
  98. bic r0,r0,#0x1f
  99. orr r0,r0,#0x13
  100. msr cpsr,r0
  101. /*
  102. * we do sys-critical inits only at reboot,
  103. * not when booting from ram!
  104. */
  105. #ifdef CONFIG_INIT_CRITICAL
  106. bl cpu_init_crit
  107. #endif
  108. relocate: /* relocate U-Boot to RAM */
  109. adr r0, _start /* r0 <- current position of code */
  110. ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
  111. cmp r0, r1 /* don't reloc during debug */
  112. beq stack_setup
  113. ldr r2, _armboot_start
  114. ldr r3, _bss_start
  115. sub r2, r3, r2 /* r2 <- size of armboot */
  116. add r2, r0, r2 /* r2 <- source end address */
  117. copy_loop:
  118. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  119. stmia r1!, {r3-r10} /* copy to target address [r1] */
  120. cmp r0, r2 /* until source end addreee [r2] */
  121. ble copy_loop
  122. /* Set up the stack */
  123. stack_setup:
  124. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  125. sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
  126. sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
  127. #ifdef CONFIG_USE_IRQ
  128. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  129. #endif
  130. sub sp, r0, #12 /* leave 3 words for abort-stack */
  131. clear_bss:
  132. ldr r0, _bss_start /* find start of bss segment */
  133. add r0, r0, #4 /* start at first byte of bss */
  134. ldr r1, _bss_end /* stop here */
  135. mov r2, #0x00000000 /* clear */
  136. clbss_l:str r2, [r0] /* clear loop... */
  137. add r0, r0, #4
  138. cmp r0, r1
  139. bne clbss_l
  140. ldr pc, _start_armboot
  141. _start_armboot: .word start_armboot
  142. /*
  143. *************************************************************************
  144. *
  145. * CPU_init_critical registers
  146. *
  147. * setup important registers
  148. * setup memory timing
  149. *
  150. *************************************************************************
  151. */
  152. /* Interupt-Controller base addresses */
  153. INTMR1: .word 0x80000280 @ 32 bit size
  154. INTMR2: .word 0x80001280 @ 16 bit size
  155. INTMR3: .word 0x80002280 @ 8 bit size
  156. /* SYSCONs */
  157. SYSCON1: .word 0x80000100
  158. SYSCON2: .word 0x80001100
  159. SYSCON3: .word 0x80002200
  160. #define CLKCTL 0x6 /* mask */
  161. #define CLKCTL_18 0x0 /* 18.432 MHz */
  162. #define CLKCTL_36 0x2 /* 36.864 MHz */
  163. #define CLKCTL_49 0x4 /* 49.152 MHz */
  164. #define CLKCTL_73 0x6 /* 73.728 MHz */
  165. cpu_init_crit:
  166. #ifndef CONFIG_NETARM
  167. /*
  168. * mask all IRQs by clearing all bits in the INTMRs
  169. */
  170. mov r1, #0x00
  171. ldr r0, INTMR1
  172. str r1, [r0]
  173. ldr r0, INTMR2
  174. str r1, [r0]
  175. ldr r0, INTMR3
  176. str r1, [r0]
  177. /*
  178. * flush v4 I/D caches
  179. */
  180. mov r0, #0
  181. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  182. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  183. /*
  184. * disable MMU stuff and caches
  185. */
  186. mrc p15,0,r0,c1,c0
  187. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  188. bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
  189. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  190. mcr p15,0,r0,c1,c0
  191. #else /* CONFIG_NETARM */
  192. /*
  193. * prior to software reset : need to set pin PORTC4 to be *HRESET
  194. */
  195. ldr r0, =NETARM_GEN_MODULE_BASE
  196. ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
  197. NETARM_GEN_PORT_DIR(0x10))
  198. str r1, [r0, #+NETARM_GEN_PORTC]
  199. /*
  200. * software reset : see HW Ref. Guide 8.2.4 : Software Service register
  201. * for an explanation of this process
  202. */
  203. ldr r0, =NETARM_GEN_MODULE_BASE
  204. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  205. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  206. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  207. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  208. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  209. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  210. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  211. str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
  212. /*
  213. * setup PLL and System Config
  214. */
  215. ldr r0, =NETARM_GEN_MODULE_BASE
  216. ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
  217. NETARM_GEN_SYS_CFG_BUSFULL | \
  218. NETARM_GEN_SYS_CFG_USER_EN | \
  219. NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
  220. NETARM_GEN_SYS_CFG_BUSARB_INT | \
  221. NETARM_GEN_SYS_CFG_BUSMON_EN )
  222. str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
  223. ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
  224. NETARM_GEN_PLL_CTL_POLTST_DEF | \
  225. NETARM_GEN_PLL_CTL_INDIV(1) | \
  226. NETARM_GEN_PLL_CTL_ICP_DEF | \
  227. NETARM_GEN_PLL_CTL_OUTDIV(2) )
  228. str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
  229. /*
  230. * mask all IRQs by clearing all bits in the INTMRs
  231. */
  232. mov r1, #0
  233. ldr r0, =NETARM_GEN_MODULE_BASE
  234. str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
  235. #endif /* CONFIG_NETARM */
  236. #ifdef CONFIG_ARM7_REVD
  237. /* set clock speed */
  238. /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
  239. /* !!! not doing DRAM refresh properly! */
  240. ldr r0, SYSCON3
  241. ldr r1, [r0]
  242. bic r1, r1, #CLKCTL
  243. orr r1, r1, #CLKCTL_36
  244. str r1, [r0]
  245. #endif
  246. /*
  247. * before relocating, we have to setup RAM timing
  248. * because memory timing is board-dependent, you will
  249. * find a memsetup.S in your board directory.
  250. */
  251. mov ip, lr
  252. bl memsetup
  253. mov lr, ip
  254. mov pc, lr
  255. /*
  256. *************************************************************************
  257. *
  258. * Interrupt handling
  259. *
  260. *************************************************************************
  261. */
  262. @
  263. @ IRQ stack frame.
  264. @
  265. #define S_FRAME_SIZE 72
  266. #define S_OLD_R0 68
  267. #define S_PSR 64
  268. #define S_PC 60
  269. #define S_LR 56
  270. #define S_SP 52
  271. #define S_IP 48
  272. #define S_FP 44
  273. #define S_R10 40
  274. #define S_R9 36
  275. #define S_R8 32
  276. #define S_R7 28
  277. #define S_R6 24
  278. #define S_R5 20
  279. #define S_R4 16
  280. #define S_R3 12
  281. #define S_R2 8
  282. #define S_R1 4
  283. #define S_R0 0
  284. #define MODE_SVC 0x13
  285. #define I_BIT 0x80
  286. /*
  287. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  288. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  289. */
  290. .macro bad_save_user_regs
  291. sub sp, sp, #S_FRAME_SIZE
  292. stmia sp, {r0 - r12} @ Calling r0-r12
  293. add r8, sp, #S_PC
  294. ldr r2, _armboot_start
  295. sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
  296. sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
  297. ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
  298. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  299. add r5, sp, #S_SP
  300. mov r1, lr
  301. stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
  302. mov r0, sp
  303. .endm
  304. .macro irq_save_user_regs
  305. sub sp, sp, #S_FRAME_SIZE
  306. stmia sp, {r0 - r12} @ Calling r0-r12
  307. add r8, sp, #S_PC
  308. stmdb r8, {sp, lr}^ @ Calling SP, LR
  309. str lr, [r8, #0] @ Save calling PC
  310. mrs r6, spsr
  311. str r6, [r8, #4] @ Save CPSR
  312. str r0, [r8, #8] @ Save OLD_R0
  313. mov r0, sp
  314. .endm
  315. .macro irq_restore_user_regs
  316. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  317. mov r0, r0
  318. ldr lr, [sp, #S_PC] @ Get PC
  319. add sp, sp, #S_FRAME_SIZE
  320. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  321. .endm
  322. .macro get_bad_stack
  323. ldr r13, _armboot_start @ setup our mode stack
  324. sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
  325. sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
  326. str lr, [r13] @ save caller lr / spsr
  327. mrs lr, spsr
  328. str lr, [r13, #4]
  329. mov r13, #MODE_SVC @ prepare SVC-Mode
  330. msr spsr_c, r13
  331. mov lr, pc
  332. movs pc, lr
  333. .endm
  334. .macro get_irq_stack @ setup IRQ stack
  335. ldr sp, IRQ_STACK_START
  336. .endm
  337. .macro get_fiq_stack @ setup FIQ stack
  338. ldr sp, FIQ_STACK_START
  339. .endm
  340. /*
  341. * exception handlers
  342. */
  343. .align 5
  344. undefined_instruction:
  345. get_bad_stack
  346. bad_save_user_regs
  347. bl do_undefined_instruction
  348. .align 5
  349. software_interrupt:
  350. get_bad_stack
  351. bad_save_user_regs
  352. bl do_software_interrupt
  353. .align 5
  354. prefetch_abort:
  355. get_bad_stack
  356. bad_save_user_regs
  357. bl do_prefetch_abort
  358. .align 5
  359. data_abort:
  360. get_bad_stack
  361. bad_save_user_regs
  362. bl do_data_abort
  363. .align 5
  364. not_used:
  365. get_bad_stack
  366. bad_save_user_regs
  367. bl do_not_used
  368. #ifdef CONFIG_USE_IRQ
  369. .align 5
  370. irq:
  371. get_irq_stack
  372. irq_save_user_regs
  373. bl do_irq
  374. irq_restore_user_regs
  375. .align 5
  376. fiq:
  377. get_fiq_stack
  378. /* someone ought to write a more effiction fiq_save_user_regs */
  379. irq_save_user_regs
  380. bl do_fiq
  381. irq_restore_user_regs
  382. #else
  383. .align 5
  384. irq:
  385. get_bad_stack
  386. bad_save_user_regs
  387. bl do_irq
  388. .align 5
  389. fiq:
  390. get_bad_stack
  391. bad_save_user_regs
  392. bl do_fiq
  393. #endif
  394. .align 5
  395. .globl reset_cpu
  396. reset_cpu:
  397. #ifndef CONFIG_NETARM
  398. mov ip, #0
  399. mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
  400. mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
  401. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  402. bic ip, ip, #0x000f @ ............wcam
  403. bic ip, ip, #0x2100 @ ..v....s........
  404. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  405. mov pc, r0
  406. #else
  407. ldr r1, =NETARM_MEM_MODULE_BASE
  408. ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
  409. ldr r1, =0xFFFFF000
  410. and r0, r1, r0
  411. ldr r1, =(relocate-TEXT_BASE)
  412. add r0, r1, r0
  413. ldr r4, =NETARM_GEN_MODULE_BASE
  414. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  415. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  416. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  417. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  418. ldr r1, =NETARM_GEN_SW_SVC_RESETA
  419. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  420. ldr r1, =NETARM_GEN_SW_SVC_RESETB
  421. str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
  422. mov pc, r0
  423. #endif