cpu.c 3.9 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Alex Zuepke <azu@sysgo.de>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. * CPU specific code
  30. */
  31. #include <common.h>
  32. #include <command.h>
  33. #include <clps7111.h>
  34. /* read co-processor 15, register #1 (control register) */
  35. static unsigned long read_p15_c1(void)
  36. {
  37. unsigned long value;
  38. __asm__ __volatile__(
  39. "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
  40. : "=r" (value)
  41. :
  42. : "memory");
  43. /* printf("p15/c1 is = %08lx\n", value); */
  44. return value;
  45. }
  46. /* write to co-processor 15, register #1 (control register) */
  47. static void write_p15_c1(unsigned long value)
  48. {
  49. /* printf("write %08lx to p15/c1\n", value); */
  50. __asm__ __volatile__(
  51. "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
  52. :
  53. : "r" (value)
  54. : "memory");
  55. read_p15_c1();
  56. }
  57. static void cp_delay (void)
  58. {
  59. volatile int i;
  60. /* copro seems to need some delay between reading and writing */
  61. for (i = 0; i < 100; i++);
  62. }
  63. /* See also ARM Ref. Man. */
  64. #define C1_MMU (1<<0) /* mmu off/on */
  65. #define C1_ALIGN (1<<1) /* alignment faults off/on */
  66. #define C1_IDC (1<<2) /* icache and/or dcache off/on */
  67. #define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
  68. #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
  69. #define C1_SYS_PROT (1<<8) /* system protection */
  70. #define C1_ROM_PROT (1<<9) /* ROM protection */
  71. #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  72. int cpu_init (void)
  73. {
  74. /*
  75. * setup up stacks if necessary
  76. */
  77. #ifdef CONFIG_USE_IRQ
  78. DECLARE_GLOBAL_DATA_PTR;
  79. IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  80. FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  81. #endif
  82. return 0;
  83. }
  84. int cleanup_before_linux (void)
  85. {
  86. /*
  87. * this function is called just before we call linux
  88. * it prepares the processor for linux
  89. *
  90. * we turn off caches etc ...
  91. * and we set the CPU-speed to 73 MHz - see start.S for details
  92. */
  93. unsigned long i;
  94. disable_interrupts ();
  95. #ifdef CONFIG_NETARM
  96. return 0;
  97. #endif
  98. /* turn off I-cache */
  99. asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  100. i &= ~0x1000;
  101. asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  102. /* flush I-cache */
  103. asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  104. #ifdef CONFIG_ARM7_REVD
  105. /* go to high speed */
  106. IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
  107. #endif
  108. return 0;
  109. }
  110. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  111. {
  112. extern void reset_cpu (ulong addr);
  113. disable_interrupts ();
  114. reset_cpu (0);
  115. /*NOTREACHED*/
  116. return (0);
  117. }
  118. void icache_enable (void)
  119. {
  120. ulong reg;
  121. reg = read_p15_c1 ();
  122. cp_delay ();
  123. write_p15_c1 (reg | C1_IDC);
  124. }
  125. void icache_disable (void)
  126. {
  127. ulong reg;
  128. reg = read_p15_c1 ();
  129. cp_delay ();
  130. write_p15_c1 (reg & ~C1_IDC);
  131. }
  132. int icache_status (void)
  133. {
  134. return (read_p15_c1 () & C1_IDC) != 0;
  135. }
  136. void dcache_enable (void)
  137. {
  138. ulong reg;
  139. reg = read_p15_c1 ();
  140. cp_delay ();
  141. write_p15_c1 (reg | C1_IDC);
  142. }
  143. void dcache_disable (void)
  144. {
  145. ulong reg;
  146. reg = read_p15_c1 ();
  147. cp_delay ();
  148. write_p15_c1 (reg & ~C1_IDC);
  149. }
  150. int dcache_status (void)
  151. {
  152. return (read_p15_c1 () & C1_IDC) != 0;
  153. }