memsetup.S 5.9 KB

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  1. /*
  2. * Memory Setup stuff - taken from Linux
  3. *
  4. * Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
  5. * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <config.h>
  26. #include <version.h>
  27. #include <asm/arch/netarm_registers.h>
  28. /* some parameters for the board */
  29. #define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
  30. #define FLASH_70ns_WAIT_STATES 4
  31. #define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
  32. #if 1
  33. #define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
  34. #else
  35. #define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
  36. #endif
  37. #define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
  38. #define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
  39. #define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
  40. #define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
  41. #if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
  42. #define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
  43. #define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
  44. #endif
  45. #define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
  46. #define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
  47. /* setting up the memory */
  48. .globl memsetup
  49. memsetup:
  50. #if defined(CONFIG_MODNET50)
  51. ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
  52. _jump_to_high:
  53. /*
  54. * MEM Config Reg
  55. * ---------------------------------------------------
  56. */
  57. ldr r0, =NETARM_MEM_MODULE_BASE
  58. ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
  59. NETARM_MEM_CFG_REFRESH_EN | \
  60. NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
  61. str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
  62. memsetup_cs0:
  63. /*
  64. * Base Addr / Option Reg 0 (Flash)
  65. * ---------------------------------------------------
  66. */
  67. ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
  68. NETARM_MEM_BAR_DRAM_FP | \
  69. NETARM_MEM_BAR_DRAM_MUX_INT | \
  70. NETARM_MEM_BAR_DRAM_MUX_BAL | \
  71. NETARM_MEM_BAR_VALID )
  72. str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
  73. /* trust that the bus size for flash was strapped correctly */
  74. /* this saves the bus width in r2 and then ORs it back in */
  75. /* it's pretty safe assumption, otherwise it wouldn't boot */
  76. ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
  77. and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
  78. /* just a test: assume 32 bit flash mem */
  79. /* mov r2, #NETARM_MEM_OPT_32BIT */
  80. ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
  81. NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
  82. NETARM_MEM_OPT_BCYC_4 | \
  83. NETARM_MEM_OPT_BSIZE_16 | \
  84. NETARM_MEM_OPT_16BIT | \
  85. NETARM_MEM_OPT_READ_ASYNC | \
  86. NETARM_MEM_OPT_WRITE_ASYNC )
  87. orr r1, r1, r2
  88. str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
  89. memsetup_cs1:
  90. /*
  91. * Base Addr / Option Reg 1 (DRAM #1)
  92. * ---------------------------------------------------
  93. */
  94. #ifdef CONFIG_NETARM_NET40_REV2
  95. /* we have to config SDRAM in burst mode */
  96. ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
  97. NETARM_MEM_OPT_BCYC_2 | \
  98. NETARM_MEM_OPT_BSIZE_16 | \
  99. NETARM_MEM_OPT_WAIT_STATES(0) | \
  100. NETARM_MEM_OPT_32BIT | \
  101. NETARM_MEM_OPT_READ_ASYNC | \
  102. NETARM_MEM_OPT_WRITE_ASYNC )
  103. str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
  104. ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
  105. NETARM_MEM_BAR_DRAM_SYNC | \
  106. NETARM_MEM_BAR_DRAM_MUX_INT | \
  107. NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
  108. NETARM_MEM_BAR_DRAM_SEL | \
  109. NETARM_MEM_BAR_BURST_EN | \
  110. NETARM_MEM_BAR_VALID )
  111. str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
  112. #else
  113. /* we have to config FPDRAM in burst mode with smaller burst access size */
  114. ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
  115. NETARM_MEM_OPT_BCYC_2 | \
  116. NETARM_MEM_OPT_BSIZE_16 | \
  117. NETARM_MEM_OPT_WAIT_STATES(0) | \
  118. NETARM_MEM_OPT_32BIT | \
  119. NETARM_MEM_OPT_READ_ASYNC | \
  120. NETARM_MEM_OPT_WRITE_ASYNC )
  121. str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
  122. ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
  123. NETARM_MEM_BAR_DRAM_SYNC | \
  124. NETARM_MEM_BAR_DRAM_MUX_INT | \
  125. NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
  126. NETARM_MEM_BAR_DRAM_SEL | \
  127. NETARM_MEM_BAR_BURST_EN | \
  128. NETARM_MEM_BAR_VALID )
  129. str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
  130. #endif /* CONFIG_NETARM_NET40_REV2 */
  131. memsetup_cs3:
  132. /*
  133. * Base Addr / Option Reg 3 (EEPROM, NVRAM)
  134. * ---------------------------------------------------
  135. */
  136. #if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
  137. ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
  138. NETARM_MEM_OPT_BCYC_3 | \
  139. NETARM_MEM_OPT_BSIZE_2 | \
  140. NETARM_MEM_OPT_WAIT_STATES(10) | \
  141. NETARM_MEM_OPT_8BIT | \
  142. NETARM_MEM_OPT_READ_ASYNC | \
  143. NETARM_MEM_OPT_WRITE_ASYNC )
  144. str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
  145. ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
  146. NETARM_MEM_BAR_DRAM_FP | \
  147. NETARM_MEM_BAR_DRAM_MUX_INT | \
  148. NETARM_MEM_BAR_DRAM_MUX_BAL | \
  149. NETARM_MEM_BAR_VALID )
  150. str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
  151. #else
  152. /* we don't need EEPROM --> no config */
  153. ldr r1, =( 0 )
  154. str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
  155. ldr r1, =( 0 )
  156. str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
  157. #endif
  158. #else
  159. /*
  160. #error "missing CONFIG_MODNET50 (see your config.h)"
  161. */
  162. #endif /* CONFIG_MODNET50 */
  163. memsetup_end:
  164. /*
  165. * manipulate address in lr and ip to match new
  166. * address space
  167. */
  168. ldr r3, =(NETARM_MMAP_CS0_BASE)
  169. mov r0, lr
  170. add r0, r3, r0
  171. mov lr, r0
  172. mov r0, ip
  173. add r0, r3, r0
  174. mov ip, r0
  175. /* everything is fine now */
  176. mov pc, lr