clk-uclass.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dt-structs.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/devres.h>
  18. #include <dm/read.h>
  19. #include <linux/bug.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/err.h>
  22. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  23. {
  24. return (const struct clk_ops *)dev->driver->ops;
  25. }
  26. struct clk *dev_get_clk_ptr(struct udevice *dev)
  27. {
  28. return (struct clk *)dev_get_uclass_priv(dev);
  29. }
  30. #if CONFIG_IS_ENABLED(OF_CONTROL)
  31. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  32. int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
  33. struct clk *clk)
  34. {
  35. int ret;
  36. ret = device_get_by_driver_info_idx(cells->idx, &clk->dev);
  37. if (ret)
  38. return ret;
  39. clk->id = cells->arg[0];
  40. return 0;
  41. }
  42. # else
  43. static int clk_of_xlate_default(struct clk *clk,
  44. struct ofnode_phandle_args *args)
  45. {
  46. debug("%s(clk=%p)\n", __func__, clk);
  47. if (args->args_count > 1) {
  48. debug("Invaild args_count: %d\n", args->args_count);
  49. return -EINVAL;
  50. }
  51. if (args->args_count)
  52. clk->id = args->args[0];
  53. else
  54. clk->id = 0;
  55. clk->data = 0;
  56. return 0;
  57. }
  58. static int clk_get_by_index_tail(int ret, ofnode node,
  59. struct ofnode_phandle_args *args,
  60. const char *list_name, int index,
  61. struct clk *clk)
  62. {
  63. struct udevice *dev_clk;
  64. const struct clk_ops *ops;
  65. assert(clk);
  66. clk->dev = NULL;
  67. if (ret)
  68. goto err;
  69. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  70. if (ret) {
  71. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  72. __func__, ret);
  73. return ret;
  74. }
  75. clk->dev = dev_clk;
  76. ops = clk_dev_ops(dev_clk);
  77. if (ops->of_xlate)
  78. ret = ops->of_xlate(clk, args);
  79. else
  80. ret = clk_of_xlate_default(clk, args);
  81. if (ret) {
  82. debug("of_xlate() failed: %d\n", ret);
  83. return ret;
  84. }
  85. return clk_request(dev_clk, clk);
  86. err:
  87. debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  88. __func__, ofnode_get_name(node), list_name, index, ret);
  89. return ret;
  90. }
  91. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  92. int index, struct clk *clk)
  93. {
  94. int ret;
  95. struct ofnode_phandle_args args;
  96. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  97. assert(clk);
  98. clk->dev = NULL;
  99. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  100. index, &args);
  101. if (ret) {
  102. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  103. __func__, ret);
  104. return ret;
  105. }
  106. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  107. index, clk);
  108. }
  109. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  110. {
  111. struct ofnode_phandle_args args;
  112. int ret;
  113. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  114. index, &args);
  115. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  116. index, clk);
  117. }
  118. int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
  119. {
  120. struct ofnode_phandle_args args;
  121. int ret;
  122. ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
  123. index, &args);
  124. return clk_get_by_index_tail(ret, node, &args, "clocks",
  125. index, clk);
  126. }
  127. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  128. {
  129. int i, ret, err, count;
  130. bulk->count = 0;
  131. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0);
  132. if (count < 1)
  133. return count;
  134. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  135. if (!bulk->clks)
  136. return -ENOMEM;
  137. for (i = 0; i < count; i++) {
  138. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  139. if (ret < 0)
  140. goto bulk_get_err;
  141. ++bulk->count;
  142. }
  143. return 0;
  144. bulk_get_err:
  145. err = clk_release_all(bulk->clks, bulk->count);
  146. if (err)
  147. debug("%s: could release all clocks for %p\n",
  148. __func__, dev);
  149. return ret;
  150. }
  151. static struct clk *clk_set_default_get_by_id(struct clk *clk)
  152. {
  153. struct clk *c = clk;
  154. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  155. int ret = clk_get_by_id(clk->id, &c);
  156. if (ret) {
  157. debug("%s(): could not get parent clock pointer, id %lu\n",
  158. __func__, clk->id);
  159. ERR_PTR(ret);
  160. }
  161. }
  162. return c;
  163. }
  164. static int clk_set_default_parents(struct udevice *dev, int stage)
  165. {
  166. struct clk clk, parent_clk, *c, *p;
  167. int index;
  168. int num_parents;
  169. int ret;
  170. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  171. "#clock-cells", 0);
  172. if (num_parents < 0) {
  173. debug("%s: could not read assigned-clock-parents for %p\n",
  174. __func__, dev);
  175. return 0;
  176. }
  177. for (index = 0; index < num_parents; index++) {
  178. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  179. index, &parent_clk);
  180. /* If -ENOENT, this is a no-op entry */
  181. if (ret == -ENOENT)
  182. continue;
  183. if (ret) {
  184. debug("%s: could not get parent clock %d for %s\n",
  185. __func__, index, dev_read_name(dev));
  186. return ret;
  187. }
  188. p = clk_set_default_get_by_id(&parent_clk);
  189. if (IS_ERR(p))
  190. return PTR_ERR(p);
  191. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  192. index, &clk);
  193. if (ret) {
  194. debug("%s: could not get assigned clock %d for %s\n",
  195. __func__, index, dev_read_name(dev));
  196. return ret;
  197. }
  198. /* This is clk provider device trying to reparent itself
  199. * It cannot be done right now but need to wait after the
  200. * device is probed
  201. */
  202. if (stage == 0 && clk.dev == dev)
  203. continue;
  204. if (stage > 0 && clk.dev != dev)
  205. /* do not setup twice the parent clocks */
  206. continue;
  207. c = clk_set_default_get_by_id(&clk);
  208. if (IS_ERR(c))
  209. return PTR_ERR(c);
  210. ret = clk_set_parent(c, p);
  211. /*
  212. * Not all drivers may support clock-reparenting (as of now).
  213. * Ignore errors due to this.
  214. */
  215. if (ret == -ENOSYS)
  216. continue;
  217. if (ret < 0) {
  218. debug("%s: failed to reparent clock %d for %s\n",
  219. __func__, index, dev_read_name(dev));
  220. return ret;
  221. }
  222. }
  223. return 0;
  224. }
  225. static int clk_set_default_rates(struct udevice *dev, int stage)
  226. {
  227. struct clk clk, *c;
  228. int index;
  229. int num_rates;
  230. int size;
  231. int ret = 0;
  232. u32 *rates = NULL;
  233. size = dev_read_size(dev, "assigned-clock-rates");
  234. if (size < 0)
  235. return 0;
  236. num_rates = size / sizeof(u32);
  237. rates = calloc(num_rates, sizeof(u32));
  238. if (!rates)
  239. return -ENOMEM;
  240. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  241. if (ret)
  242. goto fail;
  243. for (index = 0; index < num_rates; index++) {
  244. /* If 0 is passed, this is a no-op */
  245. if (!rates[index])
  246. continue;
  247. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  248. index, &clk);
  249. if (ret) {
  250. debug("%s: could not get assigned clock %d for %s\n",
  251. __func__, index, dev_read_name(dev));
  252. continue;
  253. }
  254. /* This is clk provider device trying to program itself
  255. * It cannot be done right now but need to wait after the
  256. * device is probed
  257. */
  258. if (stage == 0 && clk.dev == dev)
  259. continue;
  260. if (stage > 0 && clk.dev != dev)
  261. /* do not setup twice the parent clocks */
  262. continue;
  263. c = clk_set_default_get_by_id(&clk);
  264. if (IS_ERR(c))
  265. return PTR_ERR(c);
  266. ret = clk_set_rate(c, rates[index]);
  267. if (ret < 0) {
  268. debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
  269. __func__, index, clk.id, dev_read_name(dev));
  270. break;
  271. }
  272. }
  273. fail:
  274. free(rates);
  275. return ret;
  276. }
  277. int clk_set_defaults(struct udevice *dev, int stage)
  278. {
  279. int ret;
  280. if (!dev_has_ofnode(dev))
  281. return 0;
  282. /* If this not in SPL and pre-reloc state, don't take any action. */
  283. if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
  284. return 0;
  285. debug("%s(%s)\n", __func__, dev_read_name(dev));
  286. ret = clk_set_default_parents(dev, stage);
  287. if (ret)
  288. return ret;
  289. ret = clk_set_default_rates(dev, stage);
  290. if (ret < 0)
  291. return ret;
  292. return 0;
  293. }
  294. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  295. {
  296. int index;
  297. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  298. clk->dev = NULL;
  299. index = dev_read_stringlist_search(dev, "clock-names", name);
  300. if (index < 0) {
  301. debug("fdt_stringlist_search() failed: %d\n", index);
  302. return index;
  303. }
  304. return clk_get_by_index(dev, index, clk);
  305. }
  306. # endif /* OF_PLATDATA */
  307. int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
  308. {
  309. int index;
  310. debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
  311. ofnode_get_name(node), name, clk);
  312. clk->dev = NULL;
  313. index = ofnode_stringlist_search(node, "clock-names", name);
  314. if (index < 0) {
  315. debug("fdt_stringlist_search() failed: %d\n", index);
  316. return index;
  317. }
  318. return clk_get_by_index_nodev(node, index, clk);
  319. }
  320. int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
  321. {
  322. int ret;
  323. ret = clk_get_by_name_nodev(node, name, clk);
  324. if (ret == -ENODATA)
  325. return 0;
  326. return ret;
  327. }
  328. int clk_release_all(struct clk *clk, int count)
  329. {
  330. int i, ret;
  331. for (i = 0; i < count; i++) {
  332. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  333. /* check if clock has been previously requested */
  334. if (!clk[i].dev)
  335. continue;
  336. ret = clk_disable(&clk[i]);
  337. if (ret && ret != -ENOSYS)
  338. return ret;
  339. ret = clk_free(&clk[i]);
  340. if (ret && ret != -ENOSYS)
  341. return ret;
  342. }
  343. return 0;
  344. }
  345. #endif /* OF_CONTROL */
  346. int clk_request(struct udevice *dev, struct clk *clk)
  347. {
  348. const struct clk_ops *ops;
  349. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  350. if (!clk)
  351. return 0;
  352. ops = clk_dev_ops(dev);
  353. clk->dev = dev;
  354. if (!ops->request)
  355. return 0;
  356. return ops->request(clk);
  357. }
  358. int clk_free(struct clk *clk)
  359. {
  360. const struct clk_ops *ops;
  361. debug("%s(clk=%p)\n", __func__, clk);
  362. if (!clk_valid(clk))
  363. return 0;
  364. ops = clk_dev_ops(clk->dev);
  365. if (!ops->rfree)
  366. return 0;
  367. return ops->rfree(clk);
  368. }
  369. ulong clk_get_rate(struct clk *clk)
  370. {
  371. const struct clk_ops *ops;
  372. debug("%s(clk=%p)\n", __func__, clk);
  373. if (!clk_valid(clk))
  374. return 0;
  375. ops = clk_dev_ops(clk->dev);
  376. if (!ops->get_rate)
  377. return -ENOSYS;
  378. return ops->get_rate(clk);
  379. }
  380. struct clk *clk_get_parent(struct clk *clk)
  381. {
  382. struct udevice *pdev;
  383. struct clk *pclk;
  384. debug("%s(clk=%p)\n", __func__, clk);
  385. if (!clk_valid(clk))
  386. return NULL;
  387. pdev = dev_get_parent(clk->dev);
  388. pclk = dev_get_clk_ptr(pdev);
  389. if (!pclk)
  390. return ERR_PTR(-ENODEV);
  391. return pclk;
  392. }
  393. long long clk_get_parent_rate(struct clk *clk)
  394. {
  395. const struct clk_ops *ops;
  396. struct clk *pclk;
  397. debug("%s(clk=%p)\n", __func__, clk);
  398. if (!clk_valid(clk))
  399. return 0;
  400. pclk = clk_get_parent(clk);
  401. if (IS_ERR(pclk))
  402. return -ENODEV;
  403. ops = clk_dev_ops(pclk->dev);
  404. if (!ops->get_rate)
  405. return -ENOSYS;
  406. /* Read the 'rate' if not already set or if proper flag set*/
  407. if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
  408. pclk->rate = clk_get_rate(pclk);
  409. return pclk->rate;
  410. }
  411. ulong clk_round_rate(struct clk *clk, ulong rate)
  412. {
  413. const struct clk_ops *ops;
  414. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  415. if (!clk_valid(clk))
  416. return 0;
  417. ops = clk_dev_ops(clk->dev);
  418. if (!ops->round_rate)
  419. return -ENOSYS;
  420. return ops->round_rate(clk, rate);
  421. }
  422. ulong clk_set_rate(struct clk *clk, ulong rate)
  423. {
  424. const struct clk_ops *ops;
  425. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  426. if (!clk_valid(clk))
  427. return 0;
  428. ops = clk_dev_ops(clk->dev);
  429. if (!ops->set_rate)
  430. return -ENOSYS;
  431. return ops->set_rate(clk, rate);
  432. }
  433. int clk_set_parent(struct clk *clk, struct clk *parent)
  434. {
  435. const struct clk_ops *ops;
  436. int ret;
  437. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  438. if (!clk_valid(clk))
  439. return 0;
  440. ops = clk_dev_ops(clk->dev);
  441. if (!ops->set_parent)
  442. return -ENOSYS;
  443. ret = ops->set_parent(clk, parent);
  444. if (ret)
  445. return ret;
  446. if (CONFIG_IS_ENABLED(CLK_CCF))
  447. ret = device_reparent(clk->dev, parent->dev);
  448. return ret;
  449. }
  450. int clk_enable(struct clk *clk)
  451. {
  452. const struct clk_ops *ops;
  453. struct clk *clkp = NULL;
  454. int ret;
  455. debug("%s(clk=%p)\n", __func__, clk);
  456. if (!clk_valid(clk))
  457. return 0;
  458. ops = clk_dev_ops(clk->dev);
  459. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  460. /* Take id 0 as a non-valid clk, such as dummy */
  461. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  462. if (clkp->enable_count) {
  463. clkp->enable_count++;
  464. return 0;
  465. }
  466. if (clkp->dev->parent &&
  467. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  468. ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
  469. if (ret) {
  470. printf("Enable %s failed\n",
  471. clkp->dev->parent->name);
  472. return ret;
  473. }
  474. }
  475. }
  476. if (ops->enable) {
  477. ret = ops->enable(clk);
  478. if (ret) {
  479. printf("Enable %s failed\n", clk->dev->name);
  480. return ret;
  481. }
  482. }
  483. if (clkp)
  484. clkp->enable_count++;
  485. } else {
  486. if (!ops->enable)
  487. return -ENOSYS;
  488. return ops->enable(clk);
  489. }
  490. return 0;
  491. }
  492. int clk_enable_bulk(struct clk_bulk *bulk)
  493. {
  494. int i, ret;
  495. for (i = 0; i < bulk->count; i++) {
  496. ret = clk_enable(&bulk->clks[i]);
  497. if (ret < 0 && ret != -ENOSYS)
  498. return ret;
  499. }
  500. return 0;
  501. }
  502. int clk_disable(struct clk *clk)
  503. {
  504. const struct clk_ops *ops;
  505. struct clk *clkp = NULL;
  506. int ret;
  507. debug("%s(clk=%p)\n", __func__, clk);
  508. if (!clk_valid(clk))
  509. return 0;
  510. ops = clk_dev_ops(clk->dev);
  511. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  512. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  513. if (clkp->flags & CLK_IS_CRITICAL)
  514. return 0;
  515. if (clkp->enable_count == 0) {
  516. printf("clk %s already disabled\n",
  517. clkp->dev->name);
  518. return 0;
  519. }
  520. if (--clkp->enable_count > 0)
  521. return 0;
  522. }
  523. if (ops->disable) {
  524. ret = ops->disable(clk);
  525. if (ret)
  526. return ret;
  527. }
  528. if (clkp && clkp->dev->parent &&
  529. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  530. ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
  531. if (ret) {
  532. printf("Disable %s failed\n",
  533. clkp->dev->parent->name);
  534. return ret;
  535. }
  536. }
  537. } else {
  538. if (!ops->disable)
  539. return -ENOSYS;
  540. return ops->disable(clk);
  541. }
  542. return 0;
  543. }
  544. int clk_disable_bulk(struct clk_bulk *bulk)
  545. {
  546. int i, ret;
  547. for (i = 0; i < bulk->count; i++) {
  548. ret = clk_disable(&bulk->clks[i]);
  549. if (ret < 0 && ret != -ENOSYS)
  550. return ret;
  551. }
  552. return 0;
  553. }
  554. int clk_get_by_id(ulong id, struct clk **clkp)
  555. {
  556. struct udevice *dev;
  557. struct uclass *uc;
  558. int ret;
  559. ret = uclass_get(UCLASS_CLK, &uc);
  560. if (ret)
  561. return ret;
  562. uclass_foreach_dev(dev, uc) {
  563. struct clk *clk = dev_get_clk_ptr(dev);
  564. if (clk && clk->id == id) {
  565. *clkp = clk;
  566. return 0;
  567. }
  568. }
  569. return -ENOENT;
  570. }
  571. bool clk_is_match(const struct clk *p, const struct clk *q)
  572. {
  573. /* trivial case: identical struct clk's or both NULL */
  574. if (p == q)
  575. return true;
  576. /* trivial case #2: on the clk pointer is NULL */
  577. if (!p || !q)
  578. return false;
  579. /* same device, id and data */
  580. if (p->dev == q->dev && p->id == q->id && p->data == q->data)
  581. return true;
  582. return false;
  583. }
  584. static void devm_clk_release(struct udevice *dev, void *res)
  585. {
  586. clk_free(res);
  587. }
  588. static int devm_clk_match(struct udevice *dev, void *res, void *data)
  589. {
  590. return res == data;
  591. }
  592. struct clk *devm_clk_get(struct udevice *dev, const char *id)
  593. {
  594. int rc;
  595. struct clk *clk;
  596. clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
  597. if (unlikely(!clk))
  598. return ERR_PTR(-ENOMEM);
  599. rc = clk_get_by_name(dev, id, clk);
  600. if (rc)
  601. return ERR_PTR(rc);
  602. devres_add(dev, clk);
  603. return clk;
  604. }
  605. struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
  606. {
  607. struct clk *clk = devm_clk_get(dev, id);
  608. if (PTR_ERR(clk) == -ENODATA)
  609. return NULL;
  610. return clk;
  611. }
  612. void devm_clk_put(struct udevice *dev, struct clk *clk)
  613. {
  614. int rc;
  615. if (!clk)
  616. return;
  617. rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
  618. WARN_ON(rc);
  619. }
  620. int clk_uclass_post_probe(struct udevice *dev)
  621. {
  622. /*
  623. * when a clock provider is probed. Call clk_set_defaults()
  624. * also after the device is probed. This takes care of cases
  625. * where the DT is used to setup default parents and rates
  626. * using assigned-clocks
  627. */
  628. clk_set_defaults(dev, 1);
  629. return 0;
  630. }
  631. UCLASS_DRIVER(clk) = {
  632. .id = UCLASS_CLK,
  633. .name = "clk",
  634. .post_probe = clk_uclass_post_probe,
  635. };