fec_mxc.c 18 KB

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  1. /*
  2. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  3. * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  4. * (C) Copyright 2008 Armadeus Systems nc
  5. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <malloc.h>
  25. #include <net.h>
  26. #include <miiphy.h>
  27. #include "fec_mxc.h"
  28. #include <asm/arch/clock.h>
  29. #include <asm/arch/imx-regs.h>
  30. #include <asm/io.h>
  31. #include <asm/errno.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #ifndef CONFIG_MII
  34. #error "CONFIG_MII has to be defined!"
  35. #endif
  36. #undef DEBUG
  37. struct nbuf {
  38. uint8_t data[1500]; /**< actual data */
  39. int length; /**< actual length */
  40. int used; /**< buffer in use or not */
  41. uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
  42. };
  43. struct fec_priv gfec = {
  44. .eth = (struct ethernet_regs *)IMX_FEC_BASE,
  45. .xcv_type = MII100,
  46. .rbd_base = NULL,
  47. .rbd_index = 0,
  48. .tbd_base = NULL,
  49. .tbd_index = 0,
  50. .bd = NULL,
  51. };
  52. /*
  53. * MII-interface related functions
  54. */
  55. static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
  56. uint16_t *retVal)
  57. {
  58. struct eth_device *edev = eth_get_dev_by_name(dev);
  59. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  60. uint32_t reg; /* convenient holder for the PHY register */
  61. uint32_t phy; /* convenient holder for the PHY */
  62. uint32_t start;
  63. /*
  64. * reading from any PHY's register is done by properly
  65. * programming the FEC's MII data register.
  66. */
  67. writel(FEC_IEVENT_MII, &fec->eth->ievent);
  68. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  69. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  70. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
  71. phy | reg, &fec->eth->mii_data);
  72. /*
  73. * wait for the related interrupt
  74. */
  75. start = get_timer_masked();
  76. while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
  77. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  78. printf("Read MDIO failed...\n");
  79. return -1;
  80. }
  81. }
  82. /*
  83. * clear mii interrupt bit
  84. */
  85. writel(FEC_IEVENT_MII, &fec->eth->ievent);
  86. /*
  87. * it's now safe to read the PHY's register
  88. */
  89. *retVal = readl(&fec->eth->mii_data);
  90. debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
  91. regAddr, *retVal);
  92. return 0;
  93. }
  94. static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
  95. uint16_t data)
  96. {
  97. struct eth_device *edev = eth_get_dev_by_name(dev);
  98. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  99. uint32_t reg; /* convenient holder for the PHY register */
  100. uint32_t phy; /* convenient holder for the PHY */
  101. uint32_t start;
  102. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  103. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  104. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  105. FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
  106. /*
  107. * wait for the MII interrupt
  108. */
  109. start = get_timer_masked();
  110. while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
  111. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  112. printf("Write MDIO failed...\n");
  113. return -1;
  114. }
  115. }
  116. /*
  117. * clear MII interrupt bit
  118. */
  119. writel(FEC_IEVENT_MII, &fec->eth->ievent);
  120. debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
  121. regAddr, data);
  122. return 0;
  123. }
  124. static int miiphy_restart_aneg(struct eth_device *dev)
  125. {
  126. /*
  127. * Wake up from sleep if necessary
  128. * Reset PHY, then delay 300ns
  129. */
  130. miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
  131. miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
  132. PHY_BMCR_RESET);
  133. udelay(1000);
  134. /*
  135. * Set the auto-negotiation advertisement register bits
  136. */
  137. miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
  138. miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
  139. PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  140. return 0;
  141. }
  142. static int miiphy_wait_aneg(struct eth_device *dev)
  143. {
  144. uint32_t start;
  145. uint16_t status;
  146. /*
  147. * Wait for AN completion
  148. */
  149. start = get_timer_masked();
  150. do {
  151. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  152. printf("%s: Autonegotiation timeout\n", dev->name);
  153. return -1;
  154. }
  155. if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
  156. PHY_BMSR, &status)) {
  157. printf("%s: Autonegotiation failed. status: 0x%04x\n",
  158. dev->name, status);
  159. return -1;
  160. }
  161. } while (!(status & PHY_BMSR_LS));
  162. return 0;
  163. }
  164. static int fec_rx_task_enable(struct fec_priv *fec)
  165. {
  166. writel(1 << 24, &fec->eth->r_des_active);
  167. return 0;
  168. }
  169. static int fec_rx_task_disable(struct fec_priv *fec)
  170. {
  171. return 0;
  172. }
  173. static int fec_tx_task_enable(struct fec_priv *fec)
  174. {
  175. writel(1 << 24, &fec->eth->x_des_active);
  176. return 0;
  177. }
  178. static int fec_tx_task_disable(struct fec_priv *fec)
  179. {
  180. return 0;
  181. }
  182. /**
  183. * Initialize receive task's buffer descriptors
  184. * @param[in] fec all we know about the device yet
  185. * @param[in] count receive buffer count to be allocated
  186. * @param[in] size size of each receive buffer
  187. * @return 0 on success
  188. *
  189. * For this task we need additional memory for the data buffers. And each
  190. * data buffer requires some alignment. Thy must be aligned to a specific
  191. * boundary each (DB_DATA_ALIGNMENT).
  192. */
  193. static int fec_rbd_init(struct fec_priv *fec, int count, int size)
  194. {
  195. int ix;
  196. uint32_t p = 0;
  197. /* reserve data memory and consider alignment */
  198. fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
  199. p = (uint32_t)fec->rdb_ptr;
  200. if (!p) {
  201. puts("fec_imx27: not enough malloc memory!\n");
  202. return -ENOMEM;
  203. }
  204. memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
  205. p += DB_DATA_ALIGNMENT-1;
  206. p &= ~(DB_DATA_ALIGNMENT-1);
  207. for (ix = 0; ix < count; ix++) {
  208. writel(p, &fec->rbd_base[ix].data_pointer);
  209. p += size;
  210. writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
  211. writew(0, &fec->rbd_base[ix].data_length);
  212. }
  213. /*
  214. * mark the last RBD to close the ring
  215. */
  216. writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
  217. fec->rbd_index = 0;
  218. return 0;
  219. }
  220. /**
  221. * Initialize transmit task's buffer descriptors
  222. * @param[in] fec all we know about the device yet
  223. *
  224. * Transmit buffers are created externally. We only have to init the BDs here.\n
  225. * Note: There is a race condition in the hardware. When only one BD is in
  226. * use it must be marked with the WRAP bit to use it for every transmitt.
  227. * This bit in combination with the READY bit results into double transmit
  228. * of each data buffer. It seems the state machine checks READY earlier then
  229. * resetting it after the first transfer.
  230. * Using two BDs solves this issue.
  231. */
  232. static void fec_tbd_init(struct fec_priv *fec)
  233. {
  234. writew(0x0000, &fec->tbd_base[0].status);
  235. writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
  236. fec->tbd_index = 0;
  237. }
  238. /**
  239. * Mark the given read buffer descriptor as free
  240. * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  241. * @param[in] pRbd buffer descriptor to mark free again
  242. */
  243. static void fec_rbd_clean(int last, struct fec_bd *pRbd)
  244. {
  245. /*
  246. * Reset buffer descriptor as empty
  247. */
  248. if (last)
  249. writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
  250. else
  251. writew(FEC_RBD_EMPTY, &pRbd->status);
  252. /*
  253. * no data in it
  254. */
  255. writew(0, &pRbd->data_length);
  256. }
  257. static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
  258. {
  259. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  260. int i;
  261. for (i = 0; i < 6; i++)
  262. mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
  263. return is_valid_ether_addr(mac);
  264. }
  265. static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
  266. {
  267. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  268. writel(0, &fec->eth->iaddr1);
  269. writel(0, &fec->eth->iaddr2);
  270. writel(0, &fec->eth->gaddr1);
  271. writel(0, &fec->eth->gaddr2);
  272. /*
  273. * Set physical address
  274. */
  275. writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
  276. &fec->eth->paddr1);
  277. writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
  278. return 0;
  279. }
  280. /**
  281. * Start the FEC engine
  282. * @param[in] dev Our device to handle
  283. */
  284. static int fec_open(struct eth_device *edev)
  285. {
  286. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  287. debug("fec_open: fec_open(dev)\n");
  288. /* full-duplex, heartbeat disabled */
  289. writel(1 << 2, &fec->eth->x_cntrl);
  290. fec->rbd_index = 0;
  291. /*
  292. * Enable FEC-Lite controller
  293. */
  294. writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
  295. miiphy_wait_aneg(edev);
  296. miiphy_speed(edev->name, 0);
  297. miiphy_duplex(edev->name, 0);
  298. /*
  299. * Enable SmartDMA receive task
  300. */
  301. fec_rx_task_enable(fec);
  302. udelay(100000);
  303. return 0;
  304. }
  305. static int fec_init(struct eth_device *dev, bd_t* bd)
  306. {
  307. uint32_t base;
  308. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  309. /*
  310. * reserve memory for both buffer descriptor chains at once
  311. * Datasheet forces the startaddress of each chain is 16 byte
  312. * aligned
  313. */
  314. fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
  315. sizeof(struct fec_bd) + DB_ALIGNMENT);
  316. base = (uint32_t)fec->base_ptr;
  317. if (!base) {
  318. puts("fec_imx27: not enough malloc memory!\n");
  319. return -ENOMEM;
  320. }
  321. memset((void *)base, 0, (2 + FEC_RBD_NUM) *
  322. sizeof(struct fec_bd) + DB_ALIGNMENT);
  323. base += (DB_ALIGNMENT-1);
  324. base &= ~(DB_ALIGNMENT-1);
  325. fec->rbd_base = (struct fec_bd *)base;
  326. base += FEC_RBD_NUM * sizeof(struct fec_bd);
  327. fec->tbd_base = (struct fec_bd *)base;
  328. /*
  329. * Set interrupt mask register
  330. */
  331. writel(0x00000000, &fec->eth->imask);
  332. /*
  333. * Clear FEC-Lite interrupt event register(IEVENT)
  334. */
  335. writel(0xffffffff, &fec->eth->ievent);
  336. /*
  337. * Set FEC-Lite receive control register(R_CNTRL):
  338. */
  339. if (fec->xcv_type == SEVENWIRE) {
  340. /*
  341. * Frame length=1518; 7-wire mode
  342. */
  343. writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
  344. } else {
  345. /*
  346. * Frame length=1518; MII mode;
  347. */
  348. writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
  349. /*
  350. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  351. * and do not drop the Preamble.
  352. */
  353. writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
  354. &fec->eth->mii_speed);
  355. debug("fec_init: mii_speed %#lx\n",
  356. (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
  357. }
  358. /*
  359. * Set Opcode/Pause Duration Register
  360. */
  361. writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
  362. writel(0x2, &fec->eth->x_wmrk);
  363. /*
  364. * Set multicast address filter
  365. */
  366. writel(0x00000000, &fec->eth->gaddr1);
  367. writel(0x00000000, &fec->eth->gaddr2);
  368. /* clear MIB RAM */
  369. long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
  370. while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
  371. *mib_ptr++ = 0;
  372. /* FIFO receive start register */
  373. writel(0x520, &fec->eth->r_fstart);
  374. /* size and address of each buffer */
  375. writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
  376. writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
  377. writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
  378. /*
  379. * Initialize RxBD/TxBD rings
  380. */
  381. if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
  382. free(fec->base_ptr);
  383. return -ENOMEM;
  384. }
  385. fec_tbd_init(fec);
  386. if (fec->xcv_type != SEVENWIRE)
  387. miiphy_restart_aneg(dev);
  388. fec_open(dev);
  389. return 0;
  390. }
  391. /**
  392. * Halt the FEC engine
  393. * @param[in] dev Our device to handle
  394. */
  395. static void fec_halt(struct eth_device *dev)
  396. {
  397. struct fec_priv *fec = &gfec;
  398. int counter = 0xffff;
  399. /*
  400. * issue graceful stop command to the FEC transmitter if necessary
  401. */
  402. writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
  403. &fec->eth->x_cntrl);
  404. debug("eth_halt: wait for stop regs\n");
  405. /*
  406. * wait for graceful stop to register
  407. */
  408. while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
  409. ; /* FIXME ensure time */
  410. /*
  411. * Disable SmartDMA tasks
  412. */
  413. fec_tx_task_disable(fec);
  414. fec_rx_task_disable(fec);
  415. /*
  416. * Disable the Ethernet Controller
  417. * Note: this will also reset the BD index counter!
  418. */
  419. writel(0, &fec->eth->ecntrl);
  420. fec->rbd_index = 0;
  421. fec->tbd_index = 0;
  422. free(fec->rdb_ptr);
  423. free(fec->base_ptr);
  424. debug("eth_halt: done\n");
  425. }
  426. /**
  427. * Transmit one frame
  428. * @param[in] dev Our ethernet device to handle
  429. * @param[in] packet Pointer to the data to be transmitted
  430. * @param[in] length Data count in bytes
  431. * @return 0 on success
  432. */
  433. static int fec_send(struct eth_device *dev, volatile void* packet, int length)
  434. {
  435. unsigned int status;
  436. /*
  437. * This routine transmits one frame. This routine only accepts
  438. * 6-byte Ethernet addresses.
  439. */
  440. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  441. /*
  442. * Check for valid length of data.
  443. */
  444. if ((length > 1500) || (length <= 0)) {
  445. printf("Payload (%d) to large!\n", length);
  446. return -1;
  447. }
  448. /*
  449. * Setup the transmit buffer
  450. * Note: We are always using the first buffer for transmission,
  451. * the second will be empty and only used to stop the DMA engine
  452. */
  453. writew(length, &fec->tbd_base[fec->tbd_index].data_length);
  454. writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
  455. /*
  456. * update BD's status now
  457. * This block:
  458. * - is always the last in a chain (means no chain)
  459. * - should transmitt the CRC
  460. * - might be the last BD in the list, so the address counter should
  461. * wrap (-> keep the WRAP flag)
  462. */
  463. status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
  464. status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  465. writew(status, &fec->tbd_base[fec->tbd_index].status);
  466. /*
  467. * Enable SmartDMA transmit task
  468. */
  469. fec_tx_task_enable(fec);
  470. /*
  471. * wait until frame is sent .
  472. */
  473. while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
  474. /* FIXME: Timeout */
  475. }
  476. debug("fec_send: status 0x%x index %d\n",
  477. readw(&fec->tbd_base[fec->tbd_index].status),
  478. fec->tbd_index);
  479. /* for next transmission use the other buffer */
  480. if (fec->tbd_index)
  481. fec->tbd_index = 0;
  482. else
  483. fec->tbd_index = 1;
  484. return 0;
  485. }
  486. /**
  487. * Pull one frame from the card
  488. * @param[in] dev Our ethernet device to handle
  489. * @return Length of packet read
  490. */
  491. static int fec_recv(struct eth_device *dev)
  492. {
  493. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  494. struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
  495. unsigned long ievent;
  496. int frame_length, len = 0;
  497. struct nbuf *frame;
  498. uint16_t bd_status;
  499. uchar buff[FEC_MAX_PKT_SIZE];
  500. /*
  501. * Check if any critical events have happened
  502. */
  503. ievent = readl(&fec->eth->ievent);
  504. writel(ievent, &fec->eth->ievent);
  505. debug("fec_recv: ievent 0x%x\n", ievent);
  506. if (ievent & FEC_IEVENT_BABR) {
  507. fec_halt(dev);
  508. fec_init(dev, fec->bd);
  509. printf("some error: 0x%08lx\n", ievent);
  510. return 0;
  511. }
  512. if (ievent & FEC_IEVENT_HBERR) {
  513. /* Heartbeat error */
  514. writel(0x00000001 | readl(&fec->eth->x_cntrl),
  515. &fec->eth->x_cntrl);
  516. }
  517. if (ievent & FEC_IEVENT_GRA) {
  518. /* Graceful stop complete */
  519. if (readl(&fec->eth->x_cntrl) & 0x00000001) {
  520. fec_halt(dev);
  521. writel(~0x00000001 & readl(&fec->eth->x_cntrl),
  522. &fec->eth->x_cntrl);
  523. fec_init(dev, fec->bd);
  524. }
  525. }
  526. /*
  527. * ensure reading the right buffer status
  528. */
  529. bd_status = readw(&rbd->status);
  530. debug("fec_recv: status 0x%x\n", bd_status);
  531. if (!(bd_status & FEC_RBD_EMPTY)) {
  532. if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
  533. ((readw(&rbd->data_length) - 4) > 14)) {
  534. /*
  535. * Get buffer address and size
  536. */
  537. frame = (struct nbuf *)readl(&rbd->data_pointer);
  538. frame_length = readw(&rbd->data_length) - 4;
  539. /*
  540. * Fill the buffer and pass it to upper layers
  541. */
  542. memcpy(buff, frame->data, frame_length);
  543. NetReceive(buff, frame_length);
  544. len = frame_length;
  545. } else {
  546. if (bd_status & FEC_RBD_ERR)
  547. printf("error frame: 0x%08lx 0x%08x\n",
  548. (ulong)rbd->data_pointer,
  549. bd_status);
  550. }
  551. /*
  552. * free the current buffer, restart the engine
  553. * and move forward to the next buffer
  554. */
  555. fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
  556. fec_rx_task_enable(fec);
  557. fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
  558. }
  559. debug("fec_recv: stop\n");
  560. return len;
  561. }
  562. static int fec_probe(bd_t *bd)
  563. {
  564. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  565. struct eth_device *edev;
  566. struct fec_priv *fec = &gfec;
  567. unsigned char ethaddr_str[20];
  568. unsigned char ethaddr[6];
  569. char *tmp = getenv("ethaddr");
  570. char *end;
  571. /* enable FEC clock */
  572. writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
  573. writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
  574. /* create and fill edev struct */
  575. edev = (struct eth_device *)malloc(sizeof(struct eth_device));
  576. if (!edev) {
  577. puts("fec_imx27: not enough malloc memory!\n");
  578. return -ENOMEM;
  579. }
  580. edev->priv = fec;
  581. edev->init = fec_init;
  582. edev->send = fec_send;
  583. edev->recv = fec_recv;
  584. edev->halt = fec_halt;
  585. fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
  586. fec->bd = bd;
  587. fec->xcv_type = MII100;
  588. /* Reset chip. */
  589. writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
  590. while (readl(&fec->eth->ecntrl) & 1)
  591. udelay(10);
  592. /*
  593. * Set interrupt mask register
  594. */
  595. writel(0x00000000, &fec->eth->imask);
  596. /*
  597. * Clear FEC-Lite interrupt event register(IEVENT)
  598. */
  599. writel(0xffffffff, &fec->eth->ievent);
  600. /*
  601. * Set FEC-Lite receive control register(R_CNTRL):
  602. */
  603. /*
  604. * Frame length=1518; MII mode;
  605. */
  606. writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
  607. /*
  608. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  609. * and do not drop the Preamble.
  610. */
  611. writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
  612. &fec->eth->mii_speed);
  613. debug("fec_init: mii_speed %#lx\n",
  614. (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
  615. sprintf(edev->name, "FEC_MXC");
  616. miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
  617. eth_register(edev);
  618. if ((NULL != tmp) && (12 <= strlen(tmp))) {
  619. int i;
  620. /* convert MAC from string to int */
  621. for (i = 0; i < 6; i++) {
  622. ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  623. if (tmp)
  624. tmp = (*end) ? end + 1 : end;
  625. }
  626. } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
  627. printf("got MAC address from EEPROM: %pM\n", ethaddr);
  628. setenv("ethaddr", (char *)ethaddr_str);
  629. }
  630. memcpy(edev->enetaddr, ethaddr, 6);
  631. fec_set_hwaddr(edev, ethaddr);
  632. return 0;
  633. }
  634. int fecmxc_initialize(bd_t *bd)
  635. {
  636. int lout = 1;
  637. debug("eth_init: fec_probe(bd)\n");
  638. lout = fec_probe(bd);
  639. return lout;
  640. }