pcm030.c 5.6 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * (C) Copyright 2006
  9. * Eric Schumann, Phytec Messtechnik GmbH
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <common.h>
  30. #include <mpc5xxx.h>
  31. #include <pci.h>
  32. #include <asm-ppc/io.h>
  33. #include "mt46v32m16-75.h"
  34. #ifndef CONFIG_SYS_RAMBOOT
  35. static void sdram_start(int hi_addr)
  36. {
  37. volatile struct mpc5xxx_cdm *cdm =
  38. (struct mpc5xxx_cdm *)MPC5XXX_CDM;
  39. volatile struct mpc5xxx_sdram *sdram =
  40. (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  41. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  42. /* unlock mode register */
  43. out_be32 (&sdram->ctrl,
  44. (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
  45. /* precharge all banks */
  46. out_be32 (&sdram->ctrl,
  47. (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  48. #ifdef SDRAM_DDR
  49. /* set mode register: extended mode */
  50. out_be32 (&sdram->mode, (SDRAM_EMODE));
  51. /* set mode register: reset DLL */
  52. out_be32 (&sdram->mode,
  53. (SDRAM_MODE | 0x04000000));
  54. #endif
  55. /* precharge all banks */
  56. out_be32 (&sdram->ctrl,
  57. (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  58. /* auto refresh */
  59. out_be32 (&sdram->ctrl,
  60. (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
  61. /* set mode register */
  62. out_be32 (&sdram->mode, (SDRAM_MODE));
  63. /* normal operation */
  64. out_be32 (&sdram->ctrl,
  65. (SDRAM_CONTROL | hi_addr_bit));
  66. /* set CDM clock enable register, set MPC5200B SDRAM bus */
  67. /* to reduced driver strength */
  68. out_be32 (&cdm->clock_enable, (0x00CFFFFF));
  69. }
  70. #endif
  71. /*
  72. * ATTENTION: Although partially referenced initdram does NOT make
  73. * real use of CONFIG_SYS_SDRAM_BASE. The code does not
  74. * work if CONFIG_SYS_SDRAM_BASE
  75. * is something else than 0x00000000.
  76. */
  77. phys_size_t initdram(int board_type)
  78. {
  79. volatile struct mpc5xxx_mmap_ctl *mm =
  80. (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  81. volatile struct mpc5xxx_cdm *cdm =
  82. (struct mpc5xxx_cdm *)MPC5XXX_CDM;
  83. volatile struct mpc5xxx_sdram *sdram =
  84. (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  85. ulong dramsize = 0;
  86. ulong dramsize2 = 0;
  87. #ifndef CONFIG_SYS_RAMBOOT
  88. ulong test1, test2;
  89. /* setup SDRAM chip selects */
  90. /* 256MB at 0x0 */
  91. out_be32 (&mm->sdram0, 0x0000001b);
  92. /* disabled */
  93. out_be32 (&mm->sdram1, 0x10000000);
  94. /* setup config registers */
  95. out_be32 (&sdram->config1, SDRAM_CONFIG1);
  96. out_be32 (&sdram->config2, SDRAM_CONFIG2);
  97. #if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
  98. /* set tap delay */
  99. out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
  100. #endif
  101. /* find RAM size using SDRAM CS0 only */
  102. sdram_start(0);
  103. test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
  104. sdram_start(1);
  105. test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
  106. if (test1 > test2) {
  107. sdram_start(0);
  108. dramsize = test1;
  109. } else
  110. dramsize = test2;
  111. /* memory smaller than 1MB is impossible */
  112. if (dramsize < (1 << 20))
  113. dramsize = 0;
  114. /* set SDRAM CS0 size according to the amount of RAM found */
  115. if (dramsize > 0) {
  116. out_be32 (&mm->sdram0,
  117. (0x13 + __builtin_ffs(dramsize >> 20) - 1));
  118. } else {
  119. /* disabled */
  120. out_be32 (&mm->sdram0, 0);
  121. }
  122. #else /* CONFIG_SYS_RAMBOOT */
  123. /* retrieve size of memory connected to SDRAM CS0 */
  124. dramsize = in_be32(&mm->sdram0) & 0xFF;
  125. if (dramsize >= 0x13)
  126. dramsize = (1 << (dramsize - 0x13)) << 20;
  127. else
  128. dramsize = 0;
  129. /* retrieve size of memory connected to SDRAM CS1 */
  130. dramsize2 = in_be32(&mm->sdram1) & 0xFF;
  131. if (dramsize2 >= 0x13)
  132. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  133. else
  134. dramsize2 = 0;
  135. #endif /* CONFIG_SYS_RAMBOOT */
  136. return dramsize + dramsize2;
  137. }
  138. int checkboard(void)
  139. {
  140. puts("Board: phyCORE-MPC5200B-tiny\n");
  141. return 0;
  142. }
  143. #ifdef CONFIG_PCI
  144. static struct pci_controller hose;
  145. extern void pci_mpc5xxx_init(struct pci_controller *);
  146. void pci_init_board(void)
  147. {
  148. pci_mpc5xxx_init(&hose);
  149. }
  150. #endif
  151. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  152. void ft_board_setup(void *blob, bd_t * bd)
  153. {
  154. ft_cpu_setup(blob, bd);
  155. }
  156. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
  157. #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
  158. #define GPIO_PSC2_4 0x02000000UL
  159. void init_ide_reset(void)
  160. {
  161. volatile struct mpc5xxx_wu_gpio *wu_gpio =
  162. (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
  163. debug("init_ide_reset\n");
  164. /* Configure PSC2_4 as GPIO output for ATA reset */
  165. setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
  166. setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
  167. /* Deassert reset */
  168. setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
  169. }
  170. void ide_set_reset(int idereset)
  171. {
  172. volatile struct mpc5xxx_wu_gpio *wu_gpio =
  173. (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
  174. debug("ide_reset(%d)\n", idereset);
  175. if (idereset) {
  176. clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
  177. /* Make a delay. MPC5200 spec says 25 usec min */
  178. udelay(500000);
  179. } else
  180. setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
  181. }
  182. #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */