ahci.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. *
  7. * with the reference on libata and ahci drvier in kernel
  8. *
  9. * This driver provides a SCSI interface to SATA.
  10. */
  11. #include <common.h>
  12. #include <blk.h>
  13. #include <cpu_func.h>
  14. #include <log.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <command.h>
  18. #include <dm.h>
  19. #include <pci.h>
  20. #include <asm/processor.h>
  21. #include <linux/errno.h>
  22. #include <asm/io.h>
  23. #include <malloc.h>
  24. #include <memalign.h>
  25. #include <pci.h>
  26. #include <scsi.h>
  27. #include <libata.h>
  28. #include <linux/ctype.h>
  29. #include <ahci.h>
  30. #include <dm/device-internal.h>
  31. #include <dm/lists.h>
  32. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
  33. #ifndef CONFIG_DM_SCSI
  34. struct ahci_uc_priv *probe_ent = NULL;
  35. #endif
  36. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  37. /*
  38. * Some controllers limit number of blocks they can read/write at once.
  39. * Contemporary SSD devices work much faster if the read/write size is aligned
  40. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  41. * needed.
  42. */
  43. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  44. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  45. #endif
  46. /* Maximum timeouts for each event */
  47. #define WAIT_MS_SPINUP 20000
  48. #define WAIT_MS_DATAIO 10000
  49. #define WAIT_MS_FLUSH 5000
  50. #define WAIT_MS_LINKUP 200
  51. #define AHCI_CAP_S64A BIT(31)
  52. __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
  53. {
  54. return base + 0x100 + (port * 0x80);
  55. }
  56. #define msleep(a) udelay(a * 1000)
  57. static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
  58. {
  59. const unsigned long start = begin;
  60. const unsigned long end = start + len;
  61. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  62. flush_dcache_range(start, end);
  63. }
  64. /*
  65. * SATA controller DMAs to physical RAM. Ensure data from the
  66. * controller is invalidated from dcache; next access comes from
  67. * physical RAM.
  68. */
  69. static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
  70. {
  71. const unsigned long start = begin;
  72. const unsigned long end = start + len;
  73. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  74. invalidate_dcache_range(start, end);
  75. }
  76. /*
  77. * Ensure data for SATA controller is flushed out of dcache and
  78. * written to physical memory.
  79. */
  80. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  81. {
  82. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  83. AHCI_PORT_PRIV_DMA_SZ);
  84. }
  85. static int waiting_for_cmd_completed(void __iomem *offset,
  86. int timeout_msec,
  87. u32 sign)
  88. {
  89. int i;
  90. u32 status;
  91. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  92. msleep(1);
  93. return (i < timeout_msec) ? 0 : -1;
  94. }
  95. int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
  96. {
  97. u32 tmp;
  98. int j = 0;
  99. void __iomem *port_mmio = uc_priv->port[port].port_mmio;
  100. /*
  101. * Bring up SATA link.
  102. * SATA link bringup time is usually less than 1 ms; only very
  103. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  104. */
  105. while (j < WAIT_MS_LINKUP) {
  106. tmp = readl(port_mmio + PORT_SCR_STAT);
  107. tmp &= PORT_SCR_STAT_DET_MASK;
  108. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  109. return 0;
  110. udelay(1000);
  111. j++;
  112. }
  113. return 1;
  114. }
  115. #ifdef CONFIG_SUNXI_AHCI
  116. /* The sunxi AHCI controller requires this undocumented setup */
  117. static void sunxi_dma_init(void __iomem *port_mmio)
  118. {
  119. clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
  120. }
  121. #endif
  122. int ahci_reset(void __iomem *base)
  123. {
  124. int i = 1000;
  125. u32 __iomem *host_ctl_reg = base + HOST_CTL;
  126. u32 tmp = readl(host_ctl_reg); /* global controller reset */
  127. if ((tmp & HOST_RESET) == 0)
  128. writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
  129. /*
  130. * reset must complete within 1 second, or
  131. * the hardware should be considered fried.
  132. */
  133. do {
  134. udelay(1000);
  135. tmp = readl(host_ctl_reg);
  136. i--;
  137. } while ((i > 0) && (tmp & HOST_RESET));
  138. if (i == 0) {
  139. printf("controller reset failed (0x%x)\n", tmp);
  140. return -1;
  141. }
  142. return 0;
  143. }
  144. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  145. {
  146. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  147. # ifdef CONFIG_DM_PCI
  148. struct udevice *dev = uc_priv->dev;
  149. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  150. # else
  151. pci_dev_t pdev = uc_priv->dev;
  152. unsigned short vendor;
  153. # endif
  154. u16 tmp16;
  155. #endif
  156. void __iomem *mmio = uc_priv->mmio_base;
  157. u32 tmp, cap_save, cmd;
  158. int i, j, ret;
  159. void __iomem *port_mmio;
  160. u32 port_map;
  161. debug("ahci_host_init: start\n");
  162. cap_save = readl(mmio + HOST_CAP);
  163. cap_save &= ((1 << 28) | (1 << 17));
  164. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  165. ret = ahci_reset(uc_priv->mmio_base);
  166. if (ret)
  167. return ret;
  168. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  169. writel(cap_save, mmio + HOST_CAP);
  170. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  171. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  172. # ifdef CONFIG_DM_PCI
  173. if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
  174. u16 tmp16;
  175. dm_pci_read_config16(dev, 0x92, &tmp16);
  176. dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
  177. }
  178. # else
  179. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  180. if (vendor == PCI_VENDOR_ID_INTEL) {
  181. u16 tmp16;
  182. pci_read_config_word(pdev, 0x92, &tmp16);
  183. tmp16 |= 0xf;
  184. pci_write_config_word(pdev, 0x92, tmp16);
  185. }
  186. # endif
  187. #endif
  188. uc_priv->cap = readl(mmio + HOST_CAP);
  189. uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
  190. port_map = uc_priv->port_map;
  191. uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
  192. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  193. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  194. #if !defined(CONFIG_DM_SCSI)
  195. if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  196. uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  197. #endif
  198. for (i = 0; i < uc_priv->n_ports; i++) {
  199. if (!(port_map & (1 << i)))
  200. continue;
  201. uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
  202. port_mmio = (u8 *)uc_priv->port[i].port_mmio;
  203. /* make sure port is not active */
  204. tmp = readl(port_mmio + PORT_CMD);
  205. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  206. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  207. debug("Port %d is active. Deactivating.\n", i);
  208. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  209. PORT_CMD_FIS_RX | PORT_CMD_START);
  210. writel_with_flush(tmp, port_mmio + PORT_CMD);
  211. /* spec says 500 msecs for each bit, so
  212. * this is slightly incorrect.
  213. */
  214. msleep(500);
  215. }
  216. #ifdef CONFIG_SUNXI_AHCI
  217. sunxi_dma_init(port_mmio);
  218. #endif
  219. /* Add the spinup command to whatever mode bits may
  220. * already be on in the command register.
  221. */
  222. cmd = readl(port_mmio + PORT_CMD);
  223. cmd |= PORT_CMD_SPIN_UP;
  224. writel_with_flush(cmd, port_mmio + PORT_CMD);
  225. /* Bring up SATA link. */
  226. ret = ahci_link_up(uc_priv, i);
  227. if (ret) {
  228. printf("SATA link %d timeout.\n", i);
  229. continue;
  230. } else {
  231. debug("SATA link ok.\n");
  232. }
  233. /* Clear error status */
  234. tmp = readl(port_mmio + PORT_SCR_ERR);
  235. if (tmp)
  236. writel(tmp, port_mmio + PORT_SCR_ERR);
  237. debug("Spinning up device on SATA port %d... ", i);
  238. j = 0;
  239. while (j < WAIT_MS_SPINUP) {
  240. tmp = readl(port_mmio + PORT_TFDATA);
  241. if (!(tmp & (ATA_BUSY | ATA_DRQ)))
  242. break;
  243. udelay(1000);
  244. tmp = readl(port_mmio + PORT_SCR_STAT);
  245. tmp &= PORT_SCR_STAT_DET_MASK;
  246. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  247. break;
  248. j++;
  249. }
  250. tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
  251. if (tmp == PORT_SCR_STAT_DET_COMINIT) {
  252. debug("SATA link %d down (COMINIT received), retrying...\n", i);
  253. i--;
  254. continue;
  255. }
  256. printf("Target spinup took %d ms.\n", j);
  257. if (j == WAIT_MS_SPINUP)
  258. debug("timeout.\n");
  259. else
  260. debug("ok.\n");
  261. tmp = readl(port_mmio + PORT_SCR_ERR);
  262. debug("PORT_SCR_ERR 0x%x\n", tmp);
  263. writel(tmp, port_mmio + PORT_SCR_ERR);
  264. /* ack any pending irq events for this port */
  265. tmp = readl(port_mmio + PORT_IRQ_STAT);
  266. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  267. if (tmp)
  268. writel(tmp, port_mmio + PORT_IRQ_STAT);
  269. writel(1 << i, mmio + HOST_IRQ_STAT);
  270. /* register linkup ports */
  271. tmp = readl(port_mmio + PORT_SCR_STAT);
  272. debug("SATA port %d status: 0x%x\n", i, tmp);
  273. if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
  274. uc_priv->link_port_map |= (0x01 << i);
  275. }
  276. tmp = readl(mmio + HOST_CTL);
  277. debug("HOST_CTL 0x%x\n", tmp);
  278. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  279. tmp = readl(mmio + HOST_CTL);
  280. debug("HOST_CTL 0x%x\n", tmp);
  281. #if !defined(CONFIG_DM_SCSI)
  282. #ifndef CONFIG_SCSI_AHCI_PLAT
  283. # ifdef CONFIG_DM_PCI
  284. dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
  285. tmp |= PCI_COMMAND_MASTER;
  286. dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
  287. # else
  288. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  289. tmp |= PCI_COMMAND_MASTER;
  290. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  291. # endif
  292. #endif
  293. #endif
  294. return 0;
  295. }
  296. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  297. {
  298. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  299. # if defined(CONFIG_DM_PCI)
  300. struct udevice *dev = uc_priv->dev;
  301. # else
  302. pci_dev_t pdev = uc_priv->dev;
  303. # endif
  304. u16 cc;
  305. #endif
  306. void __iomem *mmio = uc_priv->mmio_base;
  307. u32 vers, cap, cap2, impl, speed;
  308. const char *speed_s;
  309. const char *scc_s;
  310. vers = readl(mmio + HOST_VERSION);
  311. cap = uc_priv->cap;
  312. cap2 = readl(mmio + HOST_CAP2);
  313. impl = uc_priv->port_map;
  314. speed = (cap >> 20) & 0xf;
  315. if (speed == 1)
  316. speed_s = "1.5";
  317. else if (speed == 2)
  318. speed_s = "3";
  319. else if (speed == 3)
  320. speed_s = "6";
  321. else
  322. speed_s = "?";
  323. #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
  324. scc_s = "SATA";
  325. #else
  326. # ifdef CONFIG_DM_PCI
  327. dm_pci_read_config16(dev, 0x0a, &cc);
  328. # else
  329. pci_read_config_word(pdev, 0x0a, &cc);
  330. # endif
  331. if (cc == 0x0101)
  332. scc_s = "IDE";
  333. else if (cc == 0x0106)
  334. scc_s = "SATA";
  335. else if (cc == 0x0104)
  336. scc_s = "RAID";
  337. else
  338. scc_s = "unknown";
  339. #endif
  340. printf("AHCI %02x%02x.%02x%02x "
  341. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  342. (vers >> 24) & 0xff,
  343. (vers >> 16) & 0xff,
  344. (vers >> 8) & 0xff,
  345. vers & 0xff,
  346. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  347. printf("flags: "
  348. "%s%s%s%s%s%s%s"
  349. "%s%s%s%s%s%s%s"
  350. "%s%s%s%s%s%s\n",
  351. cap & (1 << 31) ? "64bit " : "",
  352. cap & (1 << 30) ? "ncq " : "",
  353. cap & (1 << 28) ? "ilck " : "",
  354. cap & (1 << 27) ? "stag " : "",
  355. cap & (1 << 26) ? "pm " : "",
  356. cap & (1 << 25) ? "led " : "",
  357. cap & (1 << 24) ? "clo " : "",
  358. cap & (1 << 19) ? "nz " : "",
  359. cap & (1 << 18) ? "only " : "",
  360. cap & (1 << 17) ? "pmp " : "",
  361. cap & (1 << 16) ? "fbss " : "",
  362. cap & (1 << 15) ? "pio " : "",
  363. cap & (1 << 14) ? "slum " : "",
  364. cap & (1 << 13) ? "part " : "",
  365. cap & (1 << 7) ? "ccc " : "",
  366. cap & (1 << 6) ? "ems " : "",
  367. cap & (1 << 5) ? "sxs " : "",
  368. cap2 & (1 << 2) ? "apst " : "",
  369. cap2 & (1 << 1) ? "nvmp " : "",
  370. cap2 & (1 << 0) ? "boh " : "");
  371. }
  372. #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
  373. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  374. static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
  375. # else
  376. static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
  377. # endif
  378. {
  379. #if !defined(CONFIG_DM_SCSI)
  380. u16 vendor;
  381. #endif
  382. int rc;
  383. uc_priv->dev = dev;
  384. uc_priv->host_flags = ATA_FLAG_SATA
  385. | ATA_FLAG_NO_LEGACY
  386. | ATA_FLAG_MMIO
  387. | ATA_FLAG_PIO_DMA
  388. | ATA_FLAG_NO_ATAPI;
  389. uc_priv->pio_mask = 0x1f;
  390. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  391. #if !defined(CONFIG_DM_SCSI)
  392. #ifdef CONFIG_DM_PCI
  393. uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  394. PCI_REGION_MEM);
  395. /* Take from kernel:
  396. * JMicron-specific fixup:
  397. * make sure we're in AHCI mode
  398. */
  399. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  400. if (vendor == 0x197b)
  401. dm_pci_write_config8(dev, 0x41, 0xa1);
  402. #else
  403. uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  404. PCI_REGION_MEM);
  405. /* Take from kernel:
  406. * JMicron-specific fixup:
  407. * make sure we're in AHCI mode
  408. */
  409. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  410. if (vendor == 0x197b)
  411. pci_write_config_byte(dev, 0x41, 0xa1);
  412. #endif
  413. #else
  414. struct scsi_plat *plat = dev_get_uclass_plat(dev);
  415. uc_priv->mmio_base = (void *)plat->base;
  416. #endif
  417. debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
  418. /* initialize adapter */
  419. rc = ahci_host_init(uc_priv);
  420. if (rc)
  421. goto err_out;
  422. ahci_print_info(uc_priv);
  423. return 0;
  424. err_out:
  425. return rc;
  426. }
  427. #endif
  428. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  429. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  430. unsigned char *buf, int buf_len)
  431. {
  432. struct ahci_ioports *pp = &(uc_priv->port[port]);
  433. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  434. phys_addr_t pa = virt_to_phys(buf);
  435. u32 sg_count;
  436. int i;
  437. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  438. if (sg_count > AHCI_MAX_SG) {
  439. printf("Error:Too much sg!\n");
  440. return -1;
  441. }
  442. for (i = 0; i < sg_count; i++) {
  443. ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
  444. ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
  445. if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
  446. printf("Error: DMA address too high\n");
  447. return -1;
  448. }
  449. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  450. (buf_len < MAX_DATA_BYTE_COUNT ?
  451. (buf_len - 1) :
  452. (MAX_DATA_BYTE_COUNT - 1)));
  453. ahci_sg++;
  454. buf_len -= MAX_DATA_BYTE_COUNT;
  455. pa += MAX_DATA_BYTE_COUNT;
  456. }
  457. return sg_count;
  458. }
  459. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  460. {
  461. phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
  462. pp->cmd_slot->opts = cpu_to_le32(opts);
  463. pp->cmd_slot->status = 0;
  464. pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
  465. #ifdef CONFIG_PHYS_64BIT
  466. pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
  467. #endif
  468. }
  469. static int wait_spinup(void __iomem *port_mmio)
  470. {
  471. ulong start;
  472. u32 tf_data;
  473. start = get_timer(0);
  474. do {
  475. tf_data = readl(port_mmio + PORT_TFDATA);
  476. if (!(tf_data & ATA_BUSY))
  477. return 0;
  478. } while (get_timer(start) < WAIT_MS_SPINUP);
  479. return -ETIMEDOUT;
  480. }
  481. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  482. {
  483. struct ahci_ioports *pp = &(uc_priv->port[port]);
  484. void __iomem *port_mmio = pp->port_mmio;
  485. u64 dma_addr;
  486. u32 port_status;
  487. void __iomem *mem;
  488. debug("Enter start port: %d\n", port);
  489. port_status = readl(port_mmio + PORT_SCR_STAT);
  490. debug("Port %d status: %x\n", port, port_status);
  491. if ((port_status & 0xf) != 0x03) {
  492. printf("No Link on this port!\n");
  493. return -1;
  494. }
  495. mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
  496. if (!mem) {
  497. free(pp);
  498. printf("%s: No mem for table!\n", __func__);
  499. return -ENOMEM;
  500. }
  501. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  502. /*
  503. * First item in chunk of DMA memory: 32-slot command table,
  504. * 32 bytes each in size
  505. */
  506. pp->cmd_slot =
  507. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  508. debug("cmd_slot = %p\n", pp->cmd_slot);
  509. mem += (AHCI_CMD_SLOT_SZ + 224);
  510. /*
  511. * Second item: Received-FIS area
  512. */
  513. pp->rx_fis = virt_to_phys((void *)mem);
  514. mem += AHCI_RX_FIS_SZ;
  515. /*
  516. * Third item: data area for storing a single command
  517. * and its scatter-gather table
  518. */
  519. pp->cmd_tbl = virt_to_phys((void *)mem);
  520. debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
  521. mem += AHCI_CMD_TBL_HDR;
  522. pp->cmd_tbl_sg =
  523. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  524. dma_addr = (ulong)pp->cmd_slot;
  525. writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
  526. writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
  527. dma_addr = (ulong)pp->rx_fis;
  528. writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
  529. writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
  530. #ifdef CONFIG_SUNXI_AHCI
  531. sunxi_dma_init(port_mmio);
  532. #endif
  533. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  534. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  535. PORT_CMD_START, port_mmio + PORT_CMD);
  536. debug("Exit start port %d\n", port);
  537. /*
  538. * Make sure interface is not busy based on error and status
  539. * information from task file data register before proceeding
  540. */
  541. return wait_spinup(port_mmio);
  542. }
  543. static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
  544. int fis_len, u8 *buf, int buf_len, u8 is_write)
  545. {
  546. struct ahci_ioports *pp = &(uc_priv->port[port]);
  547. void __iomem *port_mmio = pp->port_mmio;
  548. u32 opts;
  549. u32 port_status;
  550. int sg_count;
  551. debug("Enter %s: for port %d\n", __func__, port);
  552. if (port > uc_priv->n_ports) {
  553. printf("Invalid port number %d\n", port);
  554. return -1;
  555. }
  556. port_status = readl(port_mmio + PORT_SCR_STAT);
  557. if ((port_status & 0xf) != 0x03) {
  558. debug("No Link on port %d!\n", port);
  559. return -1;
  560. }
  561. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  562. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  563. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  564. ahci_fill_cmd_slot(pp, opts);
  565. ahci_dcache_flush_sata_cmd(pp);
  566. ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
  567. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  568. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  569. WAIT_MS_DATAIO, 0x1)) {
  570. printf("timeout exit!\n");
  571. return -1;
  572. }
  573. ahci_dcache_invalidate_range((unsigned long)buf,
  574. (unsigned long)buf_len);
  575. debug("%s: %d byte transferred.\n", __func__,
  576. le32_to_cpu(pp->cmd_slot->status));
  577. return 0;
  578. }
  579. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  580. {
  581. int i;
  582. for (i = 0; i < len / 2; i++)
  583. target[i] = swab16(src[i]);
  584. return (char *)target;
  585. }
  586. /*
  587. * SCSI INQUIRY command operation.
  588. */
  589. static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  590. struct scsi_cmd *pccb)
  591. {
  592. static const u8 hdr[] = {
  593. 0,
  594. 0,
  595. 0x5, /* claim SPC-3 version compatibility */
  596. 2,
  597. 95 - 4,
  598. };
  599. u8 fis[20];
  600. u16 *idbuf;
  601. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  602. u8 port;
  603. /* Clean ccb data buffer */
  604. memset(pccb->pdata, 0, pccb->datalen);
  605. memcpy(pccb->pdata, hdr, sizeof(hdr));
  606. if (pccb->datalen <= 35)
  607. return 0;
  608. memset(fis, 0, sizeof(fis));
  609. /* Construct the FIS */
  610. fis[0] = 0x27; /* Host to device FIS. */
  611. fis[1] = 1 << 7; /* Command FIS. */
  612. fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
  613. /* Read id from sata */
  614. port = pccb->target;
  615. if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
  616. (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
  617. debug("scsi_ahci: SCSI inquiry command failure.\n");
  618. return -EIO;
  619. }
  620. if (!uc_priv->ataid[port]) {
  621. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  622. if (!uc_priv->ataid[port]) {
  623. printf("%s: No memory for ataid[port]\n", __func__);
  624. return -ENOMEM;
  625. }
  626. }
  627. idbuf = uc_priv->ataid[port];
  628. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  629. ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
  630. memcpy(&pccb->pdata[8], "ATA ", 8);
  631. ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  632. ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  633. #ifdef DEBUG
  634. ata_dump_id(idbuf);
  635. #endif
  636. return 0;
  637. }
  638. /*
  639. * SCSI READ10/WRITE10 command operation.
  640. */
  641. static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
  642. struct scsi_cmd *pccb, u8 is_write)
  643. {
  644. lbaint_t lba = 0;
  645. u16 blocks = 0;
  646. u8 fis[20];
  647. u8 *user_buffer = pccb->pdata;
  648. u32 user_buffer_size = pccb->datalen;
  649. /* Retrieve the base LBA number from the ccb structure. */
  650. if (pccb->cmd[0] == SCSI_READ16) {
  651. memcpy(&lba, pccb->cmd + 2, 8);
  652. lba = be64_to_cpu(lba);
  653. } else {
  654. u32 temp;
  655. memcpy(&temp, pccb->cmd + 2, 4);
  656. lba = be32_to_cpu(temp);
  657. }
  658. /*
  659. * Retrieve the base LBA number and the block count from
  660. * the ccb structure.
  661. *
  662. * For 10-byte and 16-byte SCSI R/W commands, transfer
  663. * length 0 means transfer 0 block of data.
  664. * However, for ATA R/W commands, sector count 0 means
  665. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  666. *
  667. * WARNING: one or two older ATA drives treat 0 as 0...
  668. */
  669. if (pccb->cmd[0] == SCSI_READ16)
  670. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
  671. else
  672. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  673. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  674. is_write ? "write" : "read", blocks, lba);
  675. /* Preset the FIS */
  676. memset(fis, 0, sizeof(fis));
  677. fis[0] = 0x27; /* Host to device FIS. */
  678. fis[1] = 1 << 7; /* Command FIS. */
  679. /* Command byte (read/write). */
  680. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  681. while (blocks) {
  682. u16 now_blocks; /* number of blocks per iteration */
  683. u32 transfer_size; /* number of bytes per iteration */
  684. now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
  685. transfer_size = ATA_SECT_SIZE * now_blocks;
  686. if (transfer_size > user_buffer_size) {
  687. printf("scsi_ahci: Error: buffer too small.\n");
  688. return -EIO;
  689. }
  690. /*
  691. * LBA48 SATA command but only use 32bit address range within
  692. * that (unless we've enabled 64bit LBA support). The next
  693. * smaller command range (28bit) is too small.
  694. */
  695. fis[4] = (lba >> 0) & 0xff;
  696. fis[5] = (lba >> 8) & 0xff;
  697. fis[6] = (lba >> 16) & 0xff;
  698. fis[7] = 1 << 6; /* device reg: set LBA mode */
  699. fis[8] = ((lba >> 24) & 0xff);
  700. #ifdef CONFIG_SYS_64BIT_LBA
  701. if (pccb->cmd[0] == SCSI_READ16) {
  702. fis[9] = ((lba >> 32) & 0xff);
  703. fis[10] = ((lba >> 40) & 0xff);
  704. }
  705. #endif
  706. fis[3] = 0xe0; /* features */
  707. /* Block (sector) count */
  708. fis[12] = (now_blocks >> 0) & 0xff;
  709. fis[13] = (now_blocks >> 8) & 0xff;
  710. /* Read/Write from ahci */
  711. if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
  712. sizeof(fis), user_buffer, transfer_size,
  713. is_write)) {
  714. debug("scsi_ahci: SCSI %s10 command failure.\n",
  715. is_write ? "WRITE" : "READ");
  716. return -EIO;
  717. }
  718. /* If this transaction is a write, do a following flush.
  719. * Writes in u-boot are so rare, and the logic to know when is
  720. * the last write and do a flush only there is sufficiently
  721. * difficult. Just do a flush after every write. This incurs,
  722. * usually, one extra flush when the rare writes do happen.
  723. */
  724. if (is_write) {
  725. if (-EIO == ata_io_flush(uc_priv, pccb->target))
  726. return -EIO;
  727. }
  728. user_buffer += transfer_size;
  729. user_buffer_size -= transfer_size;
  730. blocks -= now_blocks;
  731. lba += now_blocks;
  732. }
  733. return 0;
  734. }
  735. /*
  736. * SCSI READ CAPACITY10 command operation.
  737. */
  738. static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  739. struct scsi_cmd *pccb)
  740. {
  741. u32 cap;
  742. u64 cap64;
  743. u32 block_size;
  744. if (!uc_priv->ataid[pccb->target]) {
  745. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  746. "\tNo ATA info!\n"
  747. "\tPlease run SCSI command INQUIRY first!\n");
  748. return -EPERM;
  749. }
  750. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  751. if (cap64 > 0x100000000ULL)
  752. cap64 = 0xffffffff;
  753. cap = cpu_to_be32(cap64);
  754. memcpy(pccb->pdata, &cap, sizeof(cap));
  755. block_size = cpu_to_be32((u32)512);
  756. memcpy(&pccb->pdata[4], &block_size, 4);
  757. return 0;
  758. }
  759. /*
  760. * SCSI READ CAPACITY16 command operation.
  761. */
  762. static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  763. struct scsi_cmd *pccb)
  764. {
  765. u64 cap;
  766. u64 block_size;
  767. if (!uc_priv->ataid[pccb->target]) {
  768. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  769. "\tNo ATA info!\n"
  770. "\tPlease run SCSI command INQUIRY first!\n");
  771. return -EPERM;
  772. }
  773. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  774. cap = cpu_to_be64(cap);
  775. memcpy(pccb->pdata, &cap, sizeof(cap));
  776. block_size = cpu_to_be64((u64)512);
  777. memcpy(&pccb->pdata[8], &block_size, 8);
  778. return 0;
  779. }
  780. /*
  781. * SCSI TEST UNIT READY command operation.
  782. */
  783. static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  784. struct scsi_cmd *pccb)
  785. {
  786. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  787. }
  788. static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  789. {
  790. struct ahci_uc_priv *uc_priv;
  791. #ifdef CONFIG_DM_SCSI
  792. uc_priv = dev_get_uclass_priv(dev->parent);
  793. #else
  794. uc_priv = probe_ent;
  795. #endif
  796. int ret;
  797. switch (pccb->cmd[0]) {
  798. case SCSI_READ16:
  799. case SCSI_READ10:
  800. ret = ata_scsiop_read_write(uc_priv, pccb, 0);
  801. break;
  802. case SCSI_WRITE10:
  803. ret = ata_scsiop_read_write(uc_priv, pccb, 1);
  804. break;
  805. case SCSI_RD_CAPAC10:
  806. ret = ata_scsiop_read_capacity10(uc_priv, pccb);
  807. break;
  808. case SCSI_RD_CAPAC16:
  809. ret = ata_scsiop_read_capacity16(uc_priv, pccb);
  810. break;
  811. case SCSI_TST_U_RDY:
  812. ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
  813. break;
  814. case SCSI_INQUIRY:
  815. ret = ata_scsiop_inquiry(uc_priv, pccb);
  816. break;
  817. default:
  818. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  819. return -ENOTSUPP;
  820. }
  821. if (ret) {
  822. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  823. return ret;
  824. }
  825. return 0;
  826. }
  827. static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
  828. {
  829. u32 linkmap;
  830. int i;
  831. linkmap = uc_priv->link_port_map;
  832. for (i = 0; i < uc_priv->n_ports; i++) {
  833. if (((linkmap >> i) & 0x01)) {
  834. if (ahci_port_start(uc_priv, (u8) i)) {
  835. printf("Can not start port %d\n", i);
  836. continue;
  837. }
  838. }
  839. }
  840. return 0;
  841. }
  842. #ifndef CONFIG_DM_SCSI
  843. void scsi_low_level_init(int busdevfunc)
  844. {
  845. struct ahci_uc_priv *uc_priv;
  846. #ifndef CONFIG_SCSI_AHCI_PLAT
  847. probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
  848. if (!probe_ent) {
  849. printf("%s: No memory for uc_priv\n", __func__);
  850. return;
  851. }
  852. uc_priv = probe_ent;
  853. # if defined(CONFIG_DM_PCI)
  854. struct udevice *dev;
  855. int ret;
  856. ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
  857. if (ret)
  858. return;
  859. ahci_init_one(uc_priv, dev);
  860. # else
  861. ahci_init_one(uc_priv, busdevfunc);
  862. # endif
  863. #else
  864. uc_priv = probe_ent;
  865. #endif
  866. ahci_start_ports(uc_priv);
  867. }
  868. #endif
  869. #ifndef CONFIG_SCSI_AHCI_PLAT
  870. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  871. int ahci_init_one_dm(struct udevice *dev)
  872. {
  873. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  874. return ahci_init_one(uc_priv, dev);
  875. }
  876. #endif
  877. #endif
  878. int ahci_start_ports_dm(struct udevice *dev)
  879. {
  880. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  881. return ahci_start_ports(uc_priv);
  882. }
  883. #ifdef CONFIG_SCSI_AHCI_PLAT
  884. static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
  885. {
  886. int rc;
  887. uc_priv->host_flags = ATA_FLAG_SATA
  888. | ATA_FLAG_NO_LEGACY
  889. | ATA_FLAG_MMIO
  890. | ATA_FLAG_PIO_DMA
  891. | ATA_FLAG_NO_ATAPI;
  892. uc_priv->pio_mask = 0x1f;
  893. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  894. uc_priv->mmio_base = base;
  895. /* initialize adapter */
  896. rc = ahci_host_init(uc_priv);
  897. if (rc)
  898. goto err_out;
  899. ahci_print_info(uc_priv);
  900. rc = ahci_start_ports(uc_priv);
  901. err_out:
  902. return rc;
  903. }
  904. #ifndef CONFIG_DM_SCSI
  905. int ahci_init(void __iomem *base)
  906. {
  907. struct ahci_uc_priv *uc_priv;
  908. probe_ent = malloc(sizeof(struct ahci_uc_priv));
  909. if (!probe_ent) {
  910. printf("%s: No memory for uc_priv\n", __func__);
  911. return -ENOMEM;
  912. }
  913. uc_priv = probe_ent;
  914. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  915. return ahci_init_common(uc_priv, base);
  916. }
  917. #endif
  918. int ahci_init_dm(struct udevice *dev, void __iomem *base)
  919. {
  920. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  921. return ahci_init_common(uc_priv, base);
  922. }
  923. void __weak scsi_init(void)
  924. {
  925. }
  926. #endif /* CONFIG_SCSI_AHCI_PLAT */
  927. /*
  928. * In the general case of generic rotating media it makes sense to have a
  929. * flush capability. It probably even makes sense in the case of SSDs because
  930. * one cannot always know for sure what kind of internal cache/flush mechanism
  931. * is embodied therein. At first it was planned to invoke this after the last
  932. * write to disk and before rebooting. In practice, knowing, a priori, which
  933. * is the last write is difficult. Because writing to the disk in u-boot is
  934. * very rare, this flush command will be invoked after every block write.
  935. */
  936. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
  937. {
  938. u8 fis[20];
  939. struct ahci_ioports *pp = &(uc_priv->port[port]);
  940. void __iomem *port_mmio = pp->port_mmio;
  941. u32 cmd_fis_len = 5; /* five dwords */
  942. /* Preset the FIS */
  943. memset(fis, 0, 20);
  944. fis[0] = 0x27; /* Host to device FIS. */
  945. fis[1] = 1 << 7; /* Command FIS. */
  946. fis[2] = ATA_CMD_FLUSH_EXT;
  947. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  948. ahci_fill_cmd_slot(pp, cmd_fis_len);
  949. ahci_dcache_flush_sata_cmd(pp);
  950. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  951. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  952. WAIT_MS_FLUSH, 0x1)) {
  953. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  954. return -EIO;
  955. }
  956. return 0;
  957. }
  958. static int ahci_scsi_bus_reset(struct udevice *dev)
  959. {
  960. /* Not implemented */
  961. return 0;
  962. }
  963. #ifdef CONFIG_DM_SCSI
  964. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
  965. {
  966. struct udevice *dev;
  967. int ret;
  968. ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
  969. if (ret)
  970. return ret;
  971. *devp = dev;
  972. return 0;
  973. }
  974. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
  975. {
  976. struct ahci_uc_priv *uc_priv;
  977. struct scsi_plat *uc_plat;
  978. struct udevice *dev;
  979. int ret;
  980. device_find_first_child(ahci_dev, &dev);
  981. if (!dev)
  982. return -ENODEV;
  983. uc_plat = dev_get_uclass_plat(dev);
  984. uc_plat->base = base;
  985. uc_plat->max_lun = 1;
  986. uc_plat->max_id = 2;
  987. uc_priv = dev_get_uclass_priv(ahci_dev);
  988. ret = ahci_init_one(uc_priv, dev);
  989. if (ret)
  990. return ret;
  991. ret = ahci_start_ports(uc_priv);
  992. if (ret)
  993. return ret;
  994. /*
  995. * scsi_scan_dev() scans devices up-to the number of max_id.
  996. * Update max_id if the number of detected ports exceeds max_id.
  997. * This allows SCSI to scan all detected ports.
  998. */
  999. uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
  1000. uc_plat->max_id);
  1001. /* If port count is less than max_id, update max_id */
  1002. if (uc_priv->n_ports < uc_plat->max_id)
  1003. uc_plat->max_id = uc_priv->n_ports;
  1004. return 0;
  1005. }
  1006. #ifdef CONFIG_DM_PCI
  1007. int ahci_probe_scsi_pci(struct udevice *ahci_dev)
  1008. {
  1009. ulong base;
  1010. u16 vendor, device;
  1011. base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
  1012. PCI_REGION_MEM);
  1013. /*
  1014. * Note:
  1015. * Right now, we have only one quirk here, which is not enough to
  1016. * introduce a new Kconfig option to select this. Once we have more
  1017. * quirks in this AHCI code, we should add a Kconfig option for
  1018. * this though.
  1019. */
  1020. dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
  1021. dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
  1022. if (vendor == PCI_VENDOR_ID_CAVIUM &&
  1023. device == PCI_DEVICE_ID_CAVIUM_SATA)
  1024. base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
  1025. PCI_REGION_MEM);
  1026. return ahci_probe_scsi(ahci_dev, base);
  1027. }
  1028. #endif
  1029. struct scsi_ops scsi_ops = {
  1030. .exec = ahci_scsi_exec,
  1031. .bus_reset = ahci_scsi_bus_reset,
  1032. };
  1033. U_BOOT_DRIVER(ahci_scsi) = {
  1034. .name = "ahci_scsi",
  1035. .id = UCLASS_SCSI,
  1036. .ops = &scsi_ops,
  1037. };
  1038. #else
  1039. int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  1040. {
  1041. return ahci_scsi_exec(dev, pccb);
  1042. }
  1043. __weak int scsi_bus_reset(struct udevice *dev)
  1044. {
  1045. return ahci_scsi_bus_reset(dev);
  1046. return 0;
  1047. }
  1048. #endif