spl_a10.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <init.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/pl310.h>
  12. #include <asm/u-boot.h>
  13. #include <asm/utils.h>
  14. #include <image.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <spl.h>
  17. #include <asm/arch/system_manager.h>
  18. #include <asm/arch/freeze_controller.h>
  19. #include <asm/arch/clock_manager.h>
  20. #include <asm/arch/scan_manager.h>
  21. #include <asm/arch/sdram.h>
  22. #include <asm/arch/scu.h>
  23. #include <asm/arch/misc.h>
  24. #include <asm/arch/nic301.h>
  25. #include <asm/sections.h>
  26. #include <fdtdec.h>
  27. #include <watchdog.h>
  28. #include <asm/arch/pinmux.h>
  29. #include <asm/arch/fpga_manager.h>
  30. #include <mmc.h>
  31. #include <memalign.h>
  32. #define FPGA_BUFSIZ 16 * 1024
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
  35. #define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  36. SOCFPGA_PHYS_OCRAM_SIZE - \
  37. BOOTROM_SHARED_MEM_SIZE)
  38. #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
  39. static u32 rst_mgr_status __section(".data");
  40. /*
  41. * Bootrom will clear the status register in reset manager and stores the
  42. * reset status value in shared memory. Bootrom stores shared data at last
  43. * 2KB of onchip RAM.
  44. * This function save reset status provided by BootROM to rst_mgr_status.
  45. * More information about reset status register value can be found in reset
  46. * manager register description.
  47. * When running in debugger without Bootrom, r0 to r3 are random values.
  48. * So, skip save the value when r0 is not BootROM shared data address.
  49. *
  50. * r0 - Contains the pointer to the shared memory block. The shared
  51. * memory block is located in the top 2 KB of on-chip RAM.
  52. * r1 - contains the length of the shared memory.
  53. * r2 - unused and set to 0x0.
  54. * r3 - points to the version block.
  55. */
  56. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  57. unsigned long r3)
  58. {
  59. if (r0 == BOOTROM_SHARED_MEM_ADDR)
  60. rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
  61. save_boot_params_ret();
  62. }
  63. u32 spl_boot_device(void)
  64. {
  65. const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
  66. switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  67. case 0x1: /* FPGA (HPS2FPGA Bridge) */
  68. return BOOT_DEVICE_RAM;
  69. case 0x2: /* NAND Flash (1.8V) */
  70. case 0x3: /* NAND Flash (3.0V) */
  71. socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  72. return BOOT_DEVICE_NAND;
  73. case 0x4: /* SD/MMC External Transceiver (1.8V) */
  74. case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
  75. socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  76. socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  77. return BOOT_DEVICE_MMC1;
  78. case 0x6: /* QSPI Flash (1.8V) */
  79. case 0x7: /* QSPI Flash (3.0V) */
  80. socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  81. return BOOT_DEVICE_SPI;
  82. default:
  83. printf("Invalid boot device (bsel=%08x)!\n", bsel);
  84. hang();
  85. }
  86. }
  87. #ifdef CONFIG_SPL_MMC_SUPPORT
  88. u32 spl_mmc_boot_mode(const u32 boot_device)
  89. {
  90. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  91. return MMCSD_MODE_FS;
  92. #else
  93. return MMCSD_MODE_RAW;
  94. #endif
  95. }
  96. #endif
  97. void spl_board_init(void)
  98. {
  99. ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  100. /* enable console uart printing */
  101. preloader_console_init();
  102. WATCHDOG_RESET();
  103. arch_early_init_r();
  104. /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  105. if (is_fpgamgr_user_mode()) {
  106. int ret = config_pins(gd->fdt_blob, "shared");
  107. if (ret)
  108. return;
  109. ret = config_pins(gd->fdt_blob, "fpga");
  110. if (ret)
  111. return;
  112. } else if (!is_fpgamgr_early_user_mode()) {
  113. /* Program IOSSM(early IO release) or full FPGA */
  114. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  115. }
  116. /* If the IOSSM/full FPGA is already loaded, start DDR */
  117. if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
  118. ddr_calibration_sequence();
  119. if (!is_fpgamgr_user_mode())
  120. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  121. }
  122. void board_init_f(ulong dummy)
  123. {
  124. if (spl_early_init())
  125. hang();
  126. socfpga_get_managers_addr();
  127. dcache_disable();
  128. socfpga_init_security_policies();
  129. socfpga_sdram_remap_zero();
  130. socfpga_pl310_clear();
  131. /* Assert reset to all except L4WD0 and L4TIMER0 */
  132. socfpga_per_reset_all();
  133. socfpga_watchdog_disable();
  134. /* Configure the clock based on handoff */
  135. cm_basic_init(gd->fdt_blob);
  136. #ifdef CONFIG_HW_WATCHDOG
  137. /* release osc1 watchdog timer 0 from reset */
  138. socfpga_reset_deassert_osc1wd0();
  139. /* reconfigure and enable the watchdog */
  140. hw_watchdog_init();
  141. WATCHDOG_RESET();
  142. #endif /* CONFIG_HW_WATCHDOG */
  143. config_dedicated_pins(gd->fdt_blob);
  144. WATCHDOG_RESET();
  145. }