board.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fastboot.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <syscon.h>
  14. #include <asm/cache.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <asm/arch-rockchip/boot_mode.h>
  18. #include <asm/arch-rockchip/clock.h>
  19. #include <asm/arch-rockchip/periph.h>
  20. #include <asm/arch-rockchip/misc.h>
  21. #include <power/regulator.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. __weak int rk_board_late_init(void)
  24. {
  25. return 0;
  26. }
  27. int board_late_init(void)
  28. {
  29. setup_boot_mode();
  30. return rk_board_late_init();
  31. }
  32. int board_init(void)
  33. {
  34. int ret;
  35. #ifdef CONFIG_DM_REGULATOR
  36. ret = regulators_enable_boot_on(false);
  37. if (ret)
  38. debug("%s: Cannot enable boot on regulator\n", __func__);
  39. #endif
  40. return 0;
  41. }
  42. #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  43. void enable_caches(void)
  44. {
  45. /* Enable D-cache. I-cache is already enabled in start.S */
  46. dcache_enable();
  47. }
  48. #endif
  49. #if defined(CONFIG_USB_GADGET)
  50. #include <usb.h>
  51. #if defined(CONFIG_USB_GADGET_DWC2_OTG)
  52. #include <usb/dwc2_udc.h>
  53. static struct dwc2_plat_otg_data otg_data = {
  54. .rx_fifo_sz = 512,
  55. .np_tx_fifo_sz = 16,
  56. .tx_fifo_sz = 128,
  57. };
  58. int board_usb_init(int index, enum usb_init_type init)
  59. {
  60. ofnode node;
  61. const char *mode;
  62. bool matched = false;
  63. /* find the usb_otg node */
  64. node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
  65. while (ofnode_valid(node)) {
  66. mode = ofnode_read_string(node, "dr_mode");
  67. if (mode && strcmp(mode, "otg") == 0) {
  68. matched = true;
  69. break;
  70. }
  71. node = ofnode_by_compatible(node, "snps,dwc2");
  72. }
  73. if (!matched) {
  74. debug("Not found usb_otg device\n");
  75. return -ENODEV;
  76. }
  77. otg_data.regs_otg = ofnode_get_addr(node);
  78. #ifdef CONFIG_ROCKCHIP_RK3288
  79. int ret;
  80. u32 phandle, offset;
  81. ofnode phy_node;
  82. ret = ofnode_read_u32(node, "phys", &phandle);
  83. if (ret)
  84. return ret;
  85. node = ofnode_get_by_phandle(phandle);
  86. if (!ofnode_valid(node)) {
  87. debug("Not found usb phy device\n");
  88. return -ENODEV;
  89. }
  90. phy_node = ofnode_get_parent(node);
  91. if (!ofnode_valid(node)) {
  92. debug("Not found usb phy device\n");
  93. return -ENODEV;
  94. }
  95. otg_data.phy_of_node = phy_node;
  96. ret = ofnode_read_u32(node, "reg", &offset);
  97. if (ret)
  98. return ret;
  99. otg_data.regs_phy = offset +
  100. (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  101. #endif
  102. return dwc2_udc_probe(&otg_data);
  103. }
  104. int board_usb_cleanup(int index, enum usb_init_type init)
  105. {
  106. return 0;
  107. }
  108. #endif /* CONFIG_USB_GADGET_DWC2_OTG */
  109. #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
  110. #include <dwc3-uboot.h>
  111. static struct dwc3_device dwc3_device_data = {
  112. .maximum_speed = USB_SPEED_HIGH,
  113. .base = 0xfe800000,
  114. .dr_mode = USB_DR_MODE_PERIPHERAL,
  115. .index = 0,
  116. .dis_u2_susphy_quirk = 1,
  117. .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
  118. };
  119. int usb_gadget_handle_interrupts(int index)
  120. {
  121. dwc3_uboot_handle_interrupt(0);
  122. return 0;
  123. }
  124. int board_usb_init(int index, enum usb_init_type init)
  125. {
  126. return dwc3_uboot_init(&dwc3_device_data);
  127. }
  128. #endif /* CONFIG_USB_DWC3_GADGET */
  129. #endif /* CONFIG_USB_GADGET */
  130. #if CONFIG_IS_ENABLED(FASTBOOT)
  131. int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
  132. {
  133. if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
  134. return -ENOTSUPP;
  135. printf("Setting reboot to fastboot flag ...\n");
  136. /* Set boot mode to fastboot */
  137. writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
  138. return 0;
  139. }
  140. #endif
  141. #ifdef CONFIG_MISC_INIT_R
  142. __weak int misc_init_r(void)
  143. {
  144. const u32 cpuid_offset = 0x7;
  145. const u32 cpuid_length = 0x10;
  146. u8 cpuid[cpuid_length];
  147. int ret;
  148. ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
  149. if (ret)
  150. return ret;
  151. ret = rockchip_cpuid_set(cpuid, cpuid_length);
  152. if (ret)
  153. return ret;
  154. ret = rockchip_setup_macaddr();
  155. return ret;
  156. }
  157. #endif