j721e_init.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * J721E: SoC specific initialization
  4. *
  5. * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <asm/armv7_mpu.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sysfw-loader.h>
  15. #include "common.h"
  16. #include <asm/arch/sys_proto.h>
  17. #include <linux/soc/ti/ti_sci_protocol.h>
  18. #include <dm.h>
  19. #include <dm/uclass-internal.h>
  20. #include <dm/pinctrl.h>
  21. #include <mmc.h>
  22. #include <remoteproc.h>
  23. #ifdef CONFIG_SPL_BUILD
  24. #ifdef CONFIG_K3_LOAD_SYSFW
  25. #ifdef CONFIG_TI_SECURE_DEVICE
  26. struct fwl_data cbass_hc_cfg0_fwls[] = {
  27. { "PCIE0_CFG", 2560, 8 },
  28. { "PCIE1_CFG", 2561, 8 },
  29. { "USB3SS0_CORE", 2568, 4 },
  30. { "USB3SS1_CORE", 2570, 4 },
  31. { "EMMC8SS0_CFG", 2576, 4 },
  32. { "UFS_HCI0_CFG", 2580, 4 },
  33. { "SERDES0", 2584, 1 },
  34. { "SERDES1", 2585, 1 },
  35. }, cbass_hc0_fwls[] = {
  36. { "PCIE0_HP", 2528, 24 },
  37. { "PCIE0_LP", 2529, 24 },
  38. { "PCIE1_HP", 2530, 24 },
  39. { "PCIE1_LP", 2531, 24 },
  40. }, cbass_rc_cfg0_fwls[] = {
  41. { "EMMCSD4SS0_CFG", 2380, 4 },
  42. }, cbass_rc0_fwls[] = {
  43. { "GPMC0", 2310, 8 },
  44. }, infra_cbass0_fwls[] = {
  45. { "PLL_MMR0", 8, 26 },
  46. { "CTRL_MMR0", 9, 16 },
  47. }, mcu_cbass0_fwls[] = {
  48. { "MCU_R5FSS0_CORE0", 1024, 4 },
  49. { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  50. { "MCU_R5FSS0_CORE1", 1028, 4 },
  51. { "MCU_FSS0_CFG", 1032, 12 },
  52. { "MCU_FSS0_S1", 1033, 8 },
  53. { "MCU_FSS0_S0", 1036, 8 },
  54. { "MCU_PSROM49152X32", 1048, 1 },
  55. { "MCU_MSRAM128KX64", 1050, 8 },
  56. { "MCU_CTRL_MMR0", 1200, 8 },
  57. { "MCU_PLL_MMR0", 1201, 3 },
  58. { "MCU_CPSW0", 1220, 2 },
  59. }, wkup_cbass0_fwls[] = {
  60. { "WKUP_CTRL_MMR0", 131, 16 },
  61. };
  62. #endif
  63. #endif
  64. static void ctrl_mmr_unlock(void)
  65. {
  66. /* Unlock all WKUP_CTRL_MMR0 module registers */
  67. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  68. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  69. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  70. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  71. mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  72. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  73. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  74. /* Unlock all MCU_CTRL_MMR0 module registers */
  75. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  76. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  77. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  78. mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  79. mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  80. /* Unlock all CTRL_MMR0 module registers */
  81. mmr_unlock(CTRL_MMR0_BASE, 0);
  82. mmr_unlock(CTRL_MMR0_BASE, 1);
  83. mmr_unlock(CTRL_MMR0_BASE, 2);
  84. mmr_unlock(CTRL_MMR0_BASE, 3);
  85. mmr_unlock(CTRL_MMR0_BASE, 5);
  86. if (soc_is_j721e())
  87. mmr_unlock(CTRL_MMR0_BASE, 6);
  88. mmr_unlock(CTRL_MMR0_BASE, 7);
  89. }
  90. #if defined(CONFIG_K3_LOAD_SYSFW)
  91. void k3_mmc_stop_clock(void)
  92. {
  93. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  94. struct mmc *mmc = find_mmc_device(0);
  95. if (!mmc)
  96. return;
  97. mmc->saved_clock = mmc->clock;
  98. mmc_set_clock(mmc, 0, true);
  99. }
  100. }
  101. void k3_mmc_restart_clock(void)
  102. {
  103. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  104. struct mmc *mmc = find_mmc_device(0);
  105. if (!mmc)
  106. return;
  107. mmc_set_clock(mmc, mmc->saved_clock, false);
  108. }
  109. }
  110. #endif
  111. /*
  112. * This uninitialized global variable would normal end up in the .bss section,
  113. * but the .bss is cleared between writing and reading this variable, so move
  114. * it to the .data section.
  115. */
  116. u32 bootindex __section(".data");
  117. static struct rom_extended_boot_data bootdata __section(".data");
  118. static void store_boot_info_from_rom(void)
  119. {
  120. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  121. memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
  122. sizeof(struct rom_extended_boot_data));
  123. }
  124. void board_init_f(ulong dummy)
  125. {
  126. #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
  127. struct udevice *dev;
  128. int ret;
  129. #endif
  130. /*
  131. * Cannot delay this further as there is a chance that
  132. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  133. */
  134. store_boot_info_from_rom();
  135. /* Make all control module registers accessible */
  136. ctrl_mmr_unlock();
  137. #ifdef CONFIG_CPU_V7R
  138. disable_linefill_optimization();
  139. setup_k3_mpu_regions();
  140. #endif
  141. /* Init DM early */
  142. spl_early_init();
  143. #ifdef CONFIG_K3_LOAD_SYSFW
  144. /*
  145. * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
  146. * regardless of the result of pinctrl. Do this without probing the
  147. * device, but instead by searching the device that would request the
  148. * given sequence number if probed. The UART will be used by the system
  149. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  150. * to initialize its pin settings.
  151. */
  152. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
  153. if (!ret)
  154. pinctrl_select_state(dev, "default");
  155. /*
  156. * Load, start up, and configure system controller firmware. Provide
  157. * the U-Boot console init function to the SYSFW post-PM configuration
  158. * callback hook, effectively switching on (or over) the console
  159. * output.
  160. */
  161. k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
  162. k3_mmc_stop_clock, k3_mmc_restart_clock);
  163. /* Prepare console output */
  164. preloader_console_init();
  165. /* Disable ROM configured firewalls right after loading sysfw */
  166. #ifdef CONFIG_TI_SECURE_DEVICE
  167. remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
  168. remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
  169. remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
  170. remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
  171. remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
  172. remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
  173. remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
  174. #endif
  175. #else
  176. /* Prepare console output */
  177. preloader_console_init();
  178. #endif
  179. /* Output System Firmware version info */
  180. k3_sysfw_print_ver();
  181. /* Perform EEPROM-based board detection */
  182. if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
  183. do_board_detect();
  184. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  185. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
  186. &dev);
  187. if (ret)
  188. printf("AVS init failed: %d\n", ret);
  189. #endif
  190. #if defined(CONFIG_K3_J721E_DDRSS)
  191. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  192. if (ret)
  193. panic("DRAM init failed: %d\n", ret);
  194. #endif
  195. spl_enable_dcache();
  196. }
  197. u32 spl_mmc_boot_mode(const u32 boot_device)
  198. {
  199. switch (boot_device) {
  200. case BOOT_DEVICE_MMC1:
  201. return MMCSD_MODE_EMMCBOOT;
  202. case BOOT_DEVICE_MMC2:
  203. return MMCSD_MODE_FS;
  204. default:
  205. return MMCSD_MODE_RAW;
  206. }
  207. }
  208. static u32 __get_backup_bootmedia(u32 main_devstat)
  209. {
  210. u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  211. MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  212. switch (bkup_boot) {
  213. case BACKUP_BOOT_DEVICE_USB:
  214. return BOOT_DEVICE_DFU;
  215. case BACKUP_BOOT_DEVICE_UART:
  216. return BOOT_DEVICE_UART;
  217. case BACKUP_BOOT_DEVICE_ETHERNET:
  218. return BOOT_DEVICE_ETHERNET;
  219. case BACKUP_BOOT_DEVICE_MMC2:
  220. {
  221. u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  222. MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  223. if (port == 0x0)
  224. return BOOT_DEVICE_MMC1;
  225. return BOOT_DEVICE_MMC2;
  226. }
  227. case BACKUP_BOOT_DEVICE_SPI:
  228. return BOOT_DEVICE_SPI;
  229. case BACKUP_BOOT_DEVICE_I2C:
  230. return BOOT_DEVICE_I2C;
  231. }
  232. return BOOT_DEVICE_RAM;
  233. }
  234. static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
  235. {
  236. u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
  237. WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
  238. bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
  239. BOOT_MODE_B_SHIFT;
  240. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  241. bootmode = BOOT_DEVICE_SPI;
  242. if (bootmode == BOOT_DEVICE_MMC2) {
  243. u32 port = (main_devstat &
  244. MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
  245. MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
  246. if (port == 0x0)
  247. bootmode = BOOT_DEVICE_MMC1;
  248. }
  249. return bootmode;
  250. }
  251. u32 spl_boot_device(void)
  252. {
  253. u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
  254. u32 main_devstat;
  255. if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
  256. printf("ERROR: MCU only boot is not yet supported\n");
  257. return BOOT_DEVICE_RAM;
  258. }
  259. /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
  260. main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  261. if (bootindex == K3_PRIMARY_BOOTMODE)
  262. return __get_primary_bootmedia(main_devstat, wkup_devstat);
  263. else
  264. return __get_backup_bootmedia(main_devstat);
  265. }
  266. #endif
  267. #ifdef CONFIG_SYS_K3_SPL_ATF
  268. #define J721E_DEV_MCU_RTI0 262
  269. #define J721E_DEV_MCU_RTI1 263
  270. #define J721E_DEV_MCU_ARMSS0_CPU0 250
  271. #define J721E_DEV_MCU_ARMSS0_CPU1 251
  272. void release_resources_for_core_shutdown(void)
  273. {
  274. struct ti_sci_handle *ti_sci;
  275. struct ti_sci_dev_ops *dev_ops;
  276. struct ti_sci_proc_ops *proc_ops;
  277. int ret;
  278. u32 i;
  279. const u32 put_device_ids[] = {
  280. J721E_DEV_MCU_RTI0,
  281. J721E_DEV_MCU_RTI1,
  282. };
  283. ti_sci = get_ti_sci_handle();
  284. dev_ops = &ti_sci->ops.dev_ops;
  285. proc_ops = &ti_sci->ops.proc_ops;
  286. /* Iterate through list of devices to put (shutdown) */
  287. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  288. u32 id = put_device_ids[i];
  289. ret = dev_ops->put_device(ti_sci, id);
  290. if (ret)
  291. panic("Failed to put device %u (%d)\n", id, ret);
  292. }
  293. const u32 put_core_ids[] = {
  294. J721E_DEV_MCU_ARMSS0_CPU1,
  295. J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  296. };
  297. /* Iterate through list of cores to put (shutdown) */
  298. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  299. u32 id = put_core_ids[i];
  300. /*
  301. * Queue up the core shutdown request. Note that this call
  302. * needs to be followed up by an actual invocation of an WFE
  303. * or WFI CPU instruction.
  304. */
  305. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  306. if (ret)
  307. panic("Failed sending core %u shutdown message (%d)\n",
  308. id, ret);
  309. }
  310. }
  311. #endif
  312. #ifdef CONFIG_SYS_K3_SPL_ATF
  313. void start_non_linux_remote_cores(void)
  314. {
  315. int size = 0, ret;
  316. u32 loadaddr = 0;
  317. if (!soc_is_j721e())
  318. return;
  319. size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
  320. &loadaddr);
  321. if (size <= 0)
  322. goto err_load;
  323. /* assuming remoteproc 2 is aliased for the needed remotecore */
  324. ret = rproc_load(2, loadaddr, size);
  325. if (ret) {
  326. printf("Firmware failed to start on rproc (%d)\n", ret);
  327. goto err_load;
  328. }
  329. ret = rproc_start(2);
  330. if (ret) {
  331. printf("Firmware init failed on rproc (%d)\n", ret);
  332. goto err_load;
  333. }
  334. printf("Remoteproc 2 started successfully\n");
  335. return;
  336. err_load:
  337. rproc_reset(2);
  338. }
  339. #endif