k3-udma.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
  4. * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  5. */
  6. #define pr_fmt(fmt) "udma: " fmt
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <asm/io.h>
  10. #include <asm/bitops.h>
  11. #include <malloc.h>
  12. #include <linux/dma-mapping.h>
  13. #include <dm.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <dm/read.h>
  17. #include <dm/of_access.h>
  18. #include <dma.h>
  19. #include <dma-uclass.h>
  20. #include <linux/delay.h>
  21. #include <dt-bindings/dma/k3-udma.h>
  22. #include <linux/bitmap.h>
  23. #include <linux/err.h>
  24. #include <linux/soc/ti/k3-navss-ringacc.h>
  25. #include <linux/soc/ti/cppi5.h>
  26. #include <linux/soc/ti/ti-udma.h>
  27. #include <linux/soc/ti/ti_sci_protocol.h>
  28. #include "k3-udma-hwdef.h"
  29. #if BITS_PER_LONG == 64
  30. #define RINGACC_RING_USE_PROXY (0)
  31. #else
  32. #define RINGACC_RING_USE_PROXY (1)
  33. #endif
  34. #define K3_UDMA_MAX_RFLOWS 1024
  35. struct udma_chan;
  36. enum udma_mmr {
  37. MMR_GCFG = 0,
  38. MMR_RCHANRT,
  39. MMR_TCHANRT,
  40. MMR_LAST,
  41. };
  42. static const char * const mmr_names[] = {
  43. "gcfg", "rchanrt", "tchanrt"
  44. };
  45. struct udma_tchan {
  46. void __iomem *reg_rt;
  47. int id;
  48. struct k3_nav_ring *t_ring; /* Transmit ring */
  49. struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
  50. };
  51. struct udma_rchan {
  52. void __iomem *reg_rt;
  53. int id;
  54. struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
  55. struct k3_nav_ring *r_ring; /* Receive ring*/
  56. };
  57. struct udma_rflow {
  58. int id;
  59. };
  60. enum udma_rm_range {
  61. RM_RANGE_TCHAN = 0,
  62. RM_RANGE_RCHAN,
  63. RM_RANGE_RFLOW,
  64. RM_RANGE_LAST,
  65. };
  66. struct udma_tisci_rm {
  67. const struct ti_sci_handle *tisci;
  68. const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
  69. u32 tisci_dev_id;
  70. /* tisci information for PSI-L thread pairing/unpairing */
  71. const struct ti_sci_rm_psil_ops *tisci_psil_ops;
  72. u32 tisci_navss_dev_id;
  73. struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
  74. };
  75. struct udma_dev {
  76. struct udevice *dev;
  77. void __iomem *mmrs[MMR_LAST];
  78. struct udma_tisci_rm tisci_rm;
  79. struct k3_nav_ringacc *ringacc;
  80. u32 features;
  81. int tchan_cnt;
  82. int echan_cnt;
  83. int rchan_cnt;
  84. int rflow_cnt;
  85. unsigned long *tchan_map;
  86. unsigned long *rchan_map;
  87. unsigned long *rflow_map;
  88. unsigned long *rflow_map_reserved;
  89. struct udma_tchan *tchans;
  90. struct udma_rchan *rchans;
  91. struct udma_rflow *rflows;
  92. struct udma_chan *channels;
  93. u32 psil_base;
  94. u32 ch_count;
  95. };
  96. struct udma_chan {
  97. struct udma_dev *ud;
  98. char name[20];
  99. struct udma_tchan *tchan;
  100. struct udma_rchan *rchan;
  101. struct udma_rflow *rflow;
  102. struct ti_udma_drv_chan_cfg_data cfg_data;
  103. u32 bcnt; /* number of bytes completed since the start of the channel */
  104. bool pkt_mode; /* TR or packet */
  105. bool needs_epib; /* EPIB is needed for the communication or not */
  106. u32 psd_size; /* size of Protocol Specific Data */
  107. u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
  108. int slave_thread_id;
  109. u32 src_thread;
  110. u32 dst_thread;
  111. u32 static_tr_type;
  112. u32 id;
  113. enum dma_direction dir;
  114. struct cppi5_host_desc_t *desc_tx;
  115. u32 hdesc_size;
  116. bool in_use;
  117. void *desc_rx;
  118. u32 num_rx_bufs;
  119. u32 desc_rx_cur;
  120. };
  121. #define UDMA_CH_1000(ch) (ch * 0x1000)
  122. #define UDMA_CH_100(ch) (ch * 0x100)
  123. #define UDMA_CH_40(ch) (ch * 0x40)
  124. #ifdef PKTBUFSRX
  125. #define UDMA_RX_DESC_NUM PKTBUFSRX
  126. #else
  127. #define UDMA_RX_DESC_NUM 4
  128. #endif
  129. /* Generic register access functions */
  130. static inline u32 udma_read(void __iomem *base, int reg)
  131. {
  132. u32 v;
  133. v = __raw_readl(base + reg);
  134. pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, base + reg);
  135. return v;
  136. }
  137. static inline void udma_write(void __iomem *base, int reg, u32 val)
  138. {
  139. pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val, base + reg);
  140. __raw_writel(val, base + reg);
  141. }
  142. static inline void udma_update_bits(void __iomem *base, int reg,
  143. u32 mask, u32 val)
  144. {
  145. u32 tmp, orig;
  146. orig = udma_read(base, reg);
  147. tmp = orig & ~mask;
  148. tmp |= (val & mask);
  149. if (tmp != orig)
  150. udma_write(base, reg, tmp);
  151. }
  152. /* TCHANRT */
  153. static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
  154. {
  155. if (!tchan)
  156. return 0;
  157. return udma_read(tchan->reg_rt, reg);
  158. }
  159. static inline void udma_tchanrt_write(struct udma_tchan *tchan,
  160. int reg, u32 val)
  161. {
  162. if (!tchan)
  163. return;
  164. udma_write(tchan->reg_rt, reg, val);
  165. }
  166. /* RCHANRT */
  167. static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
  168. {
  169. if (!rchan)
  170. return 0;
  171. return udma_read(rchan->reg_rt, reg);
  172. }
  173. static inline void udma_rchanrt_write(struct udma_rchan *rchan,
  174. int reg, u32 val)
  175. {
  176. if (!rchan)
  177. return;
  178. udma_write(rchan->reg_rt, reg, val);
  179. }
  180. static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
  181. u32 dst_thread)
  182. {
  183. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  184. dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
  185. return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
  186. tisci_rm->tisci_navss_dev_id,
  187. src_thread, dst_thread);
  188. }
  189. static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
  190. u32 dst_thread)
  191. {
  192. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  193. dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
  194. return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
  195. tisci_rm->tisci_navss_dev_id,
  196. src_thread, dst_thread);
  197. }
  198. static inline char *udma_get_dir_text(enum dma_direction dir)
  199. {
  200. switch (dir) {
  201. case DMA_DEV_TO_MEM:
  202. return "DEV_TO_MEM";
  203. case DMA_MEM_TO_DEV:
  204. return "MEM_TO_DEV";
  205. case DMA_MEM_TO_MEM:
  206. return "MEM_TO_MEM";
  207. case DMA_DEV_TO_DEV:
  208. return "DEV_TO_DEV";
  209. default:
  210. break;
  211. }
  212. return "invalid";
  213. }
  214. static inline bool udma_is_chan_running(struct udma_chan *uc)
  215. {
  216. u32 trt_ctl = 0;
  217. u32 rrt_ctl = 0;
  218. switch (uc->dir) {
  219. case DMA_DEV_TO_MEM:
  220. rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  221. pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
  222. __func__, rrt_ctl,
  223. udma_rchanrt_read(uc->rchan,
  224. UDMA_RCHAN_RT_PEER_RT_EN_REG));
  225. break;
  226. case DMA_MEM_TO_DEV:
  227. trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  228. pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
  229. __func__, trt_ctl,
  230. udma_tchanrt_read(uc->tchan,
  231. UDMA_TCHAN_RT_PEER_RT_EN_REG));
  232. break;
  233. case DMA_MEM_TO_MEM:
  234. trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  235. rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  236. break;
  237. default:
  238. break;
  239. }
  240. if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
  241. return true;
  242. return false;
  243. }
  244. static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
  245. {
  246. struct k3_nav_ring *ring = NULL;
  247. int ret = -ENOENT;
  248. switch (uc->dir) {
  249. case DMA_DEV_TO_MEM:
  250. ring = uc->rchan->r_ring;
  251. break;
  252. case DMA_MEM_TO_DEV:
  253. ring = uc->tchan->tc_ring;
  254. break;
  255. case DMA_MEM_TO_MEM:
  256. ring = uc->tchan->tc_ring;
  257. break;
  258. default:
  259. break;
  260. }
  261. if (ring && k3_nav_ringacc_ring_get_occ(ring))
  262. ret = k3_nav_ringacc_ring_pop(ring, addr);
  263. return ret;
  264. }
  265. static void udma_reset_rings(struct udma_chan *uc)
  266. {
  267. struct k3_nav_ring *ring1 = NULL;
  268. struct k3_nav_ring *ring2 = NULL;
  269. switch (uc->dir) {
  270. case DMA_DEV_TO_MEM:
  271. ring1 = uc->rchan->fd_ring;
  272. ring2 = uc->rchan->r_ring;
  273. break;
  274. case DMA_MEM_TO_DEV:
  275. ring1 = uc->tchan->t_ring;
  276. ring2 = uc->tchan->tc_ring;
  277. break;
  278. case DMA_MEM_TO_MEM:
  279. ring1 = uc->tchan->t_ring;
  280. ring2 = uc->tchan->tc_ring;
  281. break;
  282. default:
  283. break;
  284. }
  285. if (ring1)
  286. k3_nav_ringacc_ring_reset_dma(ring1, 0);
  287. if (ring2)
  288. k3_nav_ringacc_ring_reset(ring2);
  289. }
  290. static void udma_reset_counters(struct udma_chan *uc)
  291. {
  292. u32 val;
  293. if (uc->tchan) {
  294. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
  295. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
  296. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
  297. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
  298. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
  299. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
  300. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
  301. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
  302. }
  303. if (uc->rchan) {
  304. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
  305. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
  306. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
  307. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
  308. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
  309. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
  310. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
  311. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
  312. }
  313. uc->bcnt = 0;
  314. }
  315. static inline int udma_stop_hard(struct udma_chan *uc)
  316. {
  317. pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
  318. switch (uc->dir) {
  319. case DMA_DEV_TO_MEM:
  320. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
  321. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  322. break;
  323. case DMA_MEM_TO_DEV:
  324. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  325. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
  326. break;
  327. case DMA_MEM_TO_MEM:
  328. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  329. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  330. break;
  331. default:
  332. return -EINVAL;
  333. }
  334. return 0;
  335. }
  336. static int udma_start(struct udma_chan *uc)
  337. {
  338. /* Channel is already running, no need to proceed further */
  339. if (udma_is_chan_running(uc))
  340. goto out;
  341. pr_debug("%s: chan:%d dir:%s (static_tr_type: %d)\n",
  342. __func__, uc->id, udma_get_dir_text(uc->dir),
  343. uc->static_tr_type);
  344. /* Make sure that we clear the teardown bit, if it is set */
  345. udma_stop_hard(uc);
  346. /* Reset all counters */
  347. udma_reset_counters(uc);
  348. switch (uc->dir) {
  349. case DMA_DEV_TO_MEM:
  350. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
  351. UDMA_CHAN_RT_CTL_EN);
  352. /* Enable remote */
  353. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
  354. UDMA_PEER_RT_EN_ENABLE);
  355. pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
  356. __func__,
  357. udma_rchanrt_read(uc->rchan,
  358. UDMA_RCHAN_RT_CTL_REG),
  359. udma_rchanrt_read(uc->rchan,
  360. UDMA_RCHAN_RT_PEER_RT_EN_REG));
  361. break;
  362. case DMA_MEM_TO_DEV:
  363. /* Enable remote */
  364. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
  365. UDMA_PEER_RT_EN_ENABLE);
  366. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  367. UDMA_CHAN_RT_CTL_EN);
  368. pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
  369. __func__,
  370. udma_tchanrt_read(uc->tchan,
  371. UDMA_TCHAN_RT_CTL_REG),
  372. udma_tchanrt_read(uc->tchan,
  373. UDMA_TCHAN_RT_PEER_RT_EN_REG));
  374. break;
  375. case DMA_MEM_TO_MEM:
  376. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
  377. UDMA_CHAN_RT_CTL_EN);
  378. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  379. UDMA_CHAN_RT_CTL_EN);
  380. break;
  381. default:
  382. return -EINVAL;
  383. }
  384. pr_debug("%s: DONE chan:%d\n", __func__, uc->id);
  385. out:
  386. return 0;
  387. }
  388. static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
  389. {
  390. int i = 0;
  391. u32 val;
  392. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  393. UDMA_CHAN_RT_CTL_EN |
  394. UDMA_CHAN_RT_CTL_TDOWN);
  395. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  396. while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
  397. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  398. udelay(1);
  399. if (i > 1000) {
  400. printf(" %s TIMEOUT !\n", __func__);
  401. break;
  402. }
  403. i++;
  404. }
  405. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
  406. if (val & UDMA_PEER_RT_EN_ENABLE)
  407. printf("%s: peer not stopped TIMEOUT !\n", __func__);
  408. }
  409. static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
  410. {
  411. int i = 0;
  412. u32 val;
  413. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
  414. UDMA_PEER_RT_EN_ENABLE |
  415. UDMA_PEER_RT_EN_TEARDOWN);
  416. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  417. while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
  418. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  419. udelay(1);
  420. if (i > 1000) {
  421. printf("%s TIMEOUT !\n", __func__);
  422. break;
  423. }
  424. i++;
  425. }
  426. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
  427. if (val & UDMA_PEER_RT_EN_ENABLE)
  428. printf("%s: peer not stopped TIMEOUT !\n", __func__);
  429. }
  430. static inline int udma_stop(struct udma_chan *uc)
  431. {
  432. pr_debug("%s: chan:%d dir:%s\n",
  433. __func__, uc->id, udma_get_dir_text(uc->dir));
  434. udma_reset_counters(uc);
  435. switch (uc->dir) {
  436. case DMA_DEV_TO_MEM:
  437. udma_stop_dev2mem(uc, true);
  438. break;
  439. case DMA_MEM_TO_DEV:
  440. udma_stop_mem2dev(uc, true);
  441. break;
  442. case DMA_MEM_TO_MEM:
  443. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  444. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  445. break;
  446. default:
  447. return -EINVAL;
  448. }
  449. return 0;
  450. }
  451. static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
  452. {
  453. int i = 1;
  454. while (udma_pop_from_ring(uc, paddr)) {
  455. udelay(1);
  456. if (!(i % 1000000))
  457. printf(".");
  458. i++;
  459. }
  460. }
  461. static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
  462. {
  463. DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
  464. if (id >= 0) {
  465. if (test_bit(id, ud->rflow_map)) {
  466. dev_err(ud->dev, "rflow%d is in use\n", id);
  467. return ERR_PTR(-ENOENT);
  468. }
  469. } else {
  470. bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
  471. ud->rflow_cnt);
  472. id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
  473. if (id >= ud->rflow_cnt)
  474. return ERR_PTR(-ENOENT);
  475. }
  476. __set_bit(id, ud->rflow_map);
  477. return &ud->rflows[id];
  478. }
  479. #define UDMA_RESERVE_RESOURCE(res) \
  480. static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
  481. int id) \
  482. { \
  483. if (id >= 0) { \
  484. if (test_bit(id, ud->res##_map)) { \
  485. dev_err(ud->dev, "res##%d is in use\n", id); \
  486. return ERR_PTR(-ENOENT); \
  487. } \
  488. } else { \
  489. id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
  490. if (id == ud->res##_cnt) { \
  491. return ERR_PTR(-ENOENT); \
  492. } \
  493. } \
  494. \
  495. __set_bit(id, ud->res##_map); \
  496. return &ud->res##s[id]; \
  497. }
  498. UDMA_RESERVE_RESOURCE(tchan);
  499. UDMA_RESERVE_RESOURCE(rchan);
  500. static int udma_get_tchan(struct udma_chan *uc)
  501. {
  502. struct udma_dev *ud = uc->ud;
  503. if (uc->tchan) {
  504. dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
  505. uc->id, uc->tchan->id);
  506. return 0;
  507. }
  508. uc->tchan = __udma_reserve_tchan(ud, -1);
  509. if (IS_ERR(uc->tchan))
  510. return PTR_ERR(uc->tchan);
  511. pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
  512. return 0;
  513. }
  514. static int udma_get_rchan(struct udma_chan *uc)
  515. {
  516. struct udma_dev *ud = uc->ud;
  517. if (uc->rchan) {
  518. dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
  519. uc->id, uc->rchan->id);
  520. return 0;
  521. }
  522. uc->rchan = __udma_reserve_rchan(ud, -1);
  523. if (IS_ERR(uc->rchan))
  524. return PTR_ERR(uc->rchan);
  525. pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
  526. return 0;
  527. }
  528. static int udma_get_chan_pair(struct udma_chan *uc)
  529. {
  530. struct udma_dev *ud = uc->ud;
  531. int chan_id, end;
  532. if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
  533. dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
  534. uc->id, uc->tchan->id);
  535. return 0;
  536. }
  537. if (uc->tchan) {
  538. dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
  539. uc->id, uc->tchan->id);
  540. return -EBUSY;
  541. } else if (uc->rchan) {
  542. dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
  543. uc->id, uc->rchan->id);
  544. return -EBUSY;
  545. }
  546. /* Can be optimized, but let's have it like this for now */
  547. end = min(ud->tchan_cnt, ud->rchan_cnt);
  548. for (chan_id = 0; chan_id < end; chan_id++) {
  549. if (!test_bit(chan_id, ud->tchan_map) &&
  550. !test_bit(chan_id, ud->rchan_map))
  551. break;
  552. }
  553. if (chan_id == end)
  554. return -ENOENT;
  555. __set_bit(chan_id, ud->tchan_map);
  556. __set_bit(chan_id, ud->rchan_map);
  557. uc->tchan = &ud->tchans[chan_id];
  558. uc->rchan = &ud->rchans[chan_id];
  559. pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
  560. return 0;
  561. }
  562. static int udma_get_rflow(struct udma_chan *uc, int flow_id)
  563. {
  564. struct udma_dev *ud = uc->ud;
  565. if (uc->rflow) {
  566. dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
  567. uc->id, uc->rflow->id);
  568. return 0;
  569. }
  570. if (!uc->rchan)
  571. dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
  572. uc->rflow = __udma_reserve_rflow(ud, flow_id);
  573. if (IS_ERR(uc->rflow))
  574. return PTR_ERR(uc->rflow);
  575. pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
  576. return 0;
  577. }
  578. static void udma_put_rchan(struct udma_chan *uc)
  579. {
  580. struct udma_dev *ud = uc->ud;
  581. if (uc->rchan) {
  582. dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
  583. uc->rchan->id);
  584. __clear_bit(uc->rchan->id, ud->rchan_map);
  585. uc->rchan = NULL;
  586. }
  587. }
  588. static void udma_put_tchan(struct udma_chan *uc)
  589. {
  590. struct udma_dev *ud = uc->ud;
  591. if (uc->tchan) {
  592. dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
  593. uc->tchan->id);
  594. __clear_bit(uc->tchan->id, ud->tchan_map);
  595. uc->tchan = NULL;
  596. }
  597. }
  598. static void udma_put_rflow(struct udma_chan *uc)
  599. {
  600. struct udma_dev *ud = uc->ud;
  601. if (uc->rflow) {
  602. dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
  603. uc->rflow->id);
  604. __clear_bit(uc->rflow->id, ud->rflow_map);
  605. uc->rflow = NULL;
  606. }
  607. }
  608. static void udma_free_tx_resources(struct udma_chan *uc)
  609. {
  610. if (!uc->tchan)
  611. return;
  612. k3_nav_ringacc_ring_free(uc->tchan->t_ring);
  613. k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
  614. uc->tchan->t_ring = NULL;
  615. uc->tchan->tc_ring = NULL;
  616. udma_put_tchan(uc);
  617. }
  618. static int udma_alloc_tx_resources(struct udma_chan *uc)
  619. {
  620. struct k3_nav_ring_cfg ring_cfg;
  621. struct udma_dev *ud = uc->ud;
  622. int ret;
  623. ret = udma_get_tchan(uc);
  624. if (ret)
  625. return ret;
  626. uc->tchan->t_ring = k3_nav_ringacc_request_ring(
  627. ud->ringacc, uc->tchan->id,
  628. RINGACC_RING_USE_PROXY);
  629. if (!uc->tchan->t_ring) {
  630. ret = -EBUSY;
  631. goto err_tx_ring;
  632. }
  633. uc->tchan->tc_ring = k3_nav_ringacc_request_ring(
  634. ud->ringacc, -1, RINGACC_RING_USE_PROXY);
  635. if (!uc->tchan->tc_ring) {
  636. ret = -EBUSY;
  637. goto err_txc_ring;
  638. }
  639. memset(&ring_cfg, 0, sizeof(ring_cfg));
  640. ring_cfg.size = 16;
  641. ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
  642. ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
  643. ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
  644. ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
  645. if (ret)
  646. goto err_ringcfg;
  647. return 0;
  648. err_ringcfg:
  649. k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
  650. uc->tchan->tc_ring = NULL;
  651. err_txc_ring:
  652. k3_nav_ringacc_ring_free(uc->tchan->t_ring);
  653. uc->tchan->t_ring = NULL;
  654. err_tx_ring:
  655. udma_put_tchan(uc);
  656. return ret;
  657. }
  658. static void udma_free_rx_resources(struct udma_chan *uc)
  659. {
  660. if (!uc->rchan)
  661. return;
  662. k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
  663. k3_nav_ringacc_ring_free(uc->rchan->r_ring);
  664. uc->rchan->fd_ring = NULL;
  665. uc->rchan->r_ring = NULL;
  666. udma_put_rflow(uc);
  667. udma_put_rchan(uc);
  668. }
  669. static int udma_alloc_rx_resources(struct udma_chan *uc)
  670. {
  671. struct k3_nav_ring_cfg ring_cfg;
  672. struct udma_dev *ud = uc->ud;
  673. int fd_ring_id;
  674. int ret;
  675. ret = udma_get_rchan(uc);
  676. if (ret)
  677. return ret;
  678. /* For MEM_TO_MEM we don't need rflow or rings */
  679. if (uc->dir == DMA_MEM_TO_MEM)
  680. return 0;
  681. ret = udma_get_rflow(uc, uc->rchan->id);
  682. if (ret) {
  683. ret = -EBUSY;
  684. goto err_rflow;
  685. }
  686. fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
  687. uc->rchan->fd_ring = k3_nav_ringacc_request_ring(
  688. ud->ringacc, fd_ring_id,
  689. RINGACC_RING_USE_PROXY);
  690. if (!uc->rchan->fd_ring) {
  691. ret = -EBUSY;
  692. goto err_rx_ring;
  693. }
  694. uc->rchan->r_ring = k3_nav_ringacc_request_ring(
  695. ud->ringacc, -1, RINGACC_RING_USE_PROXY);
  696. if (!uc->rchan->r_ring) {
  697. ret = -EBUSY;
  698. goto err_rxc_ring;
  699. }
  700. memset(&ring_cfg, 0, sizeof(ring_cfg));
  701. ring_cfg.size = 16;
  702. ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
  703. ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
  704. ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg);
  705. ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
  706. if (ret)
  707. goto err_ringcfg;
  708. return 0;
  709. err_ringcfg:
  710. k3_nav_ringacc_ring_free(uc->rchan->r_ring);
  711. uc->rchan->r_ring = NULL;
  712. err_rxc_ring:
  713. k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
  714. uc->rchan->fd_ring = NULL;
  715. err_rx_ring:
  716. udma_put_rflow(uc);
  717. err_rflow:
  718. udma_put_rchan(uc);
  719. return ret;
  720. }
  721. static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
  722. {
  723. struct udma_dev *ud = uc->ud;
  724. int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  725. struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
  726. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  727. u32 mode;
  728. int ret;
  729. if (uc->pkt_mode)
  730. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
  731. else
  732. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
  733. req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
  734. TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
  735. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
  736. req.nav_id = tisci_rm->tisci_dev_id;
  737. req.index = uc->tchan->id;
  738. req.tx_chan_type = mode;
  739. if (uc->dir == DMA_MEM_TO_MEM)
  740. req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
  741. else
  742. req.tx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
  743. uc->psd_size,
  744. 0) >> 2;
  745. req.txcq_qnum = tc_ring;
  746. ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
  747. if (ret)
  748. dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
  749. return ret;
  750. }
  751. static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
  752. {
  753. struct udma_dev *ud = uc->ud;
  754. int fd_ring = k3_nav_ringacc_get_ring_id(uc->rchan->fd_ring);
  755. int rx_ring = k3_nav_ringacc_get_ring_id(uc->rchan->r_ring);
  756. int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  757. struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
  758. struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
  759. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  760. u32 mode;
  761. int ret;
  762. if (uc->pkt_mode)
  763. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
  764. else
  765. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
  766. req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
  767. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
  768. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
  769. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
  770. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
  771. req.nav_id = tisci_rm->tisci_dev_id;
  772. req.index = uc->rchan->id;
  773. req.rx_chan_type = mode;
  774. if (uc->dir == DMA_MEM_TO_MEM) {
  775. req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
  776. req.rxcq_qnum = tc_ring;
  777. } else {
  778. req.rx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
  779. uc->psd_size,
  780. 0) >> 2;
  781. req.rxcq_qnum = rx_ring;
  782. }
  783. if (uc->rflow->id != uc->rchan->id && uc->dir != DMA_MEM_TO_MEM) {
  784. req.flowid_start = uc->rflow->id;
  785. req.flowid_cnt = 1;
  786. }
  787. ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
  788. if (ret) {
  789. dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
  790. uc->rchan->id, ret);
  791. return ret;
  792. }
  793. if (uc->dir == DMA_MEM_TO_MEM)
  794. return ret;
  795. flow_req.valid_params =
  796. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
  797. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
  798. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
  799. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
  800. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
  801. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
  802. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
  803. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
  804. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
  805. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
  806. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
  807. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
  808. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
  809. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
  810. flow_req.nav_id = tisci_rm->tisci_dev_id;
  811. flow_req.flow_index = uc->rflow->id;
  812. if (uc->needs_epib)
  813. flow_req.rx_einfo_present = 1;
  814. else
  815. flow_req.rx_einfo_present = 0;
  816. if (uc->psd_size)
  817. flow_req.rx_psinfo_present = 1;
  818. else
  819. flow_req.rx_psinfo_present = 0;
  820. flow_req.rx_error_handling = 0;
  821. flow_req.rx_desc_type = 0;
  822. flow_req.rx_dest_qnum = rx_ring;
  823. flow_req.rx_src_tag_hi_sel = 2;
  824. flow_req.rx_src_tag_lo_sel = 4;
  825. flow_req.rx_dest_tag_hi_sel = 5;
  826. flow_req.rx_dest_tag_lo_sel = 4;
  827. flow_req.rx_fdq0_sz0_qnum = fd_ring;
  828. flow_req.rx_fdq1_qnum = fd_ring;
  829. flow_req.rx_fdq2_qnum = fd_ring;
  830. flow_req.rx_fdq3_qnum = fd_ring;
  831. flow_req.rx_ps_location = 0;
  832. ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
  833. &flow_req);
  834. if (ret)
  835. dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
  836. uc->rchan->id, uc->rflow->id, ret);
  837. return ret;
  838. }
  839. static int udma_alloc_chan_resources(struct udma_chan *uc)
  840. {
  841. struct udma_dev *ud = uc->ud;
  842. int ret;
  843. pr_debug("%s: chan:%d as %s\n",
  844. __func__, uc->id, udma_get_dir_text(uc->dir));
  845. switch (uc->dir) {
  846. case DMA_MEM_TO_MEM:
  847. /* Non synchronized - mem to mem type of transfer */
  848. ret = udma_get_chan_pair(uc);
  849. if (ret)
  850. return ret;
  851. ret = udma_alloc_tx_resources(uc);
  852. if (ret)
  853. goto err_free_res;
  854. ret = udma_alloc_rx_resources(uc);
  855. if (ret)
  856. goto err_free_res;
  857. uc->src_thread = ud->psil_base + uc->tchan->id;
  858. uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
  859. break;
  860. case DMA_MEM_TO_DEV:
  861. /* Slave transfer synchronized - mem to dev (TX) trasnfer */
  862. ret = udma_alloc_tx_resources(uc);
  863. if (ret)
  864. goto err_free_res;
  865. uc->src_thread = ud->psil_base + uc->tchan->id;
  866. uc->dst_thread = uc->slave_thread_id;
  867. if (!(uc->dst_thread & 0x8000))
  868. uc->dst_thread |= 0x8000;
  869. break;
  870. case DMA_DEV_TO_MEM:
  871. /* Slave transfer synchronized - dev to mem (RX) trasnfer */
  872. ret = udma_alloc_rx_resources(uc);
  873. if (ret)
  874. goto err_free_res;
  875. uc->src_thread = uc->slave_thread_id;
  876. uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
  877. break;
  878. default:
  879. /* Can not happen */
  880. pr_debug("%s: chan:%d invalid direction (%u)\n",
  881. __func__, uc->id, uc->dir);
  882. return -EINVAL;
  883. }
  884. /* We have channel indexes and rings */
  885. if (uc->dir == DMA_MEM_TO_MEM) {
  886. ret = udma_alloc_tchan_sci_req(uc);
  887. if (ret)
  888. goto err_free_res;
  889. ret = udma_alloc_rchan_sci_req(uc);
  890. if (ret)
  891. goto err_free_res;
  892. } else {
  893. /* Slave transfer */
  894. if (uc->dir == DMA_MEM_TO_DEV) {
  895. ret = udma_alloc_tchan_sci_req(uc);
  896. if (ret)
  897. goto err_free_res;
  898. } else {
  899. ret = udma_alloc_rchan_sci_req(uc);
  900. if (ret)
  901. goto err_free_res;
  902. }
  903. }
  904. if (udma_is_chan_running(uc)) {
  905. dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
  906. udma_stop(uc);
  907. if (udma_is_chan_running(uc)) {
  908. dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
  909. goto err_free_res;
  910. }
  911. }
  912. /* PSI-L pairing */
  913. ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
  914. if (ret) {
  915. dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
  916. goto err_free_res;
  917. }
  918. return 0;
  919. err_free_res:
  920. udma_free_tx_resources(uc);
  921. udma_free_rx_resources(uc);
  922. uc->slave_thread_id = -1;
  923. return ret;
  924. }
  925. static void udma_free_chan_resources(struct udma_chan *uc)
  926. {
  927. /* Some configuration to UDMA-P channel: disable, reset, whatever */
  928. /* Release PSI-L pairing */
  929. udma_navss_psil_unpair(uc->ud, uc->src_thread, uc->dst_thread);
  930. /* Reset the rings for a new start */
  931. udma_reset_rings(uc);
  932. udma_free_tx_resources(uc);
  933. udma_free_rx_resources(uc);
  934. uc->slave_thread_id = -1;
  935. uc->dir = DMA_MEM_TO_MEM;
  936. }
  937. static int udma_get_mmrs(struct udevice *dev)
  938. {
  939. struct udma_dev *ud = dev_get_priv(dev);
  940. int i;
  941. for (i = 0; i < MMR_LAST; i++) {
  942. ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
  943. mmr_names[i]);
  944. if (!ud->mmrs[i])
  945. return -EINVAL;
  946. }
  947. return 0;
  948. }
  949. static int udma_setup_resources(struct udma_dev *ud)
  950. {
  951. struct udevice *dev = ud->dev;
  952. int ch_count, i;
  953. u32 cap2, cap3;
  954. struct ti_sci_resource_desc *rm_desc;
  955. struct ti_sci_resource *rm_res;
  956. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  957. static const char * const range_names[] = { "ti,sci-rm-range-tchan",
  958. "ti,sci-rm-range-rchan",
  959. "ti,sci-rm-range-rflow" };
  960. cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
  961. cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
  962. ud->rflow_cnt = cap3 & 0x3fff;
  963. ud->tchan_cnt = cap2 & 0x1ff;
  964. ud->echan_cnt = (cap2 >> 9) & 0x1ff;
  965. ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
  966. ch_count = ud->tchan_cnt + ud->rchan_cnt;
  967. ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
  968. sizeof(unsigned long), GFP_KERNEL);
  969. ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
  970. GFP_KERNEL);
  971. ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
  972. sizeof(unsigned long), GFP_KERNEL);
  973. ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
  974. GFP_KERNEL);
  975. ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
  976. sizeof(unsigned long), GFP_KERNEL);
  977. ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
  978. sizeof(unsigned long),
  979. GFP_KERNEL);
  980. ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
  981. GFP_KERNEL);
  982. if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
  983. !ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
  984. !ud->rflows)
  985. return -ENOMEM;
  986. /*
  987. * RX flows with the same Ids as RX channels are reserved to be used
  988. * as default flows if remote HW can't generate flow_ids. Those
  989. * RX flows can be requested only explicitly by id.
  990. */
  991. bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
  992. /* Get resource ranges from tisci */
  993. for (i = 0; i < RM_RANGE_LAST; i++)
  994. tisci_rm->rm_ranges[i] =
  995. devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
  996. tisci_rm->tisci_dev_id,
  997. (char *)range_names[i]);
  998. /* tchan ranges */
  999. rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
  1000. if (IS_ERR(rm_res)) {
  1001. bitmap_zero(ud->tchan_map, ud->tchan_cnt);
  1002. } else {
  1003. bitmap_fill(ud->tchan_map, ud->tchan_cnt);
  1004. for (i = 0; i < rm_res->sets; i++) {
  1005. rm_desc = &rm_res->desc[i];
  1006. bitmap_clear(ud->tchan_map, rm_desc->start,
  1007. rm_desc->num);
  1008. }
  1009. }
  1010. /* rchan and matching default flow ranges */
  1011. rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
  1012. if (IS_ERR(rm_res)) {
  1013. bitmap_zero(ud->rchan_map, ud->rchan_cnt);
  1014. bitmap_zero(ud->rflow_map, ud->rchan_cnt);
  1015. } else {
  1016. bitmap_fill(ud->rchan_map, ud->rchan_cnt);
  1017. bitmap_fill(ud->rflow_map, ud->rchan_cnt);
  1018. for (i = 0; i < rm_res->sets; i++) {
  1019. rm_desc = &rm_res->desc[i];
  1020. bitmap_clear(ud->rchan_map, rm_desc->start,
  1021. rm_desc->num);
  1022. bitmap_clear(ud->rflow_map, rm_desc->start,
  1023. rm_desc->num);
  1024. }
  1025. }
  1026. /* GP rflow ranges */
  1027. rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
  1028. if (IS_ERR(rm_res)) {
  1029. bitmap_clear(ud->rflow_map, ud->rchan_cnt,
  1030. ud->rflow_cnt - ud->rchan_cnt);
  1031. } else {
  1032. bitmap_set(ud->rflow_map, ud->rchan_cnt,
  1033. ud->rflow_cnt - ud->rchan_cnt);
  1034. for (i = 0; i < rm_res->sets; i++) {
  1035. rm_desc = &rm_res->desc[i];
  1036. bitmap_clear(ud->rflow_map, rm_desc->start,
  1037. rm_desc->num);
  1038. }
  1039. }
  1040. ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
  1041. ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
  1042. if (!ch_count)
  1043. return -ENODEV;
  1044. ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
  1045. GFP_KERNEL);
  1046. if (!ud->channels)
  1047. return -ENOMEM;
  1048. dev_info(dev,
  1049. "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
  1050. ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
  1051. ud->rflow_cnt);
  1052. return ch_count;
  1053. }
  1054. static int udma_probe(struct udevice *dev)
  1055. {
  1056. struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  1057. struct udma_dev *ud = dev_get_priv(dev);
  1058. int i, ret;
  1059. struct udevice *tmp;
  1060. struct udevice *tisci_dev = NULL;
  1061. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1062. ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
  1063. ret = udma_get_mmrs(dev);
  1064. if (ret)
  1065. return ret;
  1066. ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
  1067. "ti,ringacc", &tmp);
  1068. ud->ringacc = dev_get_priv(tmp);
  1069. if (IS_ERR(ud->ringacc))
  1070. return PTR_ERR(ud->ringacc);
  1071. ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0);
  1072. if (!ud->psil_base) {
  1073. dev_info(dev,
  1074. "Missing ti,psil-base property, using %d.\n", ret);
  1075. return -EINVAL;
  1076. }
  1077. ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
  1078. "ti,sci", &tisci_dev);
  1079. if (ret) {
  1080. debug("Failed to get TISCI phandle (%d)\n", ret);
  1081. tisci_rm->tisci = NULL;
  1082. return -EINVAL;
  1083. }
  1084. tisci_rm->tisci = (struct ti_sci_handle *)
  1085. (ti_sci_get_handle_from_sysfw(tisci_dev));
  1086. tisci_rm->tisci_dev_id = -1;
  1087. ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
  1088. if (ret) {
  1089. dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
  1090. return ret;
  1091. }
  1092. tisci_rm->tisci_navss_dev_id = -1;
  1093. ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
  1094. &tisci_rm->tisci_navss_dev_id);
  1095. if (ret) {
  1096. dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
  1097. return ret;
  1098. }
  1099. tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
  1100. tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
  1101. ud->dev = dev;
  1102. ud->ch_count = udma_setup_resources(ud);
  1103. if (ud->ch_count <= 0)
  1104. return ud->ch_count;
  1105. dev_info(dev,
  1106. "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
  1107. ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
  1108. tisci_rm->tisci_dev_id);
  1109. dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
  1110. for (i = 0; i < ud->tchan_cnt; i++) {
  1111. struct udma_tchan *tchan = &ud->tchans[i];
  1112. tchan->id = i;
  1113. tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
  1114. }
  1115. for (i = 0; i < ud->rchan_cnt; i++) {
  1116. struct udma_rchan *rchan = &ud->rchans[i];
  1117. rchan->id = i;
  1118. rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
  1119. }
  1120. for (i = 0; i < ud->rflow_cnt; i++) {
  1121. struct udma_rflow *rflow = &ud->rflows[i];
  1122. rflow->id = i;
  1123. }
  1124. for (i = 0; i < ud->ch_count; i++) {
  1125. struct udma_chan *uc = &ud->channels[i];
  1126. uc->ud = ud;
  1127. uc->id = i;
  1128. uc->slave_thread_id = -1;
  1129. uc->tchan = NULL;
  1130. uc->rchan = NULL;
  1131. uc->dir = DMA_MEM_TO_MEM;
  1132. sprintf(uc->name, "UDMA chan%d\n", i);
  1133. if (!i)
  1134. uc->in_use = true;
  1135. }
  1136. pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  1137. udma_read(ud->mmrs[MMR_GCFG], 0),
  1138. udma_read(ud->mmrs[MMR_GCFG], 0x20),
  1139. udma_read(ud->mmrs[MMR_GCFG], 0x24),
  1140. udma_read(ud->mmrs[MMR_GCFG], 0x28),
  1141. udma_read(ud->mmrs[MMR_GCFG], 0x2c));
  1142. uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
  1143. return ret;
  1144. }
  1145. static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
  1146. {
  1147. u64 addr = 0;
  1148. memcpy(&addr, &elem, sizeof(elem));
  1149. return k3_nav_ringacc_ring_push(ring, &addr);
  1150. }
  1151. static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
  1152. dma_addr_t src, size_t len)
  1153. {
  1154. u32 tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  1155. struct cppi5_tr_type15_t *tr_req;
  1156. int num_tr;
  1157. size_t tr_size = sizeof(struct cppi5_tr_type15_t);
  1158. u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
  1159. unsigned long dummy;
  1160. void *tr_desc;
  1161. size_t desc_size;
  1162. if (len < SZ_64K) {
  1163. num_tr = 1;
  1164. tr0_cnt0 = len;
  1165. tr0_cnt1 = 1;
  1166. } else {
  1167. unsigned long align_to = __ffs(src | dest);
  1168. if (align_to > 3)
  1169. align_to = 3;
  1170. /*
  1171. * Keep simple: tr0: SZ_64K-alignment blocks,
  1172. * tr1: the remaining
  1173. */
  1174. num_tr = 2;
  1175. tr0_cnt0 = (SZ_64K - BIT(align_to));
  1176. if (len / tr0_cnt0 >= SZ_64K) {
  1177. dev_err(uc->ud->dev, "size %zu is not supported\n",
  1178. len);
  1179. return NULL;
  1180. }
  1181. tr0_cnt1 = len / tr0_cnt0;
  1182. tr1_cnt0 = len % tr0_cnt0;
  1183. }
  1184. desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
  1185. tr_desc = dma_alloc_coherent(desc_size, &dummy);
  1186. if (!tr_desc)
  1187. return NULL;
  1188. memset(tr_desc, 0, desc_size);
  1189. cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
  1190. cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
  1191. cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
  1192. tr_req = tr_desc + tr_size;
  1193. cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
  1194. CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
  1195. cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
  1196. tr_req[0].addr = src;
  1197. tr_req[0].icnt0 = tr0_cnt0;
  1198. tr_req[0].icnt1 = tr0_cnt1;
  1199. tr_req[0].icnt2 = 1;
  1200. tr_req[0].icnt3 = 1;
  1201. tr_req[0].dim1 = tr0_cnt0;
  1202. tr_req[0].daddr = dest;
  1203. tr_req[0].dicnt0 = tr0_cnt0;
  1204. tr_req[0].dicnt1 = tr0_cnt1;
  1205. tr_req[0].dicnt2 = 1;
  1206. tr_req[0].dicnt3 = 1;
  1207. tr_req[0].ddim1 = tr0_cnt0;
  1208. if (num_tr == 2) {
  1209. cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
  1210. CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
  1211. cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
  1212. tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
  1213. tr_req[1].icnt0 = tr1_cnt0;
  1214. tr_req[1].icnt1 = 1;
  1215. tr_req[1].icnt2 = 1;
  1216. tr_req[1].icnt3 = 1;
  1217. tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
  1218. tr_req[1].dicnt0 = tr1_cnt0;
  1219. tr_req[1].dicnt1 = 1;
  1220. tr_req[1].dicnt2 = 1;
  1221. tr_req[1].dicnt3 = 1;
  1222. }
  1223. cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
  1224. flush_dcache_range((unsigned long)tr_desc,
  1225. ALIGN((unsigned long)tr_desc + desc_size,
  1226. ARCH_DMA_MINALIGN));
  1227. udma_push_to_ring(uc->tchan->t_ring, tr_desc);
  1228. return 0;
  1229. }
  1230. static int udma_transfer(struct udevice *dev, int direction,
  1231. void *dst, void *src, size_t len)
  1232. {
  1233. struct udma_dev *ud = dev_get_priv(dev);
  1234. /* Channel0 is reserved for memcpy */
  1235. struct udma_chan *uc = &ud->channels[0];
  1236. dma_addr_t paddr = 0;
  1237. int ret;
  1238. ret = udma_alloc_chan_resources(uc);
  1239. if (ret)
  1240. return ret;
  1241. udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
  1242. udma_start(uc);
  1243. udma_poll_completion(uc, &paddr);
  1244. udma_stop(uc);
  1245. udma_free_chan_resources(uc);
  1246. return 0;
  1247. }
  1248. static int udma_request(struct dma *dma)
  1249. {
  1250. struct udma_dev *ud = dev_get_priv(dma->dev);
  1251. struct udma_chan *uc;
  1252. unsigned long dummy;
  1253. int ret;
  1254. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1255. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1256. return -EINVAL;
  1257. }
  1258. uc = &ud->channels[dma->id];
  1259. ret = udma_alloc_chan_resources(uc);
  1260. if (ret) {
  1261. dev_err(dma->dev, "alloc dma res failed %d\n", ret);
  1262. return -EINVAL;
  1263. }
  1264. uc->hdesc_size = cppi5_hdesc_calc_size(uc->needs_epib,
  1265. uc->psd_size, 0);
  1266. uc->hdesc_size = ALIGN(uc->hdesc_size, ARCH_DMA_MINALIGN);
  1267. if (uc->dir == DMA_MEM_TO_DEV) {
  1268. uc->desc_tx = dma_alloc_coherent(uc->hdesc_size, &dummy);
  1269. memset(uc->desc_tx, 0, uc->hdesc_size);
  1270. } else {
  1271. uc->desc_rx = dma_alloc_coherent(
  1272. uc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
  1273. memset(uc->desc_rx, 0, uc->hdesc_size * UDMA_RX_DESC_NUM);
  1274. }
  1275. uc->in_use = true;
  1276. uc->desc_rx_cur = 0;
  1277. uc->num_rx_bufs = 0;
  1278. if (uc->dir == DMA_DEV_TO_MEM) {
  1279. uc->cfg_data.flow_id_base = uc->rflow->id;
  1280. uc->cfg_data.flow_id_cnt = 1;
  1281. }
  1282. return 0;
  1283. }
  1284. static int udma_rfree(struct dma *dma)
  1285. {
  1286. struct udma_dev *ud = dev_get_priv(dma->dev);
  1287. struct udma_chan *uc;
  1288. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1289. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1290. return -EINVAL;
  1291. }
  1292. uc = &ud->channels[dma->id];
  1293. if (udma_is_chan_running(uc))
  1294. udma_stop(uc);
  1295. udma_free_chan_resources(uc);
  1296. uc->in_use = false;
  1297. return 0;
  1298. }
  1299. static int udma_enable(struct dma *dma)
  1300. {
  1301. struct udma_dev *ud = dev_get_priv(dma->dev);
  1302. struct udma_chan *uc;
  1303. int ret;
  1304. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1305. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1306. return -EINVAL;
  1307. }
  1308. uc = &ud->channels[dma->id];
  1309. ret = udma_start(uc);
  1310. return ret;
  1311. }
  1312. static int udma_disable(struct dma *dma)
  1313. {
  1314. struct udma_dev *ud = dev_get_priv(dma->dev);
  1315. struct udma_chan *uc;
  1316. int ret = 0;
  1317. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1318. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1319. return -EINVAL;
  1320. }
  1321. uc = &ud->channels[dma->id];
  1322. if (udma_is_chan_running(uc))
  1323. ret = udma_stop(uc);
  1324. else
  1325. dev_err(dma->dev, "%s not running\n", __func__);
  1326. return ret;
  1327. }
  1328. static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
  1329. {
  1330. struct udma_dev *ud = dev_get_priv(dma->dev);
  1331. struct cppi5_host_desc_t *desc_tx;
  1332. dma_addr_t dma_src = (dma_addr_t)src;
  1333. struct ti_udma_drv_packet_data packet_data = { 0 };
  1334. dma_addr_t paddr;
  1335. struct udma_chan *uc;
  1336. u32 tc_ring_id;
  1337. int ret;
  1338. if (metadata)
  1339. packet_data = *((struct ti_udma_drv_packet_data *)metadata);
  1340. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1341. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1342. return -EINVAL;
  1343. }
  1344. uc = &ud->channels[dma->id];
  1345. if (uc->dir != DMA_MEM_TO_DEV)
  1346. return -EINVAL;
  1347. tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  1348. desc_tx = uc->desc_tx;
  1349. cppi5_hdesc_reset_hbdesc(desc_tx);
  1350. cppi5_hdesc_init(desc_tx,
  1351. uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
  1352. uc->psd_size);
  1353. cppi5_hdesc_set_pktlen(desc_tx, len);
  1354. cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
  1355. cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
  1356. cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
  1357. /* pass below information from caller */
  1358. cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
  1359. cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
  1360. flush_dcache_range((unsigned long)dma_src,
  1361. ALIGN((unsigned long)dma_src + len,
  1362. ARCH_DMA_MINALIGN));
  1363. flush_dcache_range((unsigned long)desc_tx,
  1364. ALIGN((unsigned long)desc_tx + uc->hdesc_size,
  1365. ARCH_DMA_MINALIGN));
  1366. ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
  1367. if (ret) {
  1368. dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
  1369. dma->id, ret);
  1370. return ret;
  1371. }
  1372. udma_poll_completion(uc, &paddr);
  1373. return 0;
  1374. }
  1375. static int udma_receive(struct dma *dma, void **dst, void *metadata)
  1376. {
  1377. struct udma_dev *ud = dev_get_priv(dma->dev);
  1378. struct cppi5_host_desc_t *desc_rx;
  1379. dma_addr_t buf_dma;
  1380. struct udma_chan *uc;
  1381. u32 buf_dma_len, pkt_len;
  1382. u32 port_id = 0;
  1383. int ret;
  1384. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1385. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1386. return -EINVAL;
  1387. }
  1388. uc = &ud->channels[dma->id];
  1389. if (uc->dir != DMA_DEV_TO_MEM)
  1390. return -EINVAL;
  1391. if (!uc->num_rx_bufs)
  1392. return -EINVAL;
  1393. ret = k3_nav_ringacc_ring_pop(uc->rchan->r_ring, &desc_rx);
  1394. if (ret && ret != -ENODATA) {
  1395. dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
  1396. return ret;
  1397. } else if (ret == -ENODATA) {
  1398. return 0;
  1399. }
  1400. /* invalidate cache data */
  1401. invalidate_dcache_range((ulong)desc_rx,
  1402. (ulong)(desc_rx + uc->hdesc_size));
  1403. cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
  1404. pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
  1405. /* invalidate cache data */
  1406. invalidate_dcache_range((ulong)buf_dma,
  1407. (ulong)(buf_dma + buf_dma_len));
  1408. cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
  1409. *dst = (void *)buf_dma;
  1410. uc->num_rx_bufs--;
  1411. return pkt_len;
  1412. }
  1413. static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
  1414. {
  1415. struct udma_dev *ud = dev_get_priv(dma->dev);
  1416. struct udma_chan *uc = &ud->channels[0];
  1417. ofnode chconf_node, slave_node;
  1418. char prop[50];
  1419. u32 val;
  1420. for (val = 0; val < ud->ch_count; val++) {
  1421. uc = &ud->channels[val];
  1422. if (!uc->in_use)
  1423. break;
  1424. }
  1425. if (val == ud->ch_count)
  1426. return -EBUSY;
  1427. uc->dir = DMA_DEV_TO_MEM;
  1428. if (args->args[2] == UDMA_DIR_TX)
  1429. uc->dir = DMA_MEM_TO_DEV;
  1430. slave_node = ofnode_get_by_phandle(args->args[0]);
  1431. if (!ofnode_valid(slave_node)) {
  1432. dev_err(ud->dev, "slave node is missing\n");
  1433. return -EINVAL;
  1434. }
  1435. snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]);
  1436. chconf_node = ofnode_find_subnode(slave_node, prop);
  1437. if (!ofnode_valid(chconf_node)) {
  1438. dev_err(ud->dev, "Channel configuration node is missing\n");
  1439. return -EINVAL;
  1440. }
  1441. if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) {
  1442. if (val == UDMA_PKT_MODE)
  1443. uc->pkt_mode = true;
  1444. }
  1445. if (!ofnode_read_u32(chconf_node, "statictr-type", &val))
  1446. uc->static_tr_type = val;
  1447. uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib");
  1448. if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val))
  1449. uc->psd_size = val;
  1450. uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size;
  1451. if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) {
  1452. dev_err(ud->dev, "ti,psil-base is missing\n");
  1453. return -EINVAL;
  1454. }
  1455. uc->slave_thread_id = val + args->args[1];
  1456. dma->id = uc->id;
  1457. pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
  1458. dma->id, uc->needs_epib,
  1459. uc->psd_size, uc->metadata_size,
  1460. uc->slave_thread_id);
  1461. return 0;
  1462. }
  1463. int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
  1464. {
  1465. struct udma_dev *ud = dev_get_priv(dma->dev);
  1466. struct cppi5_host_desc_t *desc_rx;
  1467. dma_addr_t dma_dst;
  1468. struct udma_chan *uc;
  1469. u32 desc_num;
  1470. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1471. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1472. return -EINVAL;
  1473. }
  1474. uc = &ud->channels[dma->id];
  1475. if (uc->dir != DMA_DEV_TO_MEM)
  1476. return -EINVAL;
  1477. if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
  1478. return -EINVAL;
  1479. desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
  1480. desc_rx = uc->desc_rx + (desc_num * uc->hdesc_size);
  1481. dma_dst = (dma_addr_t)dst;
  1482. cppi5_hdesc_reset_hbdesc(desc_rx);
  1483. cppi5_hdesc_init(desc_rx,
  1484. uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
  1485. uc->psd_size);
  1486. cppi5_hdesc_set_pktlen(desc_rx, size);
  1487. cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
  1488. flush_dcache_range((unsigned long)desc_rx,
  1489. ALIGN((unsigned long)desc_rx + uc->hdesc_size,
  1490. ARCH_DMA_MINALIGN));
  1491. udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
  1492. uc->num_rx_bufs++;
  1493. uc->desc_rx_cur++;
  1494. return 0;
  1495. }
  1496. static int udma_get_cfg(struct dma *dma, u32 id, void **data)
  1497. {
  1498. struct udma_dev *ud = dev_get_priv(dma->dev);
  1499. struct udma_chan *uc;
  1500. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1501. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1502. return -EINVAL;
  1503. }
  1504. switch (id) {
  1505. case TI_UDMA_CHAN_PRIV_INFO:
  1506. uc = &ud->channels[dma->id];
  1507. *data = &uc->cfg_data;
  1508. return 0;
  1509. }
  1510. return -EINVAL;
  1511. }
  1512. static const struct dma_ops udma_ops = {
  1513. .transfer = udma_transfer,
  1514. .of_xlate = udma_of_xlate,
  1515. .request = udma_request,
  1516. .rfree = udma_rfree,
  1517. .enable = udma_enable,
  1518. .disable = udma_disable,
  1519. .send = udma_send,
  1520. .receive = udma_receive,
  1521. .prepare_rcv_buf = udma_prepare_rcv_buf,
  1522. .get_cfg = udma_get_cfg,
  1523. };
  1524. static const struct udevice_id udma_ids[] = {
  1525. { .compatible = "ti,k3-navss-udmap" },
  1526. { .compatible = "ti,j721e-navss-mcu-udmap" },
  1527. { }
  1528. };
  1529. U_BOOT_DRIVER(ti_edma3) = {
  1530. .name = "ti-udma",
  1531. .id = UCLASS_DMA,
  1532. .of_match = udma_ids,
  1533. .ops = &udma_ops,
  1534. .probe = udma_probe,
  1535. .priv_auto_alloc_size = sizeof(struct udma_dev),
  1536. };