arm64-mmu.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: ARM64 MMU setup
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
  8. *
  9. */
  10. #include <common.h>
  11. #include <asm/system.h>
  12. #include <asm/armv8/mmu.h>
  13. #ifdef CONFIG_SOC_K3_AM6
  14. /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  15. #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
  16. /* ToDo: Add 64bit IO */
  17. struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
  18. {
  19. .virt = 0x0UL,
  20. .phys = 0x0UL,
  21. .size = 0x80000000UL,
  22. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  23. PTE_BLOCK_NON_SHARE |
  24. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  25. }, {
  26. .virt = 0x80000000UL,
  27. .phys = 0x80000000UL,
  28. .size = 0x20000000UL,
  29. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  30. PTE_BLOCK_INNER_SHARE
  31. }, {
  32. .virt = 0xa0000000UL,
  33. .phys = 0xa0000000UL,
  34. .size = 0x02100000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  36. PTE_BLOCK_INNER_SHARE
  37. }, {
  38. .virt = 0xa2100000UL,
  39. .phys = 0xa2100000UL,
  40. .size = 0x5df00000UL,
  41. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  42. PTE_BLOCK_INNER_SHARE
  43. }, {
  44. .virt = 0x880000000UL,
  45. .phys = 0x880000000UL,
  46. .size = 0x80000000UL,
  47. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  48. PTE_BLOCK_INNER_SHARE
  49. }, {
  50. .virt = 0x500000000UL,
  51. .phys = 0x500000000UL,
  52. .size = 0x400000000UL,
  53. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  54. PTE_BLOCK_NON_SHARE |
  55. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  56. }, {
  57. /* List terminator */
  58. 0,
  59. }
  60. };
  61. struct mm_region *mem_map = am654_mem_map;
  62. #endif /* CONFIG_SOC_K3_AM6 */
  63. #ifdef CONFIG_SOC_K3_J721E
  64. /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  65. #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
  66. /* ToDo: Add 64bit IO */
  67. struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
  68. {
  69. .virt = 0x0UL,
  70. .phys = 0x0UL,
  71. .size = 0x80000000UL,
  72. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  73. PTE_BLOCK_NON_SHARE |
  74. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  75. }, {
  76. .virt = 0x80000000UL,
  77. .phys = 0x80000000UL,
  78. .size = 0x20000000UL,
  79. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  80. PTE_BLOCK_INNER_SHARE
  81. }, {
  82. .virt = 0xa0000000UL,
  83. .phys = 0xa0000000UL,
  84. .size = 0x1bc00000UL,
  85. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  86. PTE_BLOCK_NON_SHARE
  87. }, {
  88. .virt = 0xbbc00000UL,
  89. .phys = 0xbbc00000UL,
  90. .size = 0x44400000UL,
  91. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  92. PTE_BLOCK_INNER_SHARE
  93. }, {
  94. .virt = 0x880000000UL,
  95. .phys = 0x880000000UL,
  96. .size = 0x80000000UL,
  97. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  98. PTE_BLOCK_INNER_SHARE
  99. }, {
  100. .virt = 0x500000000UL,
  101. .phys = 0x500000000UL,
  102. .size = 0x400000000UL,
  103. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  104. PTE_BLOCK_NON_SHARE |
  105. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  106. }, {
  107. .virt = 0x4d80000000UL,
  108. .phys = 0x4d80000000UL,
  109. .size = 0x0002000000UL,
  110. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  111. PTE_BLOCK_INNER_SHARE
  112. }, {
  113. /* List terminator */
  114. 0,
  115. }
  116. };
  117. struct mm_region *mem_map = j721e_mem_map;
  118. #endif /* CONFIG_SOC_K3_J721E */