am6_init.c 8.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * AM6: SoC specific initialization
  4. *
  5. * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <spl.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/sysfw-loader.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include "common.h"
  15. #include <dm.h>
  16. #include <dm/uclass-internal.h>
  17. #include <dm/pinctrl.h>
  18. #include <linux/soc/ti/ti_sci_protocol.h>
  19. #include <mmc.h>
  20. #ifdef CONFIG_SPL_BUILD
  21. #ifdef CONFIG_K3_LOAD_SYSFW
  22. #ifdef CONFIG_TI_SECURE_DEVICE
  23. struct fwl_data main_cbass_fwls[] = {
  24. { "MMCSD1_CFG", 2057, 1 },
  25. { "MMCSD0_CFG", 2058, 1 },
  26. { "USB3SS0_SLV0", 2176, 2 },
  27. { "PCIE0_SLV", 2336, 8 },
  28. { "PCIE1_SLV", 2337, 8 },
  29. { "PCIE0_CFG", 2688, 1 },
  30. { "PCIE1_CFG", 2689, 1 },
  31. }, mcu_cbass_fwls[] = {
  32. { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
  33. { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
  34. { "MCU_FSS0_S1", 1033, 8 },
  35. { "MCU_FSS0_S0", 1036, 8 },
  36. { "MCU_CPSW0", 1220, 1 },
  37. };
  38. #endif
  39. #endif
  40. static void mmr_unlock(u32 base, u32 partition)
  41. {
  42. /* Translate the base address */
  43. phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  44. /* Unlock the requested partition if locked using two-step sequence */
  45. writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  46. writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  47. }
  48. static void ctrl_mmr_unlock(void)
  49. {
  50. /* Unlock all WKUP_CTRL_MMR0 module registers */
  51. mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  52. mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  53. mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  54. mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  55. mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  56. mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  57. /* Unlock all MCU_CTRL_MMR0 module registers */
  58. mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  59. mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  60. mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  61. mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
  62. /* Unlock all CTRL_MMR0 module registers */
  63. mmr_unlock(CTRL_MMR0_BASE, 0);
  64. mmr_unlock(CTRL_MMR0_BASE, 1);
  65. mmr_unlock(CTRL_MMR0_BASE, 2);
  66. mmr_unlock(CTRL_MMR0_BASE, 3);
  67. mmr_unlock(CTRL_MMR0_BASE, 6);
  68. mmr_unlock(CTRL_MMR0_BASE, 7);
  69. }
  70. /*
  71. * This uninitialized global variable would normal end up in the .bss section,
  72. * but the .bss is cleared between writing and reading this variable, so move
  73. * it to the .data section.
  74. */
  75. u32 bootindex __attribute__((section(".data")));
  76. static void store_boot_index_from_rom(void)
  77. {
  78. bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  79. }
  80. #if defined(CONFIG_K3_LOAD_SYSFW)
  81. void k3_mmc_stop_clock(void)
  82. {
  83. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  84. struct mmc *mmc = find_mmc_device(0);
  85. if (!mmc)
  86. return;
  87. mmc->saved_clock = mmc->clock;
  88. mmc_set_clock(mmc, 0, true);
  89. }
  90. }
  91. void k3_mmc_restart_clock(void)
  92. {
  93. if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  94. struct mmc *mmc = find_mmc_device(0);
  95. if (!mmc)
  96. return;
  97. mmc_set_clock(mmc, mmc->saved_clock, false);
  98. }
  99. }
  100. #endif
  101. void board_init_f(ulong dummy)
  102. {
  103. #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
  104. struct udevice *dev;
  105. int ret;
  106. #endif
  107. /*
  108. * Cannot delay this further as there is a chance that
  109. * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
  110. */
  111. store_boot_index_from_rom();
  112. /* Make all control module registers accessible */
  113. ctrl_mmr_unlock();
  114. #ifdef CONFIG_CPU_V7R
  115. disable_linefill_optimization();
  116. setup_k3_mpu_regions();
  117. #endif
  118. /* Init DM early in-order to invoke system controller */
  119. spl_early_init();
  120. #ifdef CONFIG_K3_EARLY_CONS
  121. /*
  122. * Allow establishing an early console as required for example when
  123. * doing a UART-based boot. Note that this console may not "survive"
  124. * through a SYSFW PM-init step and will need a re-init in some way
  125. * due to changing module clock frequencies.
  126. */
  127. early_console_init();
  128. #endif
  129. #ifdef CONFIG_K3_LOAD_SYSFW
  130. /*
  131. * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
  132. * regardless of the result of pinctrl. Do this without probing the
  133. * device, but instead by searching the device that would request the
  134. * given sequence number if probed. The UART will be used by the system
  135. * firmware (SYSFW) image for various purposes and SYSFW depends on us
  136. * to initialize its pin settings.
  137. */
  138. ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
  139. if (!ret)
  140. pinctrl_select_state(dev, "default");
  141. /*
  142. * Load, start up, and configure system controller firmware while
  143. * also populating the SYSFW post-PM configuration callback hook.
  144. */
  145. k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
  146. /* Prepare console output */
  147. preloader_console_init();
  148. /* Disable ROM configured firewalls right after loading sysfw */
  149. #ifdef CONFIG_TI_SECURE_DEVICE
  150. remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
  151. remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
  152. #endif
  153. #else
  154. /* Prepare console output */
  155. preloader_console_init();
  156. #endif
  157. /* Output System Firmware version info */
  158. k3_sysfw_print_ver();
  159. /* Perform EEPROM-based board detection */
  160. do_board_detect();
  161. #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
  162. ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
  163. &dev);
  164. if (ret)
  165. printf("AVS init failed: %d\n", ret);
  166. #endif
  167. #ifdef CONFIG_K3_AM654_DDRSS
  168. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  169. if (ret)
  170. panic("DRAM init failed: %d\n", ret);
  171. #endif
  172. }
  173. u32 spl_boot_mode(const u32 boot_device)
  174. {
  175. #if defined(CONFIG_SUPPORT_EMMC_BOOT)
  176. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  177. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  178. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  179. /* eMMC boot0 mode is only supported for primary boot */
  180. if (bootindex == K3_PRIMARY_BOOTMODE &&
  181. bootmode == BOOT_DEVICE_MMC1)
  182. return MMCSD_MODE_EMMCBOOT;
  183. #endif
  184. /* Everything else use filesystem if available */
  185. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  186. return MMCSD_MODE_FS;
  187. #else
  188. return MMCSD_MODE_RAW;
  189. #endif
  190. }
  191. static u32 __get_backup_bootmedia(u32 devstat)
  192. {
  193. u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
  194. CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
  195. switch (bkup_boot) {
  196. case BACKUP_BOOT_DEVICE_USB:
  197. return BOOT_DEVICE_USB;
  198. case BACKUP_BOOT_DEVICE_UART:
  199. return BOOT_DEVICE_UART;
  200. case BACKUP_BOOT_DEVICE_ETHERNET:
  201. return BOOT_DEVICE_ETHERNET;
  202. case BACKUP_BOOT_DEVICE_MMC2:
  203. {
  204. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
  205. CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
  206. if (port == 0x0)
  207. return BOOT_DEVICE_MMC1;
  208. return BOOT_DEVICE_MMC2;
  209. }
  210. case BACKUP_BOOT_DEVICE_SPI:
  211. return BOOT_DEVICE_SPI;
  212. case BACKUP_BOOT_DEVICE_HYPERFLASH:
  213. return BOOT_DEVICE_HYPERFLASH;
  214. case BACKUP_BOOT_DEVICE_I2C:
  215. return BOOT_DEVICE_I2C;
  216. };
  217. return BOOT_DEVICE_RAM;
  218. }
  219. static u32 __get_primary_bootmedia(u32 devstat)
  220. {
  221. u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
  222. CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
  223. if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
  224. bootmode = BOOT_DEVICE_SPI;
  225. if (bootmode == BOOT_DEVICE_MMC2) {
  226. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
  227. CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
  228. if (port == 0x0)
  229. bootmode = BOOT_DEVICE_MMC1;
  230. } else if (bootmode == BOOT_DEVICE_MMC1) {
  231. u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
  232. CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
  233. if (port == 0x1)
  234. bootmode = BOOT_DEVICE_MMC2;
  235. }
  236. return bootmode;
  237. }
  238. u32 spl_boot_device(void)
  239. {
  240. u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
  241. if (bootindex == K3_PRIMARY_BOOTMODE)
  242. return __get_primary_bootmedia(devstat);
  243. else
  244. return __get_backup_bootmedia(devstat);
  245. }
  246. #endif
  247. #ifdef CONFIG_SYS_K3_SPL_ATF
  248. #define AM6_DEV_MCU_RTI0 134
  249. #define AM6_DEV_MCU_RTI1 135
  250. #define AM6_DEV_MCU_ARMSS0_CPU0 159
  251. #define AM6_DEV_MCU_ARMSS0_CPU1 245
  252. void release_resources_for_core_shutdown(void)
  253. {
  254. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  255. struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
  256. struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
  257. int ret;
  258. u32 i;
  259. const u32 put_device_ids[] = {
  260. AM6_DEV_MCU_RTI0,
  261. AM6_DEV_MCU_RTI1,
  262. };
  263. /* Iterate through list of devices to put (shutdown) */
  264. for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
  265. u32 id = put_device_ids[i];
  266. ret = dev_ops->put_device(ti_sci, id);
  267. if (ret)
  268. panic("Failed to put device %u (%d)\n", id, ret);
  269. }
  270. const u32 put_core_ids[] = {
  271. AM6_DEV_MCU_ARMSS0_CPU1,
  272. AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
  273. };
  274. /* Iterate through list of cores to put (shutdown) */
  275. for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
  276. u32 id = put_core_ids[i];
  277. /*
  278. * Queue up the core shutdown request. Note that this call
  279. * needs to be followed up by an actual invocation of an WFE
  280. * or WFI CPU instruction.
  281. */
  282. ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
  283. if (ret)
  284. panic("Failed sending core %u shutdown message (%d)\n",
  285. id, ret);
  286. }
  287. }
  288. #endif