k3-j721e-r5-common-proc-board.dts 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "k3-j721e-som-p0.dtsi"
  7. #include "k3-j721e-ddr-evm-lp4-3733.dtsi"
  8. #include "k3-j721e-ddr.dtsi"
  9. / {
  10. aliases {
  11. remoteproc0 = &sysctrler;
  12. remoteproc1 = &a72_0;
  13. remoteproc2 = &main_r5fss0_core0;
  14. remoteproc3 = &main_r5fss0_core1;
  15. };
  16. chosen {
  17. stdout-path = "serial2:115200n8";
  18. tick-timer = &timer1;
  19. };
  20. a72_0: a72@0 {
  21. compatible = "ti,am654-rproc";
  22. reg = <0x0 0x00a90000 0x0 0x10>;
  23. power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  24. <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
  25. resets = <&k3_reset 202 0>;
  26. assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
  27. assigned-clock-rates = <2000000000>, <200000000>;
  28. ti,sci = <&dmsc>;
  29. ti,sci-proc-id = <32>;
  30. ti,sci-host-id = <10>;
  31. u-boot,dm-spl;
  32. };
  33. clk_200mhz: dummy_clock_200mhz {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <200000000>;
  37. u-boot,dm-spl;
  38. };
  39. clk_19_2mhz: dummy_clock_19_2mhz {
  40. compatible = "fixed-clock";
  41. #clock-cells = <0>;
  42. clock-frequency = <19200000>;
  43. u-boot,dm-spl;
  44. };
  45. };
  46. &cbass_mcu_wakeup {
  47. mcu_secproxy: secproxy@28380000 {
  48. u-boot,dm-spl;
  49. compatible = "ti,am654-secure-proxy";
  50. reg = <0x0 0x2a380000 0x0 0x80000>,
  51. <0x0 0x2a400000 0x0 0x80000>,
  52. <0x0 0x2a480000 0x0 0x80000>;
  53. reg-names = "rt", "scfg", "target_data";
  54. #mbox-cells = <1>;
  55. };
  56. sysctrler: sysctrler {
  57. u-boot,dm-spl;
  58. compatible = "ti,am654-system-controller";
  59. mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
  60. mbox-names = "tx", "rx";
  61. };
  62. wkup_vtm0: wkup_vtm@42040000 {
  63. compatible = "ti,am654-vtm", "ti,j721e-avs";
  64. reg = <0x0 0x42040000 0x0 0x330>;
  65. power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  66. #thermal-sensor-cells = <1>;
  67. };
  68. };
  69. &cbass_main {
  70. main_esm: esm@700000 {
  71. compatible = "ti,j721e-esm";
  72. reg = <0x0 0x700000 0x0 0x1000>;
  73. ti,esm-pins = <344>, <345>;
  74. u-boot,dm-spl;
  75. };
  76. };
  77. &dmsc {
  78. mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
  79. mbox-names = "tx", "rx", "notify";
  80. ti,host-id = <4>;
  81. ti,secure-host;
  82. };
  83. &wkup_pmx0 {
  84. wkup_uart0_pins_default: wkup_uart0_pins_default {
  85. u-boot,dm-spl;
  86. pinctrl-single,pins = <
  87. J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
  88. J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
  89. >;
  90. };
  91. mcu_uart0_pins_default: mcu_uart0_pins_default {
  92. u-boot,dm-spl;
  93. pinctrl-single,pins = <
  94. J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
  95. J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
  96. J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
  97. J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
  98. >;
  99. };
  100. wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  101. pinctrl-single,pins = <
  102. J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
  103. J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
  104. >;
  105. };
  106. mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  107. pinctrl-single,pins = <
  108. J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
  109. J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
  110. J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
  111. J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
  112. J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
  113. J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
  114. J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
  115. J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
  116. J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
  117. J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
  118. J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
  119. >;
  120. };
  121. mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
  122. u-boot,dm-spl;
  123. pinctrl-single,pins = <
  124. J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
  125. J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
  126. J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
  127. J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
  128. J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
  129. J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
  130. J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
  131. J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
  132. >;
  133. };
  134. };
  135. &main_pmx0 {
  136. main_uart0_pins_default: main_uart0_pins_default {
  137. u-boot,dm-spl;
  138. pinctrl-single,pins = <
  139. J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
  140. J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
  141. J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
  142. J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
  143. >;
  144. };
  145. main_usbss0_pins_default: main_usbss0_pins_default {
  146. pinctrl-single,pins = <
  147. J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
  148. J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
  149. >;
  150. };
  151. main_mmc1_pins_default: main_mmc1_pins_default {
  152. pinctrl-single,pins = <
  153. J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
  154. J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
  155. J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
  156. J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
  157. J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
  158. J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
  159. J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
  160. J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
  161. J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
  162. >;
  163. };
  164. main_i2c0_pins_default: main-i2c0-pins-default {
  165. pinctrl-single,pins = <
  166. J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
  167. J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
  168. >;
  169. };
  170. };
  171. &wkup_uart0 {
  172. u-boot,dm-spl;
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&wkup_uart0_pins_default>;
  175. status = "okay";
  176. };
  177. &mcu_uart0 {
  178. /delete-property/ power-domains;
  179. /delete-property/ clocks;
  180. /delete-property/ clock-names;
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&mcu_uart0_pins_default>;
  183. status = "okay";
  184. clock-frequency = <48000000>;
  185. };
  186. &main_uart0 {
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&main_uart0_pins_default>;
  189. status = "okay";
  190. power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  191. };
  192. &main_sdhci0 {
  193. /delete-property/ power-domains;
  194. /delete-property/ assigned-clocks;
  195. /delete-property/ assigned-clock-parents;
  196. clock-names = "clk_xin";
  197. clocks = <&clk_200mhz>;
  198. ti,driver-strength-ohm = <50>;
  199. non-removable;
  200. bus-width = <8>;
  201. };
  202. &main_sdhci1 {
  203. /delete-property/ power-domains;
  204. /delete-property/ assigned-clocks;
  205. /delete-property/ assigned-clock-parents;
  206. pinctrl-names = "default";
  207. pinctrl-0 = <&main_mmc1_pins_default>;
  208. clock-names = "clk_xin";
  209. clocks = <&clk_200mhz>;
  210. ti,driver-strength-ohm = <50>;
  211. };
  212. &wkup_i2c0 {
  213. u-boot,dm-spl;
  214. tps659413a: tps659413a@48 {
  215. reg = <0x48>;
  216. compatible = "ti,tps659413";
  217. u-boot,dm-spl;
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&wkup_i2c0_pins_default>;
  220. clock-frequency = <400000>;
  221. regulators: regulators {
  222. u-boot,dm-spl;
  223. buck12_reg: buck12 {
  224. /*VDD_MPU*/
  225. regulator-name = "buck12";
  226. regulator-min-microvolt = <800000>;
  227. regulator-max-microvolt = <1250000>;
  228. regulator-always-on;
  229. regulator-boot-on;
  230. u-boot,dm-spl;
  231. };
  232. };
  233. };
  234. };
  235. &wkup_vtm0 {
  236. vdd-supply-2 = <&buck12_reg>;
  237. u-boot,dm-spl;
  238. };
  239. &usbss0 {
  240. /delete-property/ power-domains;
  241. /delete-property/ assigned-clocks;
  242. /delete-property/ assigned-clock-parents;
  243. clocks = <&clk_19_2mhz>;
  244. clock-names = "usb2_refclk";
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&main_usbss0_pins_default>;
  247. ti,vbus-divider;
  248. };
  249. &main_i2c0 {
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&main_i2c0_pins_default>;
  252. clock-frequency = <400000>;
  253. exp1: gpio@20 {
  254. compatible = "ti,tca6416";
  255. reg = <0x20>;
  256. gpio-controller;
  257. #gpio-cells = <2>;
  258. };
  259. exp2: gpio@22 {
  260. compatible = "ti,tca6424";
  261. reg = <0x22>;
  262. gpio-controller;
  263. #gpio-cells = <2>;
  264. };
  265. };
  266. &ospi0 {
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
  269. reg = <0x0 0x47040000 0x0 0x100>,
  270. <0x0 0x50000000 0x0 0x8000000>;
  271. flash@0{
  272. compatible = "jedec,spi-nor";
  273. reg = <0x0>;
  274. spi-tx-bus-width = <1>;
  275. spi-rx-bus-width = <8>;
  276. spi-max-frequency = <40000000>;
  277. cdns,tshsl-ns = <60>;
  278. cdns,tsd2d-ns = <60>;
  279. cdns,tchsh-ns = <60>;
  280. cdns,tslch-ns = <60>;
  281. cdns,read-delay = <0>;
  282. #address-cells = <1>;
  283. #size-cells = <1>;
  284. };
  285. };
  286. &ospi1 {
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
  289. u-boot,dm-spl;
  290. reg = <0x0 0x47050000 0x0 0x100>,
  291. <0x0 0x58000000 0x0 0x8000000>;
  292. flash@0{
  293. compatible = "jedec,spi-nor";
  294. reg = <0x0>;
  295. spi-tx-bus-width = <1>;
  296. spi-rx-bus-width = <4>;
  297. spi-max-frequency = <40000000>;
  298. cdns,tshsl-ns = <60>;
  299. cdns,tsd2d-ns = <60>;
  300. cdns,tchsh-ns = <60>;
  301. cdns,tslch-ns = <60>;
  302. cdns,read-delay = <2>;
  303. #address-cells = <1>;
  304. #size-cells = <1>;
  305. u-boot,dm-spl;
  306. };
  307. };
  308. #include "k3-j721e-common-proc-board-u-boot.dtsi"