k3-j721e-common-proc-board-u-boot.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/dma/k3-udma.h>
  6. #include <dt-bindings/net/ti-dp83867.h>
  7. / {
  8. chosen {
  9. stdout-path = "serial2:115200n8";
  10. tick-timer = &timer1;
  11. };
  12. aliases {
  13. ethernet0 = &cpsw_port1;
  14. };
  15. };
  16. &cbass_main{
  17. u-boot,dm-spl;
  18. };
  19. &cbass_mcu_wakeup {
  20. u-boot,dm-spl;
  21. timer1: timer@40400000 {
  22. compatible = "ti,omap5430-timer";
  23. reg = <0x0 0x40400000 0x0 0x80>;
  24. ti,timer-alwon;
  25. clock-frequency = <25000000>;
  26. u-boot,dm-spl;
  27. };
  28. mcu_conf: scm_conf@40f00000 {
  29. compatible = "syscon", "simple-mfd";
  30. reg = <0x0 0x40f00000 0x0 0x20000>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. ranges = <0x0 0x0 0x40f00000 0x20000>;
  34. phy_sel: cpsw-phy-sel@4040 {
  35. compatible = "ti,am654-cpsw-phy-sel";
  36. reg = <0x4040 0x4>;
  37. reg-names = "gmii-sel";
  38. };
  39. };
  40. cbass_mcu_navss: mcu_navss {
  41. compatible = "simple-bus";
  42. #address-cells = <2>;
  43. #size-cells = <2>;
  44. dma-coherent;
  45. dma-ranges;
  46. ranges;
  47. ti,sci-dev-id = <232>;
  48. u-boot,dm-spl;
  49. mcu_ringacc: ringacc@2b800000 {
  50. compatible = "ti,am654-navss-ringacc";
  51. reg = <0x0 0x2b800000 0x0 0x400000>,
  52. <0x0 0x2b000000 0x0 0x400000>,
  53. <0x0 0x28590000 0x0 0x100>,
  54. <0x0 0x2a500000 0x0 0x40000>;
  55. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  56. ti,num-rings = <286>;
  57. ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
  58. ti,sci = <&dmsc>;
  59. ti,sci-dev-id = <235>;
  60. u-boot,dm-spl;
  61. };
  62. mcu_udmap: udmap@31150000 {
  63. compatible = "ti,j721e-navss-mcu-udmap";
  64. reg = <0x0 0x285c0000 0x0 0x100>,
  65. <0x0 0x2a800000 0x0 0x40000>,
  66. <0x0 0x2aa00000 0x0 0x40000>;
  67. reg-names = "gcfg", "rchanrt", "tchanrt";
  68. #dma-cells = <3>;
  69. ti,ringacc = <&mcu_ringacc>;
  70. ti,psil-base = <0x6000>;
  71. ti,sci = <&dmsc>;
  72. ti,sci-dev-id = <236>;
  73. ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
  74. <0x0f>; /* TX_HCHAN */
  75. ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
  76. <0x0b>; /* RX_HCHAN */
  77. ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
  78. u-boot,dm-spl;
  79. };
  80. };
  81. mcu_cpsw: ethernet@046000000 {
  82. compatible = "ti,j721e-cpsw-nuss";
  83. #address-cells = <2>;
  84. #size-cells = <2>;
  85. reg = <0x0 0x46000000 0x0 0x200000>;
  86. reg-names = "cpsw_nuss";
  87. ranges;
  88. dma-coherent;
  89. clocks = <&k3_clks 18 22>;
  90. clock-names = "fck";
  91. power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
  92. ti,psil-base = <0x7000>;
  93. cpsw-phy-sel = <&phy_sel>;
  94. dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
  95. <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
  96. <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
  97. <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
  98. <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
  99. <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
  100. <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
  101. <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
  102. <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
  103. dma-names = "tx0", "tx1", "tx2", "tx3",
  104. "tx4", "tx5", "tx6", "tx7",
  105. "rx";
  106. ports {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. host: host@0 {
  110. reg = <0>;
  111. ti,label = "host";
  112. };
  113. cpsw_port1: port@1 {
  114. reg = <1>;
  115. ti,mac-only;
  116. ti,label = "port1";
  117. ti,syscon-efuse = <&mcu_conf 0x200>;
  118. };
  119. };
  120. davinci_mdio: mdio {
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. bus_freq = <1000000>;
  124. };
  125. cpts {
  126. clocks = <&k3_clks 18 2>;
  127. clock-names = "cpts";
  128. interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
  129. interrupt-names = "cpts";
  130. ti,cpts-ext-ts-inputs = <4>;
  131. ti,cpts-periodic-outputs = <2>;
  132. };
  133. ti,psil-config0 {
  134. linux,udma-mode = <UDMA_PKT_MODE>;
  135. statictr-type = <PSIL_STATIC_TR_NONE>;
  136. ti,needs-epib;
  137. ti,psd-size = <16>;
  138. };
  139. ti,psil-config1 {
  140. linux,udma-mode = <UDMA_PKT_MODE>;
  141. statictr-type = <PSIL_STATIC_TR_NONE>;
  142. ti,needs-epib;
  143. ti,psd-size = <16>;
  144. };
  145. ti,psil-config2 {
  146. linux,udma-mode = <UDMA_PKT_MODE>;
  147. statictr-type = <PSIL_STATIC_TR_NONE>;
  148. ti,needs-epib;
  149. ti,psd-size = <16>;
  150. };
  151. ti,psil-config3 {
  152. linux,udma-mode = <UDMA_PKT_MODE>;
  153. statictr-type = <PSIL_STATIC_TR_NONE>;
  154. ti,needs-epib;
  155. ti,psd-size = <16>;
  156. };
  157. ti,psil-config4 {
  158. linux,udma-mode = <UDMA_PKT_MODE>;
  159. statictr-type = <PSIL_STATIC_TR_NONE>;
  160. ti,needs-epib;
  161. ti,psd-size = <16>;
  162. };
  163. ti,psil-config5 {
  164. linux,udma-mode = <UDMA_PKT_MODE>;
  165. statictr-type = <PSIL_STATIC_TR_NONE>;
  166. ti,needs-epib;
  167. ti,psd-size = <16>;
  168. };
  169. ti,psil-config6 {
  170. linux,udma-mode = <UDMA_PKT_MODE>;
  171. statictr-type = <PSIL_STATIC_TR_NONE>;
  172. ti,needs-epib;
  173. ti,psd-size = <16>;
  174. };
  175. ti,psil-config7 {
  176. linux,udma-mode = <UDMA_PKT_MODE>;
  177. statictr-type = <PSIL_STATIC_TR_NONE>;
  178. ti,needs-epib;
  179. ti,psd-size = <16>;
  180. };
  181. };
  182. };
  183. &secure_proxy_main {
  184. u-boot,dm-spl;
  185. };
  186. &dmsc {
  187. u-boot,dm-spl;
  188. k3_sysreset: sysreset-controller {
  189. compatible = "ti,sci-sysreset";
  190. u-boot,dm-spl;
  191. };
  192. };
  193. &k3_pds {
  194. u-boot,dm-spl;
  195. };
  196. &k3_clks {
  197. u-boot,dm-spl;
  198. };
  199. &k3_reset {
  200. u-boot,dm-spl;
  201. };
  202. &wkup_pmx0 {
  203. u-boot,dm-spl;
  204. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  205. pinctrl-single,pins = <
  206. J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  207. J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  208. J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  209. J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  210. J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  211. J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  212. J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  213. J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  214. J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  215. J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  216. J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  217. J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  218. >;
  219. };
  220. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  221. pinctrl-single,pins = <
  222. J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  223. J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  224. >;
  225. };
  226. };
  227. &main_pmx0 {
  228. u-boot,dm-spl;
  229. };
  230. &main_uart0 {
  231. u-boot,dm-spl;
  232. };
  233. &mcu_uart0 {
  234. u-boot,dm-spl;
  235. };
  236. &main_sdhci0 {
  237. u-boot,dm-spl;
  238. };
  239. &main_sdhci1 {
  240. u-boot,dm-spl;
  241. };
  242. &main_usbss0_pins_default {
  243. u-boot,dm-spl;
  244. };
  245. &usbss0 {
  246. u-boot,dm-spl;
  247. ti,usb2-only;
  248. };
  249. &usb0 {
  250. dr_mode = "peripheral";
  251. u-boot,dm-spl;
  252. };
  253. &mcu_cpsw {
  254. pinctrl-names = "default";
  255. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  256. };
  257. &davinci_mdio {
  258. phy0: ethernet-phy@0 {
  259. reg = <0>;
  260. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  261. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  262. };
  263. };
  264. &cpsw_port1 {
  265. phy-mode = "rgmii-rxid";
  266. phy-handle = <&phy0>;
  267. };
  268. &mcu_cpsw {
  269. reg = <0x0 0x46000000 0x0 0x200000>,
  270. <0x0 0x40f00200 0x0 0x2>;
  271. reg-names = "cpsw_nuss", "mac_efuse";
  272. cpsw-phy-sel@40f04040 {
  273. compatible = "ti,am654-cpsw-phy-sel";
  274. reg= <0x0 0x40f04040 0x0 0x4>;
  275. reg-names = "gmii-sel";
  276. };
  277. };
  278. &main_mmc1_pins_default {
  279. u-boot,dm-spl;
  280. };
  281. &wkup_i2c0_pins_default {
  282. u-boot,dm-spl;
  283. };
  284. &wkup_i2c0 {
  285. u-boot,dm-spl;
  286. };
  287. &main_i2c0 {
  288. u-boot,dm-spl;
  289. };
  290. &main_i2c0_pins_default {
  291. u-boot,dm-spl;
  292. };
  293. &exp2 {
  294. u-boot,dm-spl;
  295. };
  296. &mcu_fss0_ospi0_pins_default {
  297. u-boot,dm-spl;
  298. };
  299. &fss {
  300. u-boot,dm-spl;
  301. };
  302. &ospi0 {
  303. u-boot,dm-spl;
  304. flash@0 {
  305. u-boot,dm-spl;
  306. };
  307. };
  308. &ospi1 {
  309. u-boot,dm-spl;
  310. flash@0 {
  311. u-boot,dm-spl;
  312. };
  313. };
  314. &mcu_fss0_ospi1_pins_default {
  315. u-boot,dm-spl;
  316. };