k3-am654-base-board-u-boot.dtsi 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/pinctrl/k3.h>
  6. #include <dt-bindings/dma/k3-udma.h>
  7. #include <dt-bindings/net/ti-dp83867.h>
  8. / {
  9. chosen {
  10. stdout-path = "serial2:115200n8";
  11. };
  12. aliases {
  13. serial2 = &main_uart0;
  14. ethernet0 = &cpsw_port1;
  15. };
  16. };
  17. &cbass_main{
  18. u-boot,dm-spl;
  19. sdhci1: sdhci@04FA0000 {
  20. compatible = "ti,am654-sdhci-5.1";
  21. reg = <0x0 0x4FA0000 0x0 0x1000>,
  22. <0x0 0x4FB0000 0x0 0x400>;
  23. clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
  24. clock-names = "clk_ahb", "clk_xin";
  25. power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  26. max-frequency = <25000000>;
  27. ti,otap-del-sel-legacy = <0x0>;
  28. ti,otap-del-sel-mmc-hs = <0x0>;
  29. ti,otap-del-sel-sd-hs = <0x0>;
  30. ti,otap-del-sel-sdr12 = <0x0>;
  31. ti,otap-del-sel-sdr25 = <0x0>;
  32. ti,otap-del-sel-sdr50 = <0x8>;
  33. ti,otap-del-sel-sdr104 = <0x7>;
  34. ti,otap-del-sel-ddr50 = <0x4>;
  35. ti,otap-del-sel-ddr52 = <0x4>;
  36. ti,otap-del-sel-hs200 = <0x7>;
  37. ti,trm-icp = <0x8>;
  38. };
  39. };
  40. &cbass_mcu {
  41. u-boot,dm-spl;
  42. navss_mcu: navss-mcu {
  43. compatible = "simple-bus";
  44. #address-cells = <2>;
  45. #size-cells = <2>;
  46. ranges;
  47. u-boot,dm-spl;
  48. ti,sci-dev-id = <119>;
  49. mcu_ringacc: ringacc@2b800000 {
  50. compatible = "ti,am654-navss-ringacc";
  51. reg = <0x0 0x2b800000 0x0 0x400000>,
  52. <0x0 0x2b000000 0x0 0x400000>,
  53. <0x0 0x28590000 0x0 0x100>,
  54. <0x0 0x2a500000 0x0 0x40000>;
  55. reg-names = "rt", "fifos",
  56. "proxy_gcfg", "proxy_target";
  57. ti,num-rings = <286>;
  58. ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
  59. ti,dma-ring-reset-quirk;
  60. ti,sci = <&dmsc>;
  61. ti,sci-dev-id = <195>;
  62. u-boot,dm-spl;
  63. };
  64. mcu_udmap: udmap@285c0000 {
  65. compatible = "ti,k3-navss-udmap";
  66. reg = <0x0 0x285c0000 0x0 0x100>,
  67. <0x0 0x2a800000 0x0 0x40000>,
  68. <0x0 0x2aa00000 0x0 0x40000>;
  69. reg-names = "gcfg", "rchanrt", "tchanrt";
  70. #dma-cells = <3>;
  71. ti,ringacc = <&mcu_ringacc>;
  72. ti,psil-base = <0x6000>;
  73. ti,sci = <&dmsc>;
  74. ti,sci-dev-id = <194>;
  75. ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
  76. <0x2>; /* TX_CHAN */
  77. ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
  78. <0x4>; /* RX_CHAN */
  79. ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
  80. dma-coherent;
  81. u-boot,dm-spl;
  82. };
  83. };
  84. mcu_conf: scm_conf@40f00000 {
  85. compatible = "syscon";
  86. reg = <0x0 0x40f00000 0x0 0x20000>;
  87. };
  88. mcu_cpsw: cpsw_nuss@046000000 {
  89. compatible = "ti,am654-cpsw-nuss";
  90. #address-cells = <2>;
  91. #size-cells = <2>;
  92. reg = <0x0 0x46000000 0x0 0x200000>;
  93. reg-names = "cpsw_nuss";
  94. ranges;
  95. dma-coherent;
  96. clocks = <&k3_clks 5 10>;
  97. clock-names = "fck";
  98. power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
  99. ti,psil-base = <0x7000>;
  100. dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
  101. <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
  102. <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
  103. <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
  104. <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
  105. <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
  106. <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
  107. <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
  108. <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
  109. dma-names = "tx0", "tx1", "tx2", "tx3",
  110. "tx4", "tx5", "tx6", "tx7",
  111. "rx";
  112. ports {
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. host: host@0 {
  116. reg = <0>;
  117. ti,label = "host";
  118. };
  119. cpsw_port1: port@1 {
  120. reg = <1>;
  121. ti,mac-only;
  122. ti,label = "port1";
  123. ti,syscon-efuse = <&mcu_conf 0x200>;
  124. };
  125. };
  126. davinci_mdio: mdio {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. bus_freq = <1000000>;
  130. };
  131. ti,psil-config0 {
  132. linux,udma-mode = <UDMA_PKT_MODE>;
  133. statictr-type = <PSIL_STATIC_TR_NONE>;
  134. ti,needs-epib;
  135. ti,psd-size = <16>;
  136. };
  137. ti,psil-config1 {
  138. linux,udma-mode = <UDMA_PKT_MODE>;
  139. statictr-type = <PSIL_STATIC_TR_NONE>;
  140. ti,needs-epib;
  141. ti,psd-size = <16>;
  142. };
  143. ti,psil-config2 {
  144. linux,udma-mode = <UDMA_PKT_MODE>;
  145. statictr-type = <PSIL_STATIC_TR_NONE>;
  146. ti,needs-epib;
  147. ti,psd-size = <16>;
  148. };
  149. ti,psil-config3 {
  150. linux,udma-mode = <UDMA_PKT_MODE>;
  151. statictr-type = <PSIL_STATIC_TR_NONE>;
  152. ti,needs-epib;
  153. ti,psd-size = <16>;
  154. };
  155. ti,psil-config4 {
  156. linux,udma-mode = <UDMA_PKT_MODE>;
  157. statictr-type = <PSIL_STATIC_TR_NONE>;
  158. ti,needs-epib;
  159. ti,psd-size = <16>;
  160. };
  161. ti,psil-config5 {
  162. linux,udma-mode = <UDMA_PKT_MODE>;
  163. statictr-type = <PSIL_STATIC_TR_NONE>;
  164. ti,needs-epib;
  165. ti,psd-size = <16>;
  166. };
  167. ti,psil-config6 {
  168. linux,udma-mode = <UDMA_PKT_MODE>;
  169. statictr-type = <PSIL_STATIC_TR_NONE>;
  170. ti,needs-epib;
  171. ti,psd-size = <16>;
  172. };
  173. ti,psil-config7 {
  174. linux,udma-mode = <UDMA_PKT_MODE>;
  175. statictr-type = <PSIL_STATIC_TR_NONE>;
  176. ti,needs-epib;
  177. ti,psd-size = <16>;
  178. };
  179. };
  180. };
  181. &cbass_wakeup {
  182. u-boot,dm-spl;
  183. };
  184. &secure_proxy_main {
  185. u-boot,dm-spl;
  186. };
  187. &dmsc {
  188. u-boot,dm-spl;
  189. k3_sysreset: sysreset-controller {
  190. compatible = "ti,sci-sysreset";
  191. u-boot,dm-spl;
  192. };
  193. };
  194. &k3_pds {
  195. u-boot,dm-spl;
  196. };
  197. &k3_clks {
  198. u-boot,dm-spl;
  199. };
  200. &k3_reset {
  201. u-boot,dm-spl;
  202. };
  203. &wkup_pmx0 {
  204. u-boot,dm-spl;
  205. wkup_i2c0_pins_default {
  206. u-boot,dm-spl;
  207. };
  208. };
  209. &main_pmx0 {
  210. u-boot,dm-spl;
  211. main_uart0_pins_default: main_uart0_pins_default {
  212. pinctrl-single,pins = <
  213. AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
  214. AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
  215. AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
  216. AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
  217. >;
  218. u-boot,dm-spl;
  219. };
  220. main_mmc0_pins_default: main_mmc0_pins_default {
  221. pinctrl-single,pins = <
  222. AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
  223. AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
  224. AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
  225. AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
  226. AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
  227. AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
  228. AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
  229. AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
  230. AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
  231. AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
  232. AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
  233. AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
  234. >;
  235. u-boot,dm-spl;
  236. };
  237. main_mmc1_pins_default: main_mmc1_pins_default {
  238. pinctrl-single,pins = <
  239. AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
  240. AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
  241. AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
  242. AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
  243. AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
  244. AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
  245. AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
  246. AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
  247. >;
  248. u-boot,dm-spl;
  249. };
  250. };
  251. &main_pmx1 {
  252. u-boot,dm-spl;
  253. };
  254. &wkup_pmx0 {
  255. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  256. pinctrl-single,pins = <
  257. AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  258. AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  259. AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  260. AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  261. AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  262. AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  263. AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  264. AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  265. AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  266. AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  267. AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  268. AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  269. >;
  270. };
  271. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  272. pinctrl-single,pins = <
  273. AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  274. AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  275. >;
  276. };
  277. mcu-fss0-ospi0-pins-default {
  278. u-boot,dm-spl;
  279. };
  280. };
  281. &main_uart0 {
  282. u-boot,dm-spl;
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&main_uart0_pins_default>;
  285. status = "okay";
  286. };
  287. &sdhci0 {
  288. u-boot,dm-spl;
  289. };
  290. &sdhci1 {
  291. u-boot,dm-spl;
  292. status = "okay";
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&main_mmc1_pins_default>;
  295. sdhci-caps-mask = <0x7 0x0>;
  296. ti,driver-strength-ohm = <50>;
  297. };
  298. &mcu_cpsw {
  299. pinctrl-names = "default";
  300. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  301. };
  302. &davinci_mdio {
  303. phy0: ethernet-phy@0 {
  304. reg = <0>;
  305. /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
  306. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  307. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  308. };
  309. };
  310. &cpsw_port1 {
  311. phy-mode = "rgmii-rxid";
  312. phy-handle = <&phy0>;
  313. };
  314. &mcu_cpsw {
  315. reg = <0x0 0x46000000 0x0 0x200000>,
  316. <0x0 0x40f00200 0x0 0x2>;
  317. reg-names = "cpsw_nuss", "mac_efuse";
  318. cpsw-phy-sel@40f04040 {
  319. compatible = "ti,am654-cpsw-phy-sel";
  320. reg= <0x0 0x40f04040 0x0 0x4>;
  321. reg-names = "gmii-sel";
  322. };
  323. };
  324. &wkup_i2c0 {
  325. u-boot,dm-spl;
  326. };
  327. &usb1 {
  328. dr_mode = "peripheral";
  329. };
  330. &fss {
  331. u-boot,dm-spl;
  332. };
  333. &ospi0 {
  334. u-boot,dm-spl;
  335. flash@0{
  336. u-boot,dm-spl;
  337. };
  338. };