k3-am65.dtsi 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM6 SoC Family
  4. *
  5. * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/interrupt-controller/irq.h>
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include <dt-bindings/pinctrl/k3.h>
  11. #include <dt-bindings/soc/ti,sci_pm_domain.h>
  12. / {
  13. model = "Texas Instruments K3 AM654 SoC";
  14. compatible = "ti,am654";
  15. interrupt-parent = <&gic500>;
  16. #address-cells = <2>;
  17. #size-cells = <2>;
  18. aliases {
  19. serial0 = &wkup_uart0;
  20. serial1 = &mcu_uart0;
  21. serial2 = &main_uart0;
  22. serial3 = &main_uart1;
  23. serial4 = &main_uart2;
  24. i2c0 = &wkup_i2c0;
  25. i2c1 = &mcu_i2c0;
  26. i2c2 = &main_i2c0;
  27. i2c3 = &main_i2c1;
  28. i2c4 = &main_i2c2;
  29. i2c5 = &main_i2c3;
  30. spi0 = &ospi0;
  31. spi1 = &ospi1;
  32. };
  33. chosen { };
  34. firmware {
  35. optee {
  36. compatible = "linaro,optee-tz";
  37. method = "smc";
  38. };
  39. psci: psci {
  40. compatible = "arm,psci-1.0";
  41. method = "smc";
  42. };
  43. };
  44. a53_timer0: timer-cl0-cpu0 {
  45. compatible = "arm,armv8-timer";
  46. interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
  47. <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
  48. <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
  49. <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
  50. };
  51. pmu: pmu {
  52. compatible = "arm,armv8-pmuv3";
  53. /* Recommendation from GIC500 TRM Table A.3 */
  54. interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  55. };
  56. cbass_main: interconnect@100000 {
  57. compatible = "simple-bus";
  58. #address-cells = <2>;
  59. #size-cells = <2>;
  60. ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
  61. <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
  62. <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
  63. <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
  64. <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
  65. <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
  66. /* MCUSS Range */
  67. <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
  68. <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
  69. <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
  70. <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
  71. <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
  72. <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
  73. <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
  74. <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
  75. <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
  76. <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
  77. <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
  78. <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
  79. <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
  80. cbass_mcu: interconnect@28380000 {
  81. compatible = "simple-bus";
  82. #address-cells = <2>;
  83. #size-cells = <2>;
  84. ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
  85. <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
  86. <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
  87. <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
  88. <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
  89. <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
  90. <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
  91. <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
  92. <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
  93. <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
  94. <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
  95. <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
  96. cbass_wakeup: interconnect@42040000 {
  97. compatible = "simple-bus";
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. /* WKUP Basic peripherals */
  101. ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
  102. };
  103. };
  104. };
  105. };
  106. /* Now include the peripherals for each bus segments */
  107. #include "k3-am65-main.dtsi"
  108. #include "k3-am65-mcu.dtsi"
  109. #include "k3-am65-wakeup.dtsi"