sf_vop.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
  4. * Copyright (c) 2015 Google, Inc
  5. * Copyright 2014 Rockchip Inc.
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <dm/uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/uclass-internal.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <regmap.h>
  16. #include <syscon.h>
  17. #include <video.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <linux/delay.h>
  21. #include <power-domain-uclass.h>
  22. #include <power-domain.h>
  23. #include <clk.h>
  24. #include <video_bridge.h>
  25. #include <power/pmic.h>
  26. #include <panel.h>
  27. #include "sf_vop.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static void iotrace_writel(ulong value, void *ptr)
  30. {
  31. //printf("writel( 0x%08x, %p ) -- 0x%08x\n", value, ptr, readl(ptr));
  32. //readl(ptr);
  33. mdelay(10);
  34. writel(value, ptr);
  35. }
  36. static int sf_vop_power_off(struct udevice *dev)
  37. {
  38. struct udevice *dev_power;
  39. struct udevice *dev_pmic;
  40. struct power_domain_ops *ops;
  41. struct power_domain power_domain;
  42. int ret;
  43. if (!(gd->flags & GD_FLG_RELOC))
  44. return 0;
  45. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  46. if (ret)
  47. return ret;
  48. ret = device_probe(dev_power);
  49. if (ret) {
  50. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  51. __func__, dev_power->name, ret);
  52. return ret;
  53. }
  54. ops = (struct power_domain_ops *)dev_power->driver->ops;
  55. power_domain.dev = dev_power;
  56. power_domain.id = 4;
  57. ret = ops->off(&power_domain);
  58. if (ret) {
  59. pr_err("ops->0ff() failed: %d\n", ret);
  60. return ret;
  61. }
  62. return 0;
  63. }
  64. static int sf_vop_power(struct udevice *dev)
  65. {
  66. struct udevice *dev_power;
  67. struct udevice *dev_pmic;
  68. struct power_domain_ops *ops;
  69. struct power_domain power_domain;
  70. int ret;
  71. if (!(gd->flags & GD_FLG_RELOC))
  72. return 0;
  73. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  74. if (ret)
  75. return ret;
  76. ret = device_probe(dev_power);
  77. if (ret) {
  78. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  79. __func__, dev_power->name, ret);
  80. return ret;
  81. }
  82. ops = (struct power_domain_ops *)dev_power->driver->ops;
  83. power_domain.dev = dev_power;
  84. power_domain.id = 4;
  85. ret = ops->request(&power_domain);
  86. if (ret) {
  87. pr_err("ops->request() failed: %d\n", ret);
  88. return ret;
  89. }
  90. ret = ops->on(&power_domain);
  91. if (ret) {
  92. pr_err("ops->on() failed: %d\n", ret);
  93. return ret;
  94. }
  95. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  96. DM_DRIVER_GET(pmic_starfive), &dev_pmic);
  97. if (ret) {
  98. pr_err("failed to find PMIC: %d\n", ret);
  99. return ret;
  100. }
  101. ret = pmic_clrsetbits(dev_pmic, POWER_SW_0_REG, 0x3f, 0x3f);
  102. if (ret) {
  103. pr_err("failed to update SD control register: %d", ret);
  104. return ret;
  105. }
  106. return 0;
  107. }
  108. static int vout_get_rst_clock_resources(struct udevice *dev)
  109. {
  110. struct sf_vop_priv *priv = dev_get_priv(dev);
  111. int ret;
  112. ret = clk_get_by_name(dev, "disp_axi", &priv->disp_axi);
  113. if (ret) {
  114. pr_err("clk_get_by_name(noc_disp) failed: %d", ret);
  115. return ret;
  116. }
  117. ret = clk_get_by_name(dev, "vout_src", &priv->vout_src);
  118. if (ret) {
  119. pr_err("clk_get_by_name(vout_src) failed: %d\n", ret);
  120. return ret;
  121. }
  122. ret = clk_get_by_name(dev, "top_vout_axi", &priv->top_vout_axi);
  123. if (ret) {
  124. pr_err("clk_get_by_name(top_vout_axi) failed: %d\n", ret);
  125. return ret;
  126. }
  127. ret = clk_get_by_name(dev, "top_vout_ahb", &priv->top_vout_ahb);
  128. if (ret) {
  129. pr_err("clk_get_by_name(top_vout_ahb) failed: %d\n", ret);
  130. return ret;
  131. }
  132. ret = clk_get_by_name(dev, "dc_pix0", &priv->dc_pix0);
  133. if (ret) {
  134. pr_err("clk_get_by_name(dc_pix0) failed: %d\n", ret);
  135. return ret;
  136. }
  137. ret = clk_get_by_name(dev, "dc_pix1", &priv->dc_pix1);
  138. if (ret) {
  139. pr_err("clk_get_by_name(dc_pix1) failed: %d\n", ret);
  140. return ret;
  141. }
  142. ret = clk_get_by_name(dev, "dc_axi", &priv->dc_axi);
  143. if (ret) {
  144. pr_err("clk_get_by_name(dc_axi) failed: %d\n", ret);
  145. return ret;
  146. }
  147. ret = clk_get_by_name(dev, "dc_core", &priv->dc_core);
  148. if (ret) {
  149. pr_err("clk_get_by_name(dc_core) failed: %d\n", ret);
  150. return ret;
  151. }
  152. ret = clk_get_by_name(dev, "dc_ahb", &priv->dc_ahb);
  153. if (ret) {
  154. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  155. return ret;
  156. }
  157. ret = clk_get_by_name(dev, "top_vout_lcd", &priv->top_vout_lcd);
  158. if (ret) {
  159. pr_err("clk_get_by_name(top_vout_lcd) failed: %d\n", ret);
  160. return ret;
  161. }
  162. ret = clk_get_by_name(dev, "hdmitx0_pixelclk", &priv->hdmitx0_pixelclk);
  163. if (ret) {
  164. pr_err("clk_get_by_name(hdmitx0_pixelclk) failed: %d\n", ret);
  165. return ret;
  166. }
  167. ret = clk_get_by_name(dev, "dc8200_pix0", &priv->dc_pix_src);
  168. if (ret) {
  169. pr_err("clk_get_by_name(dc_pix_src) failed: %d\n", ret);
  170. return ret;
  171. }
  172. ret = clk_get_by_name(dev, "dc8200_pix0_out", &priv->dc_pix0_out);
  173. if (ret) {
  174. pr_err("clk_get_by_name(dc_pix0_out) failed: %d\n", ret);
  175. return ret;
  176. }
  177. ret = clk_get_by_name(dev, "dc8200_pix1_out", &priv->dc_pix1_out);
  178. if (ret) {
  179. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  180. return ret;
  181. }
  182. ret = reset_get_by_name(dev, "rst_vout_src", &priv->rst_vout_src);
  183. if (ret) {
  184. pr_err("failed to get rst_vout_src reset (ret=%d)\n", ret);
  185. return ret;
  186. }
  187. ret = reset_get_by_name(dev, "rst_axi", &priv->dc8200_rst_axi);
  188. if (ret) {
  189. pr_err("failed to get dc8200_rst_axi reset (ret=%d)\n", ret);
  190. return ret;
  191. }
  192. ret = reset_get_by_name(dev, "rst_ahb", &priv->dc8200_rst_ahb);
  193. if (ret) {
  194. pr_err("failed to get ahb reset (ret=%d)\n", ret);
  195. return ret;
  196. }
  197. ret = reset_get_by_name(dev, "rst_core", &priv->dc8200_rst_core);
  198. if (ret) {
  199. pr_err("failed to get dc8200_rst_core reset (ret=%d)\n", ret);
  200. return ret;
  201. }
  202. ret = reset_get_by_name(dev, "rst_noc_disp", &priv->noc_disp);
  203. if (ret) {
  204. pr_err("failed to get noc_disp reset (ret=%d)\n", ret);
  205. return ret;
  206. }
  207. debug("%s: OK\n", __func__);
  208. return 0;
  209. }
  210. int dc_hw_init(struct udevice *dev)
  211. {
  212. struct sf_vop_priv *priv = dev_get_priv(dev);
  213. u32 revision = readl(priv->regs_hi+DC_HW_REVISION);
  214. u32 cid = readl(priv->regs_hi+DC_HW_CHIP_CID);
  215. debug("%s: revision = %08x\n", __func__,revision);
  216. debug("%s: cid = %08x\n", __func__,cid);
  217. return 0;
  218. }
  219. static int vout_probe_resources_jh7110(struct udevice *dev)
  220. {
  221. struct sf_vop_priv *priv = dev_get_priv(dev);
  222. int ret;
  223. ret = vout_get_rst_clock_resources(dev);
  224. ret = clk_enable(&priv->disp_axi);
  225. if (ret < 0) {
  226. pr_err("clk_enable(noc_disp) failed: %d\n", ret);
  227. return ret;
  228. }
  229. ret = reset_deassert(&priv->noc_disp);
  230. if (ret) {
  231. pr_err("failed to deassert noc_disp reset (ret=%d)\n", ret);
  232. goto free_clock_vout_src;
  233. }
  234. ret = clk_enable(&priv->vout_src);
  235. if (ret < 0) {
  236. pr_err("clk_enable(vout_src) failed: %d\n", ret);
  237. goto free_clock_vout_src;
  238. }
  239. ret = clk_enable(&priv->top_vout_axi);
  240. if (ret < 0) {
  241. pr_err("clk_enable(top_vout_axi) failed: %d\n", ret);
  242. goto free_clock_top_vout_axi;
  243. }
  244. ret = clk_enable(&priv->top_vout_ahb);
  245. if (ret < 0) {
  246. pr_err("clk_enable(top_vout_ahb) failed: %d\n", ret);
  247. goto free_clock_top_vout_ahb;
  248. }
  249. ret = reset_deassert(&priv->rst_vout_src);
  250. if (ret) {
  251. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  252. goto free_clock_dc_pix0;
  253. }
  254. ret = clk_enable(&priv->dc_pix0);
  255. if (ret < 0) {
  256. pr_err("clk_enable(dc_pix0) failed: %d\n", ret);
  257. goto free_clock_dc_pix0;
  258. }
  259. ret = clk_enable(&priv->dc_pix1);
  260. if (ret < 0) {
  261. pr_err("clk_enable(dc_pix1) failed: %d\n", ret);
  262. goto free_clock_dc_pix1;
  263. }
  264. ret = clk_enable(&priv->dc_axi);
  265. if (ret < 0) {
  266. pr_err("clk_enable(dc_axi) failed: %d\n", ret);
  267. goto free_clock_dc_axi;
  268. }
  269. ret = clk_enable(&priv->dc_core);
  270. if (ret < 0) {
  271. pr_err("clk_enable(dc_core) failed: %d\n", ret);
  272. goto free_clock_dc_core;
  273. }
  274. ret = clk_enable(&priv->dc_ahb);
  275. if (ret < 0) {
  276. pr_err("clk_enable(dc_ahb) failed: %d\n", ret);
  277. goto free_clock_dc_ahb;
  278. }
  279. ret = clk_enable(&priv->hdmitx0_pixelclk);
  280. if (ret < 0) {
  281. pr_err("clk_enable(hdmitx0_pixelclk) failed: %d\n", ret);
  282. goto free_clock_hdmitx0_pixelclk;
  283. }
  284. ret = reset_deassert(&priv->dc8200_rst_axi);
  285. if (ret) {
  286. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  287. goto free_reset_dc8200;
  288. }
  289. ret = reset_deassert(&priv->dc8200_rst_core);
  290. if (ret) {
  291. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  292. goto free_reset_dc8200;
  293. }
  294. ret = reset_deassert(&priv->dc8200_rst_ahb);
  295. if (ret) {
  296. pr_err("failed to deassert dc8200_rst_ahb reset (ret=%d)\n", ret);
  297. goto free_reset_dc8200;
  298. }
  299. debug("%s: OK\n", __func__);
  300. return 0;
  301. free_reset_dc8200:
  302. clk_disable(&priv->hdmitx0_pixelclk);
  303. free_clock_hdmitx0_pixelclk:
  304. clk_disable(&priv->dc_ahb);
  305. free_clock_dc_ahb:
  306. clk_disable(&priv->dc_core);
  307. free_clock_dc_core:
  308. clk_disable(&priv->dc_axi);
  309. free_clock_dc_axi:
  310. clk_disable(&priv->dc_pix1);
  311. free_clock_dc_pix1:
  312. clk_disable(&priv->dc_pix0);
  313. free_clock_dc_pix0:
  314. clk_disable(&priv->top_vout_ahb);
  315. free_clock_top_vout_ahb:
  316. clk_disable(&priv->top_vout_axi);
  317. free_clock_top_vout_axi:
  318. clk_disable(&priv->vout_src);
  319. free_clock_vout_src:
  320. clk_disable(&priv->disp_axi);
  321. return ret;
  322. }
  323. static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
  324. {
  325. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  326. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  327. struct sf_vop_priv *priv = dev_get_priv(dev);
  328. int vop_id, remote_vop_id;
  329. struct display_timing timing;
  330. struct udevice *disp;
  331. int ret;
  332. u32 remote_phandle;
  333. ofnode remote;
  334. const char *compat;
  335. struct display_plat *disp_uc_plat;
  336. debug("%s(%s, 0x%lx, %s)\n", __func__,
  337. dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
  338. struct udevice *panel = NULL;
  339. ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
  340. if (ret)
  341. return ret;
  342. remote = ofnode_get_by_phandle(remote_phandle);
  343. if (!ofnode_valid(remote))
  344. return -EINVAL;
  345. remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
  346. uc_priv->bpix = VIDEO_BPP32;
  347. debug("remote_vop_id %d\n", remote_vop_id);
  348. /*
  349. * The remote-endpoint references into a subnode of the encoder
  350. * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
  351. * the following (assume 'hdmi_in_vopl' to be referenced):
  352. *
  353. * hdmi: hdmi@ff940000 {
  354. * ports {
  355. * hdmi_in: port {
  356. * hdmi_in_vopb: endpoint@0 { ... };
  357. * hdmi_in_vopl: endpoint@1 { ... };
  358. * }
  359. * }
  360. * }
  361. *
  362. * The original code had 3 steps of "walking the parent", but
  363. * a much better (as in: less likely to break if the DTS
  364. * changes) way of doing this is to "find the enclosing device
  365. * of UCLASS_DISPLAY".
  366. */
  367. while (ofnode_valid(remote)) {
  368. remote = ofnode_get_parent(remote);
  369. if (!ofnode_valid(remote)) {
  370. debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
  371. __func__, dev_read_name(dev));
  372. return -EINVAL;
  373. }
  374. debug("%s(%s, 0x%lx,remote %s)\n", __func__,
  375. dev_read_name(dev), fbbase, ofnode_get_name(remote));
  376. uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
  377. if (disp)
  378. break;
  379. uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &disp);
  380. if (disp)
  381. break;
  382. };
  383. compat = ofnode_get_property(remote, "compatible", NULL);
  384. if (!compat) {
  385. debug("%s(%s): Failed to find compatible property\n",
  386. __func__, dev_read_name(dev));
  387. return -EINVAL;
  388. }
  389. if (strstr(compat, "edp")) {
  390. vop_id = VOP_MODE_EDP;
  391. } else if (strstr(compat, "mipi")) {
  392. vop_id = VOP_MODE_MIPI;
  393. } else if (strstr(compat, "hdmi")) {
  394. vop_id = VOP_MODE_HDMI;
  395. } else if (strstr(compat, "cdn-dp")) {
  396. vop_id = VOP_MODE_DP;
  397. } else if (strstr(compat, "lvds")) {
  398. vop_id = VOP_MODE_LVDS;
  399. } else {
  400. debug("%s(%s): Failed to find vop mode for %s\n",
  401. __func__, dev_read_name(dev), compat);
  402. return -EINVAL;
  403. }
  404. debug("vop_id %d,compat = %s\n", vop_id,compat);
  405. if(vop_id == VOP_MODE_HDMI)
  406. {
  407. disp_uc_plat = dev_get_uclass_plat(disp);
  408. debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  409. disp_uc_plat->source_id = remote_vop_id;
  410. disp_uc_plat->src_dev = dev;
  411. ret = device_probe(disp);
  412. if (ret) {
  413. debug("%s: device '%s' display won't probe (ret=%d)\n",
  414. __func__, dev->name, ret);
  415. return ret;
  416. }
  417. ret = display_enable(disp, 1 << VIDEO_BPP32, &timing);
  418. if (ret) {
  419. debug("%s: Failed to read timings\n", __func__);
  420. return ret;
  421. }
  422. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  423. if (err) {
  424. debug("failed to set %s clock as %s's parent\n",
  425. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  426. return err;
  427. }
  428. ulong new_rate = clk_set_rate(&priv->dc_pix_src, 148500000);
  429. debug("new_rate %ld\n", new_rate);
  430. dc_hw_init(dev);
  431. uc_priv->xsize = 1920;
  432. uc_priv->ysize = 1080;
  433. writel(0xc0001fff, priv->regs_hi+0x00000014);
  434. writel(0x00002000, priv->regs_hi+0x00001cc0);
  435. //writel(uc_plat->base+0x1fa400, priv->regs_hi+0x00001530);
  436. writel(0x00000000, priv->regs_hi+0x00001800);
  437. writel(0x00000000, priv->regs_hi+0x000024d8);
  438. writel(0x021c0780, priv->regs_hi+0x000024e0);
  439. writel(0x021c0780, priv->regs_hi+0x00001810);
  440. writel(uc_plat->base, priv->regs_hi+0x00001400);
  441. writel(0x00001e00, priv->regs_hi+0x00001408);
  442. writel(0x00000f61, priv->regs_hi+0x00001ce8);
  443. writel(0x00002042, priv->regs_hi+0x00002510);
  444. writel(0x808a3156, priv->regs_hi+0x00002508);
  445. writel(0x8008e1b2, priv->regs_hi+0x00002500);
  446. writel(0x18000000, priv->regs_hi+0x00001518);
  447. writel(0x00003000, priv->regs_hi+0x00001cc0);
  448. writel(0x00060000, priv->regs_hi+0x00001540);
  449. writel(0x00000001, priv->regs_hi+0x00002540);
  450. writel(0x80060000, priv->regs_hi+0x00001540);
  451. writel(0x00060000, priv->regs_hi+0x00001544);
  452. writel(0x00000002, priv->regs_hi+0x00002544);
  453. writel(0x80060000, priv->regs_hi+0x00001544);
  454. writel(0x00060000, priv->regs_hi+0x00001548);
  455. writel(0x0000000c, priv->regs_hi+0x00002548);
  456. writel(0x80060000, priv->regs_hi+0x00001548);
  457. writel(0x00060000, priv->regs_hi+0x0000154c);
  458. writel(0x0000000d, priv->regs_hi+0x0000254c);
  459. writel(0x80060000, priv->regs_hi+0x0000154c);
  460. writel(0x00000001, priv->regs_hi+0x00002518);
  461. writel(0x00000000, priv->regs_hi+0x00001a28);
  462. writel(0x08980780, priv->regs_hi+0x00001430);
  463. writel(0x440207d8, priv->regs_hi+0x00001438);
  464. writel(0x04650438, priv->regs_hi+0x00001440);
  465. writel(0x4220843c, priv->regs_hi+0x00001448);
  466. writel(0x00000000, priv->regs_hi+0x000014b0);
  467. writel(0x000000d2, priv->regs_hi+0x00001cd0);
  468. writel(0x00000005, priv->regs_hi+0x000014b8);
  469. writel(0x00000052, priv->regs_hi+0x000014d0);
  470. writel(0xdeadbeef, priv->regs_hi+0x00001528);
  471. writel(0x00001111, priv->regs_hi+0x00001418);
  472. writel(0x00000000, priv->regs_hi+0x00001410);
  473. writel(0x00000000, priv->regs_hi+0x00002518);
  474. writel(0x00200024, priv->regs_hi+0x00001468);
  475. writel(0x00000000, priv->regs_hi+0x00001484);
  476. writel(0x00200024, priv->regs_hi+0x00001468);
  477. writel(0x00000c24, priv->regs_hi+0x000024e8);
  478. writel(0x00000000, priv->regs_hi+0x000024fc);
  479. writel(0x00000c24, priv->regs_hi+0x000024e8);
  480. writel(0x00000001, priv->regs_hi+0x00001ccc);
  481. priv->hdmi_logo = true;
  482. return 0;
  483. }
  484. if(vop_id == VOP_MODE_MIPI)
  485. {
  486. ret = device_probe(disp);
  487. if (ret) {
  488. debug("%s: device '%s' display won't probe (ret=%d)\n",
  489. __func__, dev->name, ret);
  490. return ret;
  491. }
  492. ret = video_bridge_attach(disp);
  493. if (ret) {
  494. debug("fail to attach bridge\n");
  495. return ret;
  496. }
  497. ret = video_bridge_set_backlight(disp, 80);
  498. if (ret) {
  499. debug("dp: failed to set backlight\n");
  500. return ret;
  501. }
  502. ret = uclass_first_device_err(UCLASS_PANEL, &panel);
  503. if (ret) {
  504. if (ret != -ENODEV)
  505. debug("panel device error %d\n", ret);
  506. return ret;
  507. }
  508. ret = panel_get_display_timing(panel, &timing);
  509. if (ret) {
  510. ret = ofnode_decode_display_timing(dev_ofnode(panel),
  511. 0, &timing);
  512. if (ret) {
  513. debug("decode display timing error %d\n", ret);
  514. return ret;
  515. }
  516. }
  517. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  518. if (err) {
  519. debug("failed to set %s clock as %s's parent\n",
  520. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  521. return err;
  522. }
  523. ulong new_rate = clk_set_rate(&priv->dc_pix_src, timing.pixelclock.typ);
  524. debug("new_rate %ld\n", new_rate);
  525. dc_hw_init(dev);
  526. uc_priv->xsize = timing.hactive.typ;
  527. uc_priv->ysize = timing.vactive.typ;
  528. if (IS_ENABLED(CONFIG_VIDEO_COPY))
  529. uc_plat->copy_base = uc_plat->base - uc_plat->size / 2;
  530. writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
  531. writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
  532. writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
  533. writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
  534. writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
  535. writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
  536. writel(uc_plat->base, priv->regs_hi+0x00001400);
  537. writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
  538. writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
  539. writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
  540. writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
  541. writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
  542. writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
  543. writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
  544. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  545. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  546. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  547. writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
  548. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  549. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  550. writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
  551. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  552. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  553. writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
  554. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  555. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  556. writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
  557. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  558. writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
  559. writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
  560. writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
  561. writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
  562. writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
  563. writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
  564. writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
  565. writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
  566. writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
  567. writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
  568. writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
  569. writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
  570. writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
  571. writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
  572. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  573. writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
  574. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  575. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  576. writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
  577. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  578. writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
  579. priv->mipi_logo = true;
  580. return 0;
  581. }
  582. return 0;
  583. }
  584. static int sf_vop_probe(struct udevice *dev)
  585. {
  586. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  587. struct sf_vop_priv *priv = dev_get_priv(dev);
  588. ofnode port, node;
  589. int ret;
  590. sf_vop_power(dev);
  591. mdelay(50);
  592. priv->regs_hi = dev_remap_addr_name(dev, "hi");
  593. if (!priv->regs_hi)
  594. return -EINVAL;
  595. priv->regs_low = dev_remap_addr_name(dev, "low");
  596. if (!priv->regs_low)
  597. return -EINVAL;
  598. priv->hdmi_logo = false;
  599. priv->mipi_logo = false;
  600. vout_probe_resources_jh7110(dev);
  601. port = dev_read_subnode(dev, "port");
  602. if (!ofnode_valid(port)) {
  603. debug("%s(%s): 'port' subnode not found\n",
  604. __func__, dev_read_name(dev));
  605. return -EINVAL;
  606. }
  607. for (node = ofnode_first_subnode(port);
  608. ofnode_valid(node);
  609. node = dev_read_next_subnode(node)) {
  610. ret = sf_display_init(dev, plat->base, node);
  611. if (ret)
  612. debug("Device failed: ret=%d\n", ret);
  613. if (!ret)
  614. break;
  615. }
  616. video_set_flush_dcache(dev, 1);
  617. return 0;
  618. }
  619. static int sf_vop_remove(struct udevice *dev)
  620. {
  621. struct sf_vop_priv *priv = dev_get_priv(dev);
  622. debug("sf_vop_remove-------\n");
  623. int ret;
  624. if(priv->mipi_logo == true)
  625. return 0;
  626. if(priv->hdmi_logo == false)
  627. return 0;
  628. iotrace_writel( 0x00000000, priv->regs_hi+0x1cc0 );
  629. iotrace_writel( 0x00000000, priv->regs_hi+0x24e0 );
  630. iotrace_writel( 0x00000000, priv->regs_hi+0x1810 );
  631. iotrace_writel( 0x00000000, priv->regs_hi+0x1400 );
  632. iotrace_writel( 0x00000000, priv->regs_hi+0x1408 );
  633. iotrace_writel( 0x00000000, priv->regs_hi+0x1ce8 );
  634. iotrace_writel( 0x00000000, priv->regs_hi+0x2510 );
  635. iotrace_writel( 0x00000000, priv->regs_hi+0x2508 );
  636. iotrace_writel( 0x00000000, priv->regs_hi+0x2500 );
  637. iotrace_writel( 0x00000000, priv->regs_hi+0x1518 );
  638. iotrace_writel( 0x00000000, priv->regs_hi+0x1540 );
  639. iotrace_writel( 0x00000000, priv->regs_hi+0x2540 );
  640. iotrace_writel( 0x00000000, priv->regs_hi+0x1544 );
  641. iotrace_writel( 0x00000000, priv->regs_hi+0x2544 );
  642. iotrace_writel( 0x00000000, priv->regs_hi+0x1548 );
  643. iotrace_writel( 0x00000000, priv->regs_hi+0x2548 );
  644. iotrace_writel( 0x00000000, priv->regs_hi+0x154c );
  645. iotrace_writel( 0x00000000, priv->regs_hi+0x254c );
  646. iotrace_writel( 0x00000000, priv->regs_hi+0x2518 );
  647. iotrace_writel( 0x00000e07, priv->regs_hi+0x1a28 );
  648. iotrace_writel( 0x00000000, priv->regs_hi+0x1430 );
  649. iotrace_writel( 0x00000000, priv->regs_hi+0x1438 );
  650. iotrace_writel( 0x00000000, priv->regs_hi+0x1440 );
  651. iotrace_writel( 0x00000000, priv->regs_hi+0x1448 );
  652. iotrace_writel( 0x00000000, priv->regs_hi+0x14b0 );
  653. iotrace_writel( 0x00000000, priv->regs_hi+0x1cd0 );
  654. iotrace_writel( 0x00000000, priv->regs_hi+0x14b8 );
  655. iotrace_writel( 0x00000000, priv->regs_hi+0x14d0 );
  656. iotrace_writel( 0x00000000, priv->regs_hi+0x1528 );
  657. iotrace_writel( 0x00000100, priv->regs_hi+0x1418 );
  658. iotrace_writel( 0x00000000, priv->regs_hi+0x1410 );
  659. iotrace_writel( 0x00000001, priv->regs_hi+0x2518 );
  660. iotrace_writel( 0x00000000, priv->regs_hi+0x1468 );
  661. iotrace_writel( 0x00000001, priv->regs_hi+0x1484 );
  662. iotrace_writel( 0x00000000, priv->regs_hi+0x24e8 );
  663. iotrace_writel( 0x00000001, priv->regs_hi+0x24fc );
  664. iotrace_writel( 0x00000000, priv->regs_hi+0x1ccc );
  665. ret = reset_assert(&priv->dc8200_rst_axi);
  666. if (ret) {
  667. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  668. return ret;
  669. }
  670. ret = reset_assert(&priv->dc8200_rst_core);
  671. if (ret) {
  672. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  673. return ret;
  674. }
  675. ret = reset_assert(&priv->dc8200_rst_ahb);
  676. if (ret) {
  677. pr_err("failed to assert dc8200_rst_ahb reset (ret=%d)\n", ret);
  678. return ret;
  679. }
  680. clk_set_rate(&priv->dc_pix_src, 74250000);
  681. clk_disable(&priv->hdmitx0_pixelclk);
  682. clk_disable(&priv->dc_ahb);
  683. clk_disable(&priv->dc_core);
  684. clk_disable(&priv->dc_axi);
  685. clk_disable(&priv->dc_pix1);
  686. clk_disable(&priv->dc_pix0);
  687. ret = reset_assert(&priv->rst_vout_src);
  688. if (ret) {
  689. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  690. return ret;
  691. }
  692. clk_disable(&priv->top_vout_ahb);
  693. clk_disable(&priv->top_vout_axi);
  694. clk_disable(&priv->vout_src);
  695. clk_disable(&priv->disp_axi);
  696. reset_assert(&priv->noc_disp);
  697. sf_vop_power_off(dev);
  698. return 0;
  699. }
  700. struct rkvop_driverdata rk3288_driverdata = {
  701. .features = VOP_FEATURE_OUTPUT_10BIT,
  702. };
  703. static const struct udevice_id sf_dc_ids[] = {
  704. { .compatible = "starfive,sf-dc8200",
  705. .data = (ulong)&rk3288_driverdata },
  706. { }
  707. };
  708. static const struct video_ops sf_vop_ops = {
  709. };
  710. int sf_vop_bind(struct udevice *dev)
  711. {
  712. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  713. plat->size = 4 * (CONFIG_VIDEO_STARFIVE_MAX_XRES *
  714. CONFIG_VIDEO_STARFIVE_MAX_YRES);
  715. debug("%s,%d,plat->size = %d\n",__func__,__LINE__,plat->size);
  716. return 0;
  717. }
  718. U_BOOT_DRIVER(starfive_dc8200) = {
  719. .name = "starfive_dc8200",
  720. .id = UCLASS_VIDEO,
  721. .of_match = sf_dc_ids,
  722. .ops = &sf_vop_ops,
  723. .bind = sf_vop_bind,
  724. .probe = sf_vop_probe,
  725. .remove = sf_vop_remove,
  726. .priv_auto = sizeof(struct sf_vop_priv),
  727. .flags = DM_FLAG_OS_PREPARE,
  728. };