mx6boards.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Eukréa Electromatique
  4. * Author: Eric Bénard <eric@eukrea.com>
  5. * Fabio Estevam <fabio.estevam@freescale.com>
  6. * Jon Nettleton <jon.nettleton@gmail.com>
  7. *
  8. * based on sabresd.c which is :
  9. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10. * and on hummingboard.c which is :
  11. * Copyright (C) 2013 SolidRun ltd.
  12. * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13. */
  14. #include <common.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/arch/iomux.h>
  21. #include <asm/arch/mx6-pins.h>
  22. #include <asm/global_data.h>
  23. #include <linux/delay.h>
  24. #include <linux/errno.h>
  25. #include <asm/gpio.h>
  26. #include <asm/mach-imx/iomux-v3.h>
  27. #include <asm/mach-imx/boot_mode.h>
  28. #include <asm/mach-imx/mxc_i2c.h>
  29. #include <asm/mach-imx/spi.h>
  30. #include <asm/mach-imx/video.h>
  31. #include <i2c.h>
  32. #include <input.h>
  33. #include <miiphy.h>
  34. #include <netdev.h>
  35. #include <asm/arch/mxc_hdmi.h>
  36. #include <asm/arch/crm_regs.h>
  37. #include <linux/fb.h>
  38. #include <ipu_pixfmt.h>
  39. #include <asm/io.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  45. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
  48. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  49. PAD_CTL_HYS)
  50. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52. #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
  53. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54. #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  55. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  56. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  57. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  58. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  59. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  60. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  61. static int board_type = -1;
  62. #define BOARD_IS_MARSBOARD 0
  63. #define BOARD_IS_RIOTBOARD 1
  64. int dram_init(void)
  65. {
  66. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  67. return 0;
  68. }
  69. static iomux_v3_cfg_t const uart2_pads[] = {
  70. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  71. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72. };
  73. static void setup_iomux_uart(void)
  74. {
  75. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  76. }
  77. iomux_v3_cfg_t const enet_pads[] = {
  78. /* AR8035 PHY Reset */
  79. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  80. /* AR8035 PHY Interrupt */
  81. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. };
  83. static void setup_iomux_enet(void)
  84. {
  85. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  86. /* Reset AR8035 PHY */
  87. gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
  88. mdelay(2);
  89. gpio_set_value(IMX_GPIO_NR(3, 31), 1);
  90. }
  91. int mx6_rgmii_rework(struct phy_device *phydev)
  92. {
  93. /* from linux/arch/arm/mach-imx/mach-imx6q.c :
  94. * Ar803x phy SmartEEE feature cause link status generates glitch,
  95. * which cause ethernet link down/up issue, so disable SmartEEE
  96. */
  97. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  98. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  99. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  100. return 0;
  101. }
  102. int board_phy_config(struct phy_device *phydev)
  103. {
  104. mx6_rgmii_rework(phydev);
  105. if (phydev->drv->config)
  106. phydev->drv->config(phydev);
  107. return 0;
  108. }
  109. #ifdef CONFIG_MXC_SPI
  110. iomux_v3_cfg_t const ecspi1_pads[] = {
  111. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  112. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  113. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  114. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  115. };
  116. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  117. {
  118. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  119. }
  120. static void setup_spi(void)
  121. {
  122. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  123. }
  124. #endif
  125. struct i2c_pads_info i2c_pad_info1 = {
  126. .scl = {
  127. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
  128. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  129. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
  130. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  131. .gp = IMX_GPIO_NR(5, 27)
  132. },
  133. .sda = {
  134. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
  135. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  136. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
  137. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  138. .gp = IMX_GPIO_NR(5, 26)
  139. }
  140. };
  141. struct i2c_pads_info i2c_pad_info2 = {
  142. .scl = {
  143. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
  144. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  145. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
  146. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  147. .gp = IMX_GPIO_NR(4, 12)
  148. },
  149. .sda = {
  150. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
  151. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  152. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
  153. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  154. .gp = IMX_GPIO_NR(4, 13)
  155. }
  156. };
  157. struct i2c_pads_info i2c_pad_info3 = {
  158. .scl = {
  159. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
  160. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  161. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
  162. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  163. .gp = IMX_GPIO_NR(1, 5)
  164. },
  165. .sda = {
  166. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
  167. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  168. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
  169. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  170. .gp = IMX_GPIO_NR(1, 6)
  171. }
  172. };
  173. iomux_v3_cfg_t const tft_pads_riot[] = {
  174. /* LCD_PWR_EN */
  175. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  176. /* TOUCH_INT */
  177. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  178. /* LED_PWR_EN */
  179. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  180. /* BL LEVEL */
  181. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  182. };
  183. iomux_v3_cfg_t const tft_pads_mars[] = {
  184. /* LCD_PWR_EN */
  185. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  186. /* TOUCH_INT */
  187. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  188. /* LED_PWR_EN */
  189. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  190. /* BL LEVEL (PWM4) */
  191. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  192. };
  193. #if defined(CONFIG_VIDEO_IPUV3)
  194. static void enable_lvds(struct display_info_t const *dev)
  195. {
  196. struct iomuxc *iomux = (struct iomuxc *)
  197. IOMUXC_BASE_ADDR;
  198. setbits_le32(&iomux->gpr[2],
  199. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
  200. /* set backlight level to ON */
  201. if (board_type == BOARD_IS_RIOTBOARD)
  202. gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
  203. else if (board_type == BOARD_IS_MARSBOARD)
  204. gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
  205. }
  206. static void disable_lvds(struct display_info_t const *dev)
  207. {
  208. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  209. /* set backlight level to OFF */
  210. if (board_type == BOARD_IS_RIOTBOARD)
  211. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  212. else if (board_type == BOARD_IS_MARSBOARD)
  213. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  214. clrbits_le32(&iomux->gpr[2],
  215. IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
  216. }
  217. static void do_enable_hdmi(struct display_info_t const *dev)
  218. {
  219. disable_lvds(dev);
  220. imx_enable_hdmi_phy();
  221. }
  222. static int detect_i2c(struct display_info_t const *dev)
  223. {
  224. return (0 == i2c_set_bus_num(dev->bus)) &&
  225. (0 == i2c_probe(dev->addr));
  226. }
  227. struct display_info_t const displays[] = {{
  228. .bus = -1,
  229. .addr = 0,
  230. .pixfmt = IPU_PIX_FMT_RGB24,
  231. .detect = detect_hdmi,
  232. .enable = do_enable_hdmi,
  233. .mode = {
  234. .name = "HDMI",
  235. .refresh = 60,
  236. .xres = 1024,
  237. .yres = 768,
  238. .pixclock = 15385,
  239. .left_margin = 220,
  240. .right_margin = 40,
  241. .upper_margin = 21,
  242. .lower_margin = 7,
  243. .hsync_len = 60,
  244. .vsync_len = 10,
  245. .sync = FB_SYNC_EXT,
  246. .vmode = FB_VMODE_NONINTERLACED
  247. } }, {
  248. .bus = 2,
  249. .addr = 0x1,
  250. .pixfmt = IPU_PIX_FMT_LVDS666,
  251. .detect = detect_i2c,
  252. .enable = enable_lvds,
  253. .mode = {
  254. .name = "LCD8000-97C",
  255. .refresh = 60,
  256. .xres = 1024,
  257. .yres = 768,
  258. .pixclock = 15385,
  259. .left_margin = 100,
  260. .right_margin = 200,
  261. .upper_margin = 10,
  262. .lower_margin = 20,
  263. .hsync_len = 20,
  264. .vsync_len = 8,
  265. .sync = FB_SYNC_EXT,
  266. .vmode = FB_VMODE_NONINTERLACED
  267. } } };
  268. size_t display_count = ARRAY_SIZE(displays);
  269. static void setup_display(void)
  270. {
  271. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  272. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  273. int reg;
  274. enable_ipu_clock();
  275. imx_setup_hdmi();
  276. /* Turn on LDB0, IPU,IPU DI0 clocks */
  277. setbits_le32(&mxc_ccm->CCGR3,
  278. MXC_CCM_CCGR3_LDB_DI0_MASK);
  279. /* set LDB0 clk select to 011/011 */
  280. clrsetbits_le32(&mxc_ccm->cs2cdr,
  281. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  282. (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  283. setbits_le32(&mxc_ccm->cscmr2,
  284. MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  285. setbits_le32(&mxc_ccm->chsccdr,
  286. (CHSCCDR_CLK_SEL_LDB_DI0
  287. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  288. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  289. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  290. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  291. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  292. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  293. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  294. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  295. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  296. writel(reg, &iomux->gpr[2]);
  297. clrsetbits_le32(&iomux->gpr[3],
  298. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  299. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  300. IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  301. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  302. }
  303. #endif /* CONFIG_VIDEO_IPUV3 */
  304. /*
  305. * Do not overwrite the console
  306. * Use always serial for U-Boot console
  307. */
  308. int overwrite_console(void)
  309. {
  310. return 1;
  311. }
  312. int board_early_init_f(void)
  313. {
  314. u32 cputype = cpu_type(get_cpu_rev());
  315. switch (cputype) {
  316. case MXC_CPU_MX6SOLO:
  317. board_type = BOARD_IS_RIOTBOARD;
  318. break;
  319. case MXC_CPU_MX6D:
  320. board_type = BOARD_IS_MARSBOARD;
  321. break;
  322. }
  323. setup_iomux_uart();
  324. if (board_type == BOARD_IS_RIOTBOARD)
  325. imx_iomux_v3_setup_multiple_pads(
  326. tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
  327. else if (board_type == BOARD_IS_MARSBOARD)
  328. imx_iomux_v3_setup_multiple_pads(
  329. tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
  330. #if defined(CONFIG_VIDEO_IPUV3)
  331. /* power ON LCD */
  332. gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
  333. /* touch interrupt is an input */
  334. gpio_direction_input(IMX_GPIO_NR(6, 14));
  335. /* power ON backlight */
  336. gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
  337. /* set backlight level to off */
  338. if (board_type == BOARD_IS_RIOTBOARD)
  339. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  340. else if (board_type == BOARD_IS_MARSBOARD)
  341. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  342. setup_display();
  343. #endif
  344. return 0;
  345. }
  346. int board_init(void)
  347. {
  348. /* address of boot parameters */
  349. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  350. /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
  351. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  352. /* i2c2 : HDMI EDID */
  353. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  354. /* i2c3 : LVDS, Expansion connector */
  355. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  356. #ifdef CONFIG_MXC_SPI
  357. setup_spi();
  358. #endif
  359. return 0;
  360. }
  361. #ifdef CONFIG_CMD_BMODE
  362. static const struct boot_mode riotboard_boot_modes[] = {
  363. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  364. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  365. {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  366. {NULL, 0},
  367. };
  368. static const struct boot_mode marsboard_boot_modes[] = {
  369. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  370. {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  371. {NULL, 0},
  372. };
  373. #endif
  374. int board_late_init(void)
  375. {
  376. #ifdef CONFIG_CMD_BMODE
  377. if (board_type == BOARD_IS_RIOTBOARD)
  378. add_board_boot_modes(riotboard_boot_modes);
  379. else if (board_type == BOARD_IS_RIOTBOARD)
  380. add_board_boot_modes(marsboard_boot_modes);
  381. #endif
  382. setup_iomux_enet();
  383. return 0;
  384. }
  385. int checkboard(void)
  386. {
  387. puts("Board: ");
  388. if (board_type == BOARD_IS_MARSBOARD)
  389. puts("MarSBoard\n");
  390. else if (board_type == BOARD_IS_RIOTBOARD)
  391. puts("RIoTboard\n");
  392. else
  393. printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
  394. return 0;
  395. }
  396. #ifdef CONFIG_SPL_BUILD
  397. #include <spl.h>
  398. void board_init_f(ulong dummy)
  399. {
  400. u32 cputype = cpu_type(get_cpu_rev());
  401. switch (cputype) {
  402. case MXC_CPU_MX6SOLO:
  403. board_type = BOARD_IS_RIOTBOARD;
  404. break;
  405. case MXC_CPU_MX6D:
  406. board_type = BOARD_IS_MARSBOARD;
  407. break;
  408. }
  409. arch_cpu_init();
  410. /* setup GP timer */
  411. timer_init();
  412. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  413. setup_iomux_uart();
  414. preloader_console_init();
  415. #endif
  416. }
  417. void board_boot_order(u32 *spl_boot_list)
  418. {
  419. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  420. }
  421. /*
  422. * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
  423. * to pin 3 (ground).
  424. */
  425. int spl_start_uboot(void)
  426. {
  427. int gpio_key = IMX_GPIO_NR(4, 16);
  428. gpio_direction_input(gpio_key);
  429. if (gpio_get_value(gpio_key) == 0)
  430. return 1;
  431. else
  432. return 0;
  433. }
  434. #endif