imx-regs.h 13 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. */
  19. #ifndef __ASM_ARCH_IMX_REGS_H__
  20. #define __ASM_ARCH_IMX_REGS_H__
  21. #define ARCH_MXC
  22. #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
  23. #define IRAM_SIZE 0x00080000 /* 512 KB */
  24. #define AIPS0_BASE_ADDR 0x40000000
  25. #define AIPS1_BASE_ADDR 0x40080000
  26. /* AIPS 0 */
  27. #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
  28. #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
  29. #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
  30. #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
  31. #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
  32. #define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
  33. #define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
  34. #define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
  35. #define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
  36. #define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
  37. #define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
  38. #define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
  39. #define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
  40. #define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
  41. #define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
  42. #define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
  43. #define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
  44. #define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
  45. #define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
  46. #define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
  47. #define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
  48. #define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
  49. #define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
  50. #define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
  51. #define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
  52. #define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
  53. #define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
  54. #define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
  55. #define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
  56. #define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
  57. #define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
  58. #define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
  59. #define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
  60. #define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
  61. #define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
  62. #define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
  63. #define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
  64. #define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
  65. #define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
  66. #define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
  67. #define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
  68. #define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
  69. #define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
  70. #define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
  71. #define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
  72. #define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
  73. #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
  74. #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
  75. #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
  76. #define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
  77. #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
  78. #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
  79. #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
  80. #define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
  81. #define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
  82. #define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
  83. #define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
  84. #define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
  85. #define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
  86. #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
  87. #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
  88. #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
  89. /* AIPS 1 */
  90. #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
  91. #define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
  92. #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
  93. #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
  94. #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
  95. /* MUX mode and PAD ctrl are in one register */
  96. #define CONFIG_IOMUX_SHARE_CONF_REG
  97. #define FEC_QUIRK_ENET_MAC
  98. /* MSCM interrupt rounter */
  99. #define MSCM_IRSPRC_CP0_EN 1
  100. #define MSCM_IRSPRC_NUM 112
  101. /* DDRMC */
  102. #define DDRMC_PHY_DQ_TIMING 0x00002613
  103. #define DDRMC_PHY_DQS_TIMING 0x00002615
  104. #define DDRMC_PHY_CTRL 0x01210080
  105. #define DDRMC_PHY_MASTER_CTRL 0x0001012a
  106. #define DDRMC_PHY_SLAVE_CTRL 0x00012020
  107. #define DDRMC_PHY50_DDR3_MODE (1 << 12)
  108. #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
  109. #define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
  110. #define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
  111. #define DDRMC_CR00_START 1
  112. #define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
  113. #define DDRMC_CR10_TRST_PWRON(v) (v)
  114. #define DDRMC_CR11_CKE_INACTIVE(v) (v)
  115. #define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
  116. #define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
  117. #define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
  118. #define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
  119. #define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
  120. #define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
  121. #define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
  122. #define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
  123. #define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
  124. #define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
  125. #define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
  126. #define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
  127. #define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
  128. #define DDRMC_CR17_TMOD(v) ((v) & 0xff)
  129. #define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
  130. #define DDRMC_CR18_TCKE(v) ((v) & 0x7)
  131. #define DDRMC_CR20_AP_EN (1 << 24)
  132. #define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
  133. #define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
  134. #define DDRMC_CR21_CCMAP_EN 1
  135. #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
  136. #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
  137. #define DDRMC_CR23_TDLL(v) ((v) & 0xff)
  138. #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
  139. #define DDRMC_CR25_TREF_EN (1 << 16)
  140. #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
  141. #define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
  142. #define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
  143. #define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
  144. #define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
  145. #define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
  146. #define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
  147. #define DDRMC_CR33_EN_QK_SREF (1 << 16)
  148. #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
  149. #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
  150. #define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
  151. #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
  152. #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
  153. #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
  154. #define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
  155. #define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
  156. #define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
  157. #define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
  158. #define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
  159. #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
  160. #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
  161. #define DDRMC_CR70_REF_PER_ZQ(v) (v)
  162. #define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
  163. #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
  164. #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
  165. #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
  166. #define DDRMC_CR74_BANKSPLT_EN (1 << 24)
  167. #define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
  168. #define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
  169. #define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
  170. #define DDRMC_CR75_RW_PG_EN (1 << 24)
  171. #define DDRMC_CR75_RW_EN (1 << 16)
  172. #define DDRMC_CR75_PRI_EN (1 << 8)
  173. #define DDRMC_CR75_PLEN 1
  174. #define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
  175. #define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
  176. #define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
  177. #define DDRMC_CR76_CS_EN 1
  178. #define DDRMC_CR77_CS_MAP (1 << 24)
  179. #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
  180. #define DDRMC_CR77_SWAP_EN 1
  181. #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
  182. #define DDRMC_CR79_CTLUPD_AREF (1 << 24)
  183. #define DDRMC_CR82_INT_MASK 0x1fffffff
  184. #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
  185. #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
  186. #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
  187. #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
  188. #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
  189. #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
  190. #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
  191. #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
  192. #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
  193. #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
  194. #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
  195. #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
  196. #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
  197. #define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
  198. #define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
  199. #define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
  200. #define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
  201. #define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
  202. #define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
  203. #define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
  204. #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
  205. #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
  206. #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
  207. #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
  208. #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
  209. #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
  210. #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
  211. #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
  212. #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
  213. #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
  214. #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
  215. #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
  216. #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
  217. #define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
  218. #define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
  219. #define DDRMC_CR158_TWR(v) ((v) & 0x3f)
  220. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  221. #include <asm/types.h>
  222. /* System Reset Controller (SRC) */
  223. struct src {
  224. u32 scr;
  225. u32 sbmr1;
  226. u32 srsr;
  227. u32 secr;
  228. u32 gpsr;
  229. u32 sicr;
  230. u32 simr;
  231. u32 sbmr2;
  232. u32 gpr0;
  233. u32 gpr1;
  234. u32 gpr2;
  235. u32 gpr3;
  236. u32 gpr4;
  237. u32 hab0;
  238. u32 hab1;
  239. u32 hab2;
  240. u32 hab3;
  241. u32 hab4;
  242. u32 hab5;
  243. u32 misc0;
  244. u32 misc1;
  245. u32 misc2;
  246. u32 misc3;
  247. };
  248. /* Periodic Interrupt Timer (PIT) */
  249. struct pit_reg {
  250. u32 mcr;
  251. u32 recv0[55];
  252. u32 ltmr64h;
  253. u32 ltmr64l;
  254. u32 recv1[6];
  255. u32 ldval0;
  256. u32 cval0;
  257. u32 tctrl0;
  258. u32 tflg0;
  259. u32 ldval1;
  260. u32 cval1;
  261. u32 tctrl1;
  262. u32 tflg1;
  263. u32 ldval2;
  264. u32 cval2;
  265. u32 tctrl2;
  266. u32 tflg2;
  267. u32 ldval3;
  268. u32 cval3;
  269. u32 tctrl3;
  270. u32 tflg3;
  271. u32 ldval4;
  272. u32 cval4;
  273. u32 tctrl4;
  274. u32 tflg4;
  275. u32 ldval5;
  276. u32 cval5;
  277. u32 tctrl5;
  278. u32 tflg5;
  279. u32 ldval6;
  280. u32 cval6;
  281. u32 tctrl6;
  282. u32 tflg6;
  283. u32 ldval7;
  284. u32 cval7;
  285. u32 tctrl7;
  286. u32 tflg7;
  287. };
  288. /* Watchdog Timer (WDOG) */
  289. struct wdog_regs {
  290. u16 wcr;
  291. u16 wsr;
  292. u16 wrsr;
  293. u16 wicr;
  294. u16 wmcr;
  295. };
  296. /* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
  297. struct ddrmr_regs {
  298. u32 cr[162];
  299. u32 rsvd[94];
  300. u32 phy[53];
  301. };
  302. /* On-Chip One Time Programmable Controller (OCOTP) */
  303. struct ocotp_regs {
  304. u32 ctrl;
  305. u32 ctrl_set;
  306. u32 ctrl_clr;
  307. u32 ctrl_tog;
  308. u32 timing;
  309. u32 rsvd0[3];
  310. u32 data;
  311. u32 rsvd1[3];
  312. u32 read_ctrl;
  313. u32 rsvd2[3];
  314. u32 read_fuse_data;
  315. u32 rsvd3[7];
  316. u32 scs;
  317. u32 scs_set;
  318. u32 scs_clr;
  319. u32 scs_tog;
  320. u32 crc_addr;
  321. u32 rsvd4[3];
  322. u32 crc_value;
  323. u32 rsvd5[3];
  324. u32 version;
  325. u32 rsvd6[0xdb];
  326. struct fuse_bank {
  327. u32 fuse_regs[0x20];
  328. } bank[16];
  329. };
  330. struct fuse_bank0_regs {
  331. u32 lock;
  332. u32 rsvd0[3];
  333. u32 uid_low;
  334. u32 rsvd1[3];
  335. u32 uid_high;
  336. u32 rsvd2[0x17];
  337. };
  338. struct fuse_bank4_regs {
  339. u32 sjc_resp0;
  340. u32 rsvd0[3];
  341. u32 sjc_resp1;
  342. u32 rsvd1[3];
  343. u32 mac_addr0;
  344. u32 rsvd2[3];
  345. u32 mac_addr1;
  346. u32 rsvd3[3];
  347. u32 mac_addr2;
  348. u32 rsvd4[3];
  349. u32 mac_addr3;
  350. u32 rsvd5[3];
  351. u32 gp1;
  352. u32 rsvd6[3];
  353. u32 gp2;
  354. u32 rsvd7[3];
  355. };
  356. /* UART */
  357. struct lpuart_fsl {
  358. u8 ubdh;
  359. u8 ubdl;
  360. u8 uc1;
  361. u8 uc2;
  362. u8 us1;
  363. u8 us2;
  364. u8 uc3;
  365. u8 ud;
  366. u8 uma1;
  367. u8 uma2;
  368. u8 uc4;
  369. u8 uc5;
  370. u8 ued;
  371. u8 umodem;
  372. u8 uir;
  373. u8 reserved;
  374. u8 upfifo;
  375. u8 ucfifo;
  376. u8 usfifo;
  377. u8 utwfifo;
  378. u8 utcfifo;
  379. u8 urwfifo;
  380. u8 urcfifo;
  381. u8 rsvd[28];
  382. };
  383. /* MSCM Interrupt Router */
  384. struct mscm_ir {
  385. u32 ircp0ir;
  386. u32 ircp1ir;
  387. u32 rsvd1[6];
  388. u32 ircpgir;
  389. u32 rsvd2[23];
  390. u16 irsprc[112];
  391. u16 rsvd3[848];
  392. };
  393. #endif /* __ASSEMBLER__*/
  394. #endif /* __ASM_ARCH_IMX_REGS_H__ */