crm_regs.h 5.9 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. */
  19. #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
  20. #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
  21. #ifndef __ASSEMBLY__
  22. /* Clock Controller Module (CCM) */
  23. struct ccm_reg {
  24. u32 ccr;
  25. u32 csr;
  26. u32 ccsr;
  27. u32 cacrr;
  28. u32 cscmr1;
  29. u32 cscdr1;
  30. u32 cscdr2;
  31. u32 cscdr3;
  32. u32 cscmr2;
  33. u32 cscdr4;
  34. u32 ctor;
  35. u32 clpcr;
  36. u32 cisr;
  37. u32 cimr;
  38. u32 ccosr;
  39. u32 cgpr;
  40. u32 ccgr0;
  41. u32 ccgr1;
  42. u32 ccgr2;
  43. u32 ccgr3;
  44. u32 ccgr4;
  45. u32 ccgr5;
  46. u32 ccgr6;
  47. u32 ccgr7;
  48. u32 ccgr8;
  49. u32 ccgr9;
  50. u32 ccgr10;
  51. u32 ccgr11;
  52. u32 cmeor0;
  53. u32 cmeor1;
  54. u32 cmeor2;
  55. u32 cmeor3;
  56. u32 cmeor4;
  57. u32 cmeor5;
  58. u32 cppdsr;
  59. u32 ccowr;
  60. u32 ccpgr0;
  61. u32 ccpgr1;
  62. u32 ccpgr2;
  63. u32 ccpgr3;
  64. };
  65. /* Analog components control digital interface (ANADIG) */
  66. struct anadig_reg {
  67. u32 pll3_ctrl;
  68. u32 resv0[3];
  69. u32 pll7_ctrl;
  70. u32 resv1[3];
  71. u32 pll2_ctrl;
  72. u32 resv2[3];
  73. u32 pll2_ss;
  74. u32 resv3[3];
  75. u32 pll2_num;
  76. u32 resv4[3];
  77. u32 pll2_denom;
  78. u32 resv5[3];
  79. u32 pll4_ctrl;
  80. u32 resv6[3];
  81. u32 pll4_num;
  82. u32 resv7[3];
  83. u32 pll4_denom;
  84. u32 pll6_ctrl;
  85. u32 resv8[3];
  86. u32 pll6_num;
  87. u32 resv9[3];
  88. u32 pll6_denom;
  89. u32 resv10[3];
  90. u32 pll5_ctrl;
  91. u32 resv11[3];
  92. u32 pll3_pfd;
  93. u32 resv12[3];
  94. u32 pll2_pfd;
  95. u32 resv13[3];
  96. u32 reg_1p1;
  97. u32 resv14[3];
  98. u32 reg_3p0;
  99. u32 resv15[3];
  100. u32 reg_2p5;
  101. u32 resv16[7];
  102. u32 ana_misc0;
  103. u32 resv17[3];
  104. u32 ana_misc1;
  105. u32 resv18[63];
  106. u32 anadig_digprog;
  107. u32 resv19[3];
  108. u32 pll1_ctrl;
  109. u32 resv20[3];
  110. u32 pll1_ss;
  111. u32 resv21[3];
  112. u32 pll1_num;
  113. u32 resv22[3];
  114. u32 pll1_denom;
  115. u32 resv23[3];
  116. u32 pll1_pdf;
  117. u32 resv24[3];
  118. u32 pll_lock;
  119. };
  120. #endif
  121. #define CCM_CCR_FIRC_EN (1 << 16)
  122. #define CCM_CCR_OSCNT_MASK 0xff
  123. #define CCM_CCR_OSCNT(v) ((v) & 0xff)
  124. #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
  125. #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
  126. #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
  127. #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
  128. #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
  129. #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
  130. #define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
  131. #define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
  132. #define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
  133. #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
  134. #define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
  135. #define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
  136. #define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
  137. #define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
  138. #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
  139. #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
  140. #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
  141. #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
  142. #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
  143. #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
  144. #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
  145. #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
  146. #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
  147. #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
  148. #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
  149. #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
  150. #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
  151. #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
  152. #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
  153. #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
  154. #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
  155. #define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
  156. #define CCM_CSCDR2_ESDHC1_EN (1 << 29)
  157. #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
  158. #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
  159. #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
  160. #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
  161. #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
  162. #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
  163. #define CCM_REG_CTRL_MASK 0xffffffff
  164. #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
  165. #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
  166. #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
  167. #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
  168. #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
  169. #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
  170. #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
  171. #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
  172. #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
  173. #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
  174. #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
  175. #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
  176. #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
  177. #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
  178. #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
  179. #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
  180. #define CCM_CCGR9_FEC0_CTRL_MASK 0x3
  181. #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
  182. #define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
  183. #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
  184. #define ANADIG_PLL2_CTRL_DIV_SELECT 1
  185. #define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
  186. #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
  187. #define ANADIG_PLL1_CTRL_DIV_SELECT 1
  188. #define FASE_CLK_FREQ 24000000
  189. #define SLOW_CLK_FREQ 32000
  190. #define PLL1_PFD1_FREQ 500000000
  191. #define PLL1_PFD2_FREQ 452000000
  192. #define PLL1_PFD3_FREQ 396000000
  193. #define PLL1_PFD4_FREQ 528000000
  194. #define PLL1_MAIN_FREQ 528000000
  195. #define PLL2_PFD1_FREQ 500000000
  196. #define PLL2_PFD2_FREQ 396000000
  197. #define PLL2_PFD3_FREQ 339000000
  198. #define PLL2_PFD4_FREQ 413000000
  199. #define PLL2_MAIN_FREQ 528000000
  200. #define PLL3_MAIN_FREQ 480000000
  201. #define PLL3_PFD3_FREQ 298000000
  202. #define PLL5_MAIN_FREQ 500000000
  203. #define ENET_EXTERNAL_CLK 50000000
  204. #define AUDIO_EXTERNAL_CLK 24576000
  205. #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */