generic.c 6.9 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. */
  19. #include <common.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/imx-regs.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <netdev.h>
  25. #ifdef CONFIG_FSL_ESDHC
  26. #include <fsl_esdhc.h>
  27. #endif
  28. #ifdef CONFIG_FSL_ESDHC
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #endif
  31. #ifdef CONFIG_MXC_OCOTP
  32. void enable_ocotp_clk(unsigned char enable)
  33. {
  34. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  35. u32 reg;
  36. reg = readl(&ccm->ccgr6);
  37. if (enable)
  38. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  39. else
  40. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  41. writel(reg, &ccm->ccgr6);
  42. }
  43. #endif
  44. static u32 get_mcu_main_clk(void)
  45. {
  46. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  47. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  48. u32 sysclk_sel, pll_pfd_sel = 0;
  49. u32 freq = 0;
  50. ccm_ccsr = readl(&ccm->ccsr);
  51. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  52. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  53. ccm_cacrr = readl(&ccm->cacrr);
  54. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  55. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  56. armclk_div += 1;
  57. switch (sysclk_sel) {
  58. case 0:
  59. freq = FASE_CLK_FREQ;
  60. break;
  61. case 1:
  62. freq = SLOW_CLK_FREQ;
  63. break;
  64. case 2:
  65. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  66. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  67. if (pll_pfd_sel == 0)
  68. freq = PLL2_MAIN_FREQ;
  69. else if (pll_pfd_sel == 1)
  70. freq = PLL2_PFD1_FREQ;
  71. else if (pll_pfd_sel == 2)
  72. freq = PLL2_PFD2_FREQ;
  73. else if (pll_pfd_sel == 3)
  74. freq = PLL2_PFD3_FREQ;
  75. else if (pll_pfd_sel == 4)
  76. freq = PLL2_PFD4_FREQ;
  77. break;
  78. case 3:
  79. freq = PLL2_MAIN_FREQ;
  80. break;
  81. case 4:
  82. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  83. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  84. if (pll_pfd_sel == 0)
  85. freq = PLL1_MAIN_FREQ;
  86. else if (pll_pfd_sel == 1)
  87. freq = PLL1_PFD1_FREQ;
  88. else if (pll_pfd_sel == 2)
  89. freq = PLL1_PFD2_FREQ;
  90. else if (pll_pfd_sel == 3)
  91. freq = PLL1_PFD3_FREQ;
  92. else if (pll_pfd_sel == 4)
  93. freq = PLL1_PFD4_FREQ;
  94. break;
  95. case 5:
  96. freq = PLL3_MAIN_FREQ;
  97. break;
  98. default:
  99. printf("unsupported system clock select\n");
  100. }
  101. return freq / armclk_div;
  102. }
  103. static u32 get_bus_clk(void)
  104. {
  105. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  106. u32 ccm_cacrr, busclk_div;
  107. ccm_cacrr = readl(&ccm->cacrr);
  108. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  109. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  110. busclk_div += 1;
  111. return get_mcu_main_clk() / busclk_div;
  112. }
  113. static u32 get_ipg_clk(void)
  114. {
  115. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  116. u32 ccm_cacrr, ipgclk_div;
  117. ccm_cacrr = readl(&ccm->cacrr);
  118. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  119. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  120. ipgclk_div += 1;
  121. return get_bus_clk() / ipgclk_div;
  122. }
  123. static u32 get_uart_clk(void)
  124. {
  125. return get_ipg_clk();
  126. }
  127. static u32 get_sdhc_clk(void)
  128. {
  129. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  130. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  131. u32 freq = 0;
  132. ccm_cscmr1 = readl(&ccm->cscmr1);
  133. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  134. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  135. ccm_cscdr2 = readl(&ccm->cscdr2);
  136. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  137. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  138. sdhc_clk_div += 1;
  139. switch (sdhc_clk_sel) {
  140. case 0:
  141. freq = PLL3_MAIN_FREQ;
  142. break;
  143. case 1:
  144. freq = PLL3_PFD3_FREQ;
  145. break;
  146. case 2:
  147. freq = PLL1_PFD3_FREQ;
  148. break;
  149. case 3:
  150. freq = get_bus_clk();
  151. break;
  152. }
  153. return freq / sdhc_clk_div;
  154. }
  155. u32 get_fec_clk(void)
  156. {
  157. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  158. u32 ccm_cscmr2, rmii_clk_sel;
  159. u32 freq = 0;
  160. ccm_cscmr2 = readl(&ccm->cscmr2);
  161. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  162. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  163. switch (rmii_clk_sel) {
  164. case 0:
  165. freq = ENET_EXTERNAL_CLK;
  166. break;
  167. case 1:
  168. freq = AUDIO_EXTERNAL_CLK;
  169. break;
  170. case 2:
  171. freq = PLL5_MAIN_FREQ;
  172. break;
  173. case 3:
  174. freq = PLL5_MAIN_FREQ / 2;
  175. break;
  176. }
  177. return freq;
  178. }
  179. unsigned int mxc_get_clock(enum mxc_clock clk)
  180. {
  181. switch (clk) {
  182. case MXC_ARM_CLK:
  183. return get_mcu_main_clk();
  184. case MXC_BUS_CLK:
  185. return get_bus_clk();
  186. case MXC_IPG_CLK:
  187. return get_ipg_clk();
  188. case MXC_UART_CLK:
  189. return get_uart_clk();
  190. case MXC_ESDHC_CLK:
  191. return get_sdhc_clk();
  192. case MXC_FEC_CLK:
  193. return get_fec_clk();
  194. default:
  195. break;
  196. }
  197. return -1;
  198. }
  199. /* Dump some core clocks */
  200. int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  201. char * const argv[])
  202. {
  203. printf("\n");
  204. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  205. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  206. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  207. return 0;
  208. }
  209. U_BOOT_CMD(
  210. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  211. "display clocks",
  212. ""
  213. );
  214. #ifdef CONFIG_FEC_MXC
  215. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  216. {
  217. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  218. struct fuse_bank *bank = &ocotp->bank[4];
  219. struct fuse_bank4_regs *fuse =
  220. (struct fuse_bank4_regs *)bank->fuse_regs;
  221. u32 value = readl(&fuse->mac_addr0);
  222. mac[0] = (value >> 8);
  223. mac[1] = value;
  224. value = readl(&fuse->mac_addr1);
  225. mac[2] = value >> 24;
  226. mac[3] = value >> 16;
  227. mac[4] = value >> 8;
  228. mac[5] = value;
  229. }
  230. #endif
  231. #if defined(CONFIG_DISPLAY_CPUINFO)
  232. static char *get_reset_cause(void)
  233. {
  234. u32 cause;
  235. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  236. cause = readl(&src_regs->srsr);
  237. writel(cause, &src_regs->srsr);
  238. cause &= 0xff;
  239. switch (cause) {
  240. case 0x08:
  241. return "WDOG";
  242. case 0x20:
  243. return "JTAG HIGH-Z";
  244. case 0x80:
  245. return "EXTERNAL RESET";
  246. case 0xfd:
  247. return "POR";
  248. default:
  249. return "unknown reset";
  250. }
  251. }
  252. int print_cpuinfo(void)
  253. {
  254. printf("CPU: Freescale Vybrid VF610 at %d MHz\n",
  255. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  256. printf("Reset cause: %s\n", get_reset_cause());
  257. return 0;
  258. }
  259. #endif
  260. int cpu_eth_init(bd_t *bis)
  261. {
  262. int rc = -ENODEV;
  263. #if defined(CONFIG_FEC_MXC)
  264. rc = fecmxc_initialize(bis);
  265. #endif
  266. return rc;
  267. }
  268. #ifdef CONFIG_FSL_ESDHC
  269. int cpu_mmc_init(bd_t *bis)
  270. {
  271. return fsl_esdhc_mmc_init(bis);
  272. }
  273. #endif
  274. int get_clocks(void)
  275. {
  276. #ifdef CONFIG_FSL_ESDHC
  277. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  278. #endif
  279. return 0;
  280. }