pci.h 64 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. */
  9. #ifndef _PCI_H
  10. #define _PCI_H
  11. #define PCI_CFG_SPACE_SIZE 256
  12. #define PCI_CFG_SPACE_EXP_SIZE 4096
  13. /*
  14. * Under PCI, each device has 256 bytes of configuration address space,
  15. * of which the first 64 bytes are standardized as follows:
  16. */
  17. #define PCI_STD_HEADER_SIZEOF 64
  18. #define PCI_VENDOR_ID 0x00 /* 16 bits */
  19. #define PCI_DEVICE_ID 0x02 /* 16 bits */
  20. #define PCI_COMMAND 0x04 /* 16 bits */
  21. #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
  22. #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
  23. #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
  24. #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
  25. #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
  26. #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
  27. #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
  28. #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
  29. #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
  30. #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
  31. #define PCI_STATUS 0x06 /* 16 bits */
  32. #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
  33. #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
  34. #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
  35. #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
  36. #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
  37. #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
  38. #define PCI_STATUS_DEVSEL_FAST 0x000
  39. #define PCI_STATUS_DEVSEL_MEDIUM 0x200
  40. #define PCI_STATUS_DEVSEL_SLOW 0x400
  41. #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  42. #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  43. #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  44. #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  45. #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  46. #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
  47. revision */
  48. #define PCI_REVISION_ID 0x08 /* Revision ID */
  49. #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
  50. #define PCI_CLASS_DEVICE 0x0a /* Device class */
  51. #define PCI_CLASS_CODE 0x0b /* Device class code */
  52. #define PCI_CLASS_CODE_TOO_OLD 0x00
  53. #define PCI_CLASS_CODE_STORAGE 0x01
  54. #define PCI_CLASS_CODE_NETWORK 0x02
  55. #define PCI_CLASS_CODE_DISPLAY 0x03
  56. #define PCI_CLASS_CODE_MULTIMEDIA 0x04
  57. #define PCI_CLASS_CODE_MEMORY 0x05
  58. #define PCI_CLASS_CODE_BRIDGE 0x06
  59. #define PCI_CLASS_CODE_COMM 0x07
  60. #define PCI_CLASS_CODE_PERIPHERAL 0x08
  61. #define PCI_CLASS_CODE_INPUT 0x09
  62. #define PCI_CLASS_CODE_DOCKING 0x0A
  63. #define PCI_CLASS_CODE_PROCESSOR 0x0B
  64. #define PCI_CLASS_CODE_SERIAL 0x0C
  65. #define PCI_CLASS_CODE_WIRELESS 0x0D
  66. #define PCI_CLASS_CODE_I2O 0x0E
  67. #define PCI_CLASS_CODE_SATELLITE 0x0F
  68. #define PCI_CLASS_CODE_CRYPTO 0x10
  69. #define PCI_CLASS_CODE_DATA 0x11
  70. /* Base Class 0x12 - 0xFE is reserved */
  71. #define PCI_CLASS_CODE_OTHER 0xFF
  72. #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
  73. #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
  74. #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
  75. #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
  76. #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
  77. #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
  78. #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
  79. #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
  80. #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
  81. #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
  82. #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
  83. #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
  84. #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
  85. #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
  86. #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
  87. #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
  88. #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
  89. #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
  90. #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
  91. #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
  92. #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
  93. #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
  94. #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
  95. #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
  96. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
  97. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
  98. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
  99. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
  100. #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
  101. #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
  102. #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
  103. #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
  104. #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
  105. #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
  106. #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
  107. #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
  108. #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
  109. #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
  110. #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
  111. #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
  112. #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
  113. #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
  114. #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
  115. #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
  116. #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
  117. #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
  118. #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
  119. #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
  120. #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
  121. #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
  122. #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
  123. #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
  124. #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
  125. #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
  126. #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
  127. #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
  128. #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
  129. #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
  130. #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
  131. #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
  132. #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
  133. #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
  134. #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
  135. #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
  136. #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
  137. #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
  138. #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
  139. #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
  140. #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
  141. #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
  142. #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
  143. #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
  144. #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
  145. #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
  146. #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
  147. #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
  148. #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
  149. #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
  150. #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
  151. #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
  152. #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
  153. #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
  154. #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
  155. #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
  156. #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
  157. #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
  158. #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
  159. #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
  160. #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
  161. #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
  162. #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
  163. #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
  164. #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
  165. #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
  166. #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
  167. #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
  168. #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
  169. #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
  170. #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
  171. #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
  172. #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
  173. #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
  174. #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
  175. #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
  176. #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
  177. #define PCI_HEADER_TYPE 0x0e /* 8 bits */
  178. #define PCI_HEADER_TYPE_NORMAL 0
  179. #define PCI_HEADER_TYPE_BRIDGE 1
  180. #define PCI_HEADER_TYPE_CARDBUS 2
  181. #define PCI_BIST 0x0f /* 8 bits */
  182. #define PCI_BIST_CODE_MASK 0x0f /* Return result */
  183. #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
  184. #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
  185. /*
  186. * Base addresses specify locations in memory or I/O space.
  187. * Decoded size can be determined by writing a value of
  188. * 0xffffffff to the register, and reading it back. Only
  189. * 1 bits are decoded.
  190. */
  191. #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
  192. #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
  193. #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
  194. #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
  195. #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
  196. #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
  197. #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
  198. #define PCI_BASE_ADDRESS_SPACE_IO 0x01
  199. #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  200. #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  201. #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
  202. #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
  203. #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
  204. #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
  205. #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
  206. #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
  207. /* bit 1 is reserved if address_space = 1 */
  208. /* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
  209. #define pci_offset_to_barnum(offset) \
  210. (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
  211. /* Header type 0 (normal devices) */
  212. #define PCI_CARDBUS_CIS 0x28
  213. #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  214. #define PCI_SUBSYSTEM_ID 0x2e
  215. #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
  216. #define PCI_ROM_ADDRESS_ENABLE 0x01
  217. #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
  218. #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
  219. /* 0x35-0x3b are reserved */
  220. #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
  221. #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
  222. #define PCI_MIN_GNT 0x3e /* 8 bits */
  223. #define PCI_MAX_LAT 0x3f /* 8 bits */
  224. #define PCI_INTERRUPT_LINE_DISABLE 0xff
  225. /* Header type 1 (PCI-to-PCI bridges) */
  226. #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
  227. #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
  228. #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
  229. #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
  230. #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
  231. #define PCI_IO_LIMIT 0x1d
  232. #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
  233. #define PCI_IO_RANGE_TYPE_16 0x00
  234. #define PCI_IO_RANGE_TYPE_32 0x01
  235. #define PCI_IO_RANGE_MASK ~0x0f
  236. #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
  237. #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
  238. #define PCI_MEMORY_LIMIT 0x22
  239. #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
  240. #define PCI_MEMORY_RANGE_MASK ~0x0f
  241. #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
  242. #define PCI_PREF_MEMORY_LIMIT 0x26
  243. #define PCI_PREF_RANGE_TYPE_MASK 0x0f
  244. #define PCI_PREF_RANGE_TYPE_32 0x00
  245. #define PCI_PREF_RANGE_TYPE_64 0x01
  246. #define PCI_PREF_RANGE_MASK ~0x0f
  247. #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
  248. #define PCI_PREF_LIMIT_UPPER32 0x2c
  249. #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
  250. #define PCI_IO_LIMIT_UPPER16 0x32
  251. /* 0x34 same as for htype 0 */
  252. /* 0x35-0x3b is reserved */
  253. #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
  254. /* 0x3c-0x3d are same as for htype 0 */
  255. #define PCI_BRIDGE_CONTROL 0x3e
  256. #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
  257. #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
  258. #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
  259. #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
  260. #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
  261. #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
  262. #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
  263. /* Header type 2 (CardBus bridges) */
  264. #define PCI_CB_CAPABILITY_LIST 0x14
  265. /* 0x15 reserved */
  266. #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
  267. #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
  268. #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
  269. #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
  270. #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
  271. #define PCI_CB_MEMORY_BASE_0 0x1c
  272. #define PCI_CB_MEMORY_LIMIT_0 0x20
  273. #define PCI_CB_MEMORY_BASE_1 0x24
  274. #define PCI_CB_MEMORY_LIMIT_1 0x28
  275. #define PCI_CB_IO_BASE_0 0x2c
  276. #define PCI_CB_IO_BASE_0_HI 0x2e
  277. #define PCI_CB_IO_LIMIT_0 0x30
  278. #define PCI_CB_IO_LIMIT_0_HI 0x32
  279. #define PCI_CB_IO_BASE_1 0x34
  280. #define PCI_CB_IO_BASE_1_HI 0x36
  281. #define PCI_CB_IO_LIMIT_1 0x38
  282. #define PCI_CB_IO_LIMIT_1_HI 0x3a
  283. #define PCI_CB_IO_RANGE_MASK ~0x03
  284. /* 0x3c-0x3d are same as for htype 0 */
  285. #define PCI_CB_BRIDGE_CONTROL 0x3e
  286. #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
  287. #define PCI_CB_BRIDGE_CTL_SERR 0x02
  288. #define PCI_CB_BRIDGE_CTL_ISA 0x04
  289. #define PCI_CB_BRIDGE_CTL_VGA 0x08
  290. #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
  291. #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
  292. #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
  293. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
  294. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  295. #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
  296. #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
  297. #define PCI_CB_SUBSYSTEM_ID 0x42
  298. #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
  299. /* 0x48-0x7f reserved */
  300. /* Capability lists */
  301. #define PCI_CAP_LIST_ID 0 /* Capability ID */
  302. #define PCI_CAP_ID_PM 0x01 /* Power Management */
  303. #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
  304. #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
  305. #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
  306. #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
  307. #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
  308. #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
  309. #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
  310. #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
  311. #define PCI_CAP_ID_DBG 0x0A /* Debug port */
  312. #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
  313. #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
  314. #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
  315. #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
  316. #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
  317. #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
  318. #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
  319. #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
  320. #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
  321. #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
  322. #define PCI_CAP_ID_MAX PCI_CAP_ID_EA
  323. #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
  324. #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
  325. #define PCI_CAP_SIZEOF 4
  326. /* Power Management Registers */
  327. #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
  328. #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
  329. #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
  330. #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
  331. #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
  332. #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
  333. #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
  334. #define PCI_PM_CTRL 4 /* PM control and status register */
  335. #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
  336. #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
  337. #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
  338. #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
  339. #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
  340. #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
  341. #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
  342. #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
  343. #define PCI_PM_DATA_REGISTER 7 /* (??) */
  344. #define PCI_PM_SIZEOF 8
  345. /* AGP registers */
  346. #define PCI_AGP_VERSION 2 /* BCD version number */
  347. #define PCI_AGP_RFU 3 /* Rest of capability flags */
  348. #define PCI_AGP_STATUS 4 /* Status register */
  349. #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
  350. #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
  351. #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
  352. #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
  353. #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
  354. #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
  355. #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
  356. #define PCI_AGP_COMMAND 8 /* Control register */
  357. #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
  358. #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
  359. #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
  360. #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
  361. #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
  362. #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
  363. #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
  364. #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
  365. #define PCI_AGP_SIZEOF 12
  366. /* PCI-X registers */
  367. #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
  368. #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
  369. #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
  370. #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
  371. #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
  372. /* Slot Identification */
  373. #define PCI_SID_ESR 2 /* Expansion Slot Register */
  374. #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
  375. #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
  376. #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
  377. /* Message Signalled Interrupts registers */
  378. #define PCI_MSI_FLAGS 2 /* Various flags */
  379. #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
  380. #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
  381. #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
  382. #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
  383. #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
  384. #define PCI_MSI_RFU 3 /* Rest of capability flags */
  385. #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
  386. #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  387. #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
  388. #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
  389. #define PCI_MAX_PCI_DEVICES 32
  390. #define PCI_MAX_PCI_FUNCTIONS 8
  391. #define PCI_FIND_CAP_TTL 0x48
  392. #define CAP_START_POS 0x40
  393. /* Extended Capabilities (PCI-X 2.0 and Express) */
  394. #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
  395. #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
  396. #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
  397. #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
  398. #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
  399. #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
  400. #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
  401. #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
  402. #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
  403. #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
  404. #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
  405. #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
  406. #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
  407. #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
  408. #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
  409. #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
  410. #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
  411. #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
  412. #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
  413. #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
  414. #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
  415. #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
  416. #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
  417. #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
  418. #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
  419. #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
  420. #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
  421. #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
  422. #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
  423. #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
  424. #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
  425. #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
  426. #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
  427. #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
  428. /* Enhanced Allocation Registers */
  429. #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
  430. #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
  431. #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
  432. #define PCI_EA_ES 0x00000007 /* Entry Size */
  433. #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
  434. /* 9-14 map to VF BARs 0-5 respectively */
  435. #define PCI_EA_BEI_VF_BAR0 9
  436. #define PCI_EA_BEI_VF_BAR5 14
  437. /* Base, MaxOffset registers */
  438. /* bit 0 is reserved */
  439. #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
  440. #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
  441. /* PCI Express capabilities */
  442. #define PCI_EXP_FLAGS 2 /* Capabilities register */
  443. #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
  444. #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
  445. #define PCI_EXP_DEVCAP 4 /* Device capabilities */
  446. #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
  447. #define PCI_EXP_DEVCTL 8 /* Device Control */
  448. #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
  449. #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
  450. #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
  451. #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
  452. #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
  453. #define PCI_EXP_LNKSTA 18 /* Link Status */
  454. #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
  455. #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
  456. #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
  457. #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
  458. #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
  459. #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
  460. #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
  461. #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
  462. #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
  463. #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
  464. #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
  465. #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
  466. #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
  467. #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
  468. /* Single Root I/O Virtualization Registers */
  469. #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
  470. #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
  471. #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
  472. #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
  473. #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
  474. #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
  475. #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
  476. #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
  477. #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
  478. #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
  479. #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
  480. /* Include the ID list */
  481. #include <pci_ids.h>
  482. #ifndef __ASSEMBLY__
  483. #include <dm/pci.h>
  484. #ifdef CONFIG_SYS_PCI_64BIT
  485. typedef u64 pci_addr_t;
  486. typedef u64 pci_size_t;
  487. #else
  488. typedef unsigned long pci_addr_t;
  489. typedef unsigned long pci_size_t;
  490. #endif
  491. struct pci_region {
  492. pci_addr_t bus_start; /* Start on the bus */
  493. phys_addr_t phys_start; /* Start in physical address space */
  494. pci_size_t size; /* Size */
  495. unsigned long flags; /* Resource flags */
  496. pci_addr_t bus_lower;
  497. };
  498. #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
  499. #define PCI_REGION_IO 0x00000001 /* PCI IO space */
  500. #define PCI_REGION_TYPE 0x00000001
  501. #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
  502. #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
  503. #define PCI_REGION_RO 0x00000200 /* Read-only memory */
  504. static inline void pci_set_region(struct pci_region *reg,
  505. pci_addr_t bus_start,
  506. phys_addr_t phys_start,
  507. pci_size_t size,
  508. unsigned long flags) {
  509. reg->bus_start = bus_start;
  510. reg->phys_start = phys_start;
  511. reg->size = size;
  512. reg->flags = flags;
  513. }
  514. typedef int pci_dev_t;
  515. #define PCI_BUS(d) (((d) >> 16) & 0xff)
  516. /*
  517. * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
  518. * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
  519. * Please see the Linux header include/uapi/linux/pci.h for more details.
  520. * This is relevant for the following macros:
  521. * PCI_DEV, PCI_FUNC, PCI_DEVFN
  522. * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
  523. * the remark from above (input is in bits 15-8 instead of 7-0.
  524. */
  525. #define PCI_DEV(d) (((d) >> 11) & 0x1f)
  526. #define PCI_FUNC(d) (((d) >> 8) & 0x7)
  527. #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
  528. #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
  529. #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
  530. #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
  531. #define PCI_ANY_ID (~0)
  532. /* Convert from Linux format to U-Boot format */
  533. #define PCI_TO_BDF(val) ((val) << 8)
  534. struct pci_device_id {
  535. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  536. unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
  537. unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
  538. unsigned long driver_data; /* Data private to the driver */
  539. };
  540. struct pci_controller;
  541. struct pci_config_table {
  542. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  543. unsigned int class; /* Class ID, or PCI_ANY_ID */
  544. unsigned int bus; /* Bus number, or PCI_ANY_ID */
  545. unsigned int dev; /* Device number, or PCI_ANY_ID */
  546. unsigned int func; /* Function number, or PCI_ANY_ID */
  547. void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
  548. struct pci_config_table *);
  549. unsigned long priv[3];
  550. };
  551. extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
  552. struct pci_config_table *);
  553. extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
  554. struct pci_config_table *);
  555. #define INDIRECT_TYPE_NO_PCIE_LINK 1
  556. /**
  557. * Structure of a PCI controller (host bridge)
  558. *
  559. * With driver model this is dev_get_uclass_priv(bus)
  560. *
  561. * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
  562. * relocated. Normally if PCI is used before relocation, this happens
  563. * before relocation also. Some platforms set up static configuration in
  564. * TPL/SPL to reduce code size and boot time, since these phases only know
  565. * about a small subset of PCI devices. This is normally false.
  566. */
  567. struct pci_controller {
  568. struct udevice *bus;
  569. struct udevice *ctlr;
  570. bool skip_auto_config_until_reloc;
  571. int first_busno;
  572. int last_busno;
  573. volatile unsigned int *cfg_addr;
  574. volatile unsigned char *cfg_data;
  575. int indirect_type;
  576. /*
  577. * TODO(sjg@chromium.org): With driver model we use struct
  578. * pci_controller for both the controller and any bridge devices
  579. * attached to it. But there is only one region list and it is in the
  580. * top-level controller.
  581. *
  582. * This could be changed so that struct pci_controller is only used
  583. * for PCI controllers and a separate UCLASS (or perhaps
  584. * UCLASS_PCI_GENERIC) is used for bridges.
  585. */
  586. struct pci_region *regions;
  587. int region_count;
  588. struct pci_config_table *config_table;
  589. void (*fixup_irq)(struct pci_controller *, pci_dev_t);
  590. /* Used by auto config */
  591. struct pci_region *pci_mem, *pci_io, *pci_prefetch;
  592. };
  593. #if defined(CONFIG_DM_PCI_COMPAT)
  594. extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
  595. pci_addr_t addr, unsigned long flags);
  596. extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
  597. phys_addr_t addr, unsigned long flags);
  598. #define pci_phys_to_bus(dev, addr, flags) \
  599. pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  600. #define pci_bus_to_phys(dev, addr, flags) \
  601. pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  602. #define pci_virt_to_bus(dev, addr, flags) \
  603. pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
  604. (virt_to_phys(addr)), (flags))
  605. #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
  606. map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
  607. (addr), (flags)), \
  608. (len), (map_flags))
  609. #define pci_phys_to_mem(dev, addr) \
  610. pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
  611. #define pci_mem_to_phys(dev, addr) \
  612. pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
  613. #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
  614. #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
  615. #define pci_virt_to_mem(dev, addr) \
  616. pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
  617. #define pci_mem_to_virt(dev, addr, len, map_flags) \
  618. pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
  619. #define pci_virt_to_io(dev, addr) \
  620. pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
  621. #define pci_io_to_virt(dev, addr, len, map_flags) \
  622. pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
  623. /* For driver model these are defined in macros in pci_compat.c */
  624. extern int pci_hose_read_config_byte(struct pci_controller *hose,
  625. pci_dev_t dev, int where, u8 *val);
  626. extern int pci_hose_read_config_word(struct pci_controller *hose,
  627. pci_dev_t dev, int where, u16 *val);
  628. extern int pci_hose_read_config_dword(struct pci_controller *hose,
  629. pci_dev_t dev, int where, u32 *val);
  630. extern int pci_hose_write_config_byte(struct pci_controller *hose,
  631. pci_dev_t dev, int where, u8 val);
  632. extern int pci_hose_write_config_word(struct pci_controller *hose,
  633. pci_dev_t dev, int where, u16 val);
  634. extern int pci_hose_write_config_dword(struct pci_controller *hose,
  635. pci_dev_t dev, int where, u32 val);
  636. #endif
  637. void pciauto_region_init(struct pci_region *res);
  638. void pciauto_region_align(struct pci_region *res, pci_size_t size);
  639. void pciauto_config_init(struct pci_controller *hose);
  640. /**
  641. * pciauto_region_allocate() - Allocate resources from a PCI resource region
  642. *
  643. * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
  644. * false, the result will be guaranteed to fit in 32 bits.
  645. *
  646. * @res: PCI region to allocate from
  647. * @size: Amount of bytes to allocate
  648. * @bar: Returns the PCI bus address of the allocated resource
  649. * @supports_64bit: Whether to allow allocations above the 32-bit boundary
  650. * @return 0 if successful, -1 on failure
  651. */
  652. int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  653. pci_addr_t *bar, bool supports_64bit);
  654. #if defined(CONFIG_DM_PCI_COMPAT)
  655. extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
  656. pci_dev_t dev, int where, u8 *val);
  657. extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
  658. pci_dev_t dev, int where, u16 *val);
  659. extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
  660. pci_dev_t dev, int where, u8 val);
  661. extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
  662. pci_dev_t dev, int where, u16 val);
  663. extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
  664. extern void pci_register_hose(struct pci_controller* hose);
  665. extern struct pci_controller* pci_bus_to_hose(int bus);
  666. extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
  667. extern struct pci_controller *pci_get_hose_head(void);
  668. extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
  669. extern int pci_hose_scan(struct pci_controller *hose);
  670. extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
  671. extern void pciauto_setup_device(struct pci_controller *hose,
  672. pci_dev_t dev, int bars_num,
  673. struct pci_region *mem,
  674. struct pci_region *prefetch,
  675. struct pci_region *io);
  676. extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  677. pci_dev_t dev, int sub_bus);
  678. extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  679. pci_dev_t dev, int sub_bus);
  680. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  681. extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
  682. extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
  683. pci_dev_t pci_find_class(unsigned int find_class, int index);
  684. extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
  685. int cap);
  686. extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
  687. u8 hdr_type);
  688. extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
  689. int cap);
  690. int pci_find_next_ext_capability(struct pci_controller *hose,
  691. pci_dev_t dev, int start, int cap);
  692. int pci_hose_find_ext_capability(struct pci_controller *hose,
  693. pci_dev_t dev, int cap);
  694. #endif /* defined(CONFIG_DM_PCI_COMPAT) */
  695. const char * pci_class_str(u8 class);
  696. int pci_last_busno(void);
  697. #ifdef CONFIG_MPC85xx
  698. extern void pci_mpc85xx_init (struct pci_controller *hose);
  699. #endif
  700. /**
  701. * pci_write_bar32() - Write the address of a BAR including control bits
  702. *
  703. * This writes a raw address (with control bits) to a bar. This can be used
  704. * with devices which require hard-coded addresses, not part of the normal
  705. * PCI enumeration process.
  706. *
  707. * This is only available if CONFIG_DM_PCI_COMPAT is enabled
  708. *
  709. * @hose: PCI hose to use
  710. * @dev: PCI device to update
  711. * @barnum: BAR number (0-5)
  712. * @addr: BAR address with control bits
  713. */
  714. void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
  715. u32 addr);
  716. /**
  717. * pci_read_bar32() - read the address of a bar
  718. *
  719. * This is only available if CONFIG_DM_PCI_COMPAT is enabled
  720. *
  721. * @hose: PCI hose to use
  722. * @dev: PCI device to inspect
  723. * @barnum: BAR number (0-5)
  724. * @return address of the bar, masking out any control bits
  725. * */
  726. u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
  727. /**
  728. * pci_hose_find_devices() - Find devices by vendor/device ID
  729. *
  730. * This is only available if CONFIG_DM_PCI_COMPAT is enabled
  731. *
  732. * @hose: PCI hose to search
  733. * @busnum: Bus number to search
  734. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  735. * @indexp: Pointer to device index to find. To find the first matching
  736. * device, pass 0; to find the second, pass 1, etc. This
  737. * parameter is decremented for each non-matching device so
  738. * can be called repeatedly.
  739. */
  740. pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
  741. struct pci_device_id *ids, int *indexp);
  742. /* Access sizes for PCI reads and writes */
  743. enum pci_size_t {
  744. PCI_SIZE_8,
  745. PCI_SIZE_16,
  746. PCI_SIZE_32,
  747. };
  748. struct udevice;
  749. /**
  750. * struct pci_child_plat - information stored about each PCI device
  751. *
  752. * Every device on a PCI bus has this per-child data.
  753. *
  754. * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a
  755. * PCI bus (i.e. UCLASS_PCI)
  756. *
  757. * @devfn: Encoded device and function index - see PCI_DEVFN()
  758. * @vendor: PCI vendor ID (see pci_ids.h)
  759. * @device: PCI device ID (see pci_ids.h)
  760. * @class: PCI class, 3 bytes: (base, sub, prog-if)
  761. * @is_virtfn: True for Virtual Function device
  762. * @pfdev: Handle to Physical Function device
  763. * @virtid: Virtual Function Index
  764. */
  765. struct pci_child_plat {
  766. int devfn;
  767. unsigned short vendor;
  768. unsigned short device;
  769. unsigned int class;
  770. /* Variables for CONFIG_PCI_SRIOV */
  771. bool is_virtfn;
  772. struct udevice *pfdev;
  773. int virtid;
  774. };
  775. /* PCI bus operations */
  776. struct dm_pci_ops {
  777. /**
  778. * read_config() - Read a PCI configuration value
  779. *
  780. * PCI buses must support reading and writing configuration values
  781. * so that the bus can be scanned and its devices configured.
  782. *
  783. * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always.
  784. * If bridges exist it is possible to use the top-level bus to
  785. * access a sub-bus. In that case @bus will be the top-level bus
  786. * and PCI_BUS(bdf) will be a different (higher) value
  787. *
  788. * @bus: Bus to read from
  789. * @bdf: Bus, device and function to read
  790. * @offset: Byte offset within the device's configuration space
  791. * @valuep: Place to put the returned value
  792. * @size: Access size
  793. * @return 0 if OK, -ve on error
  794. */
  795. int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
  796. uint offset, ulong *valuep, enum pci_size_t size);
  797. /**
  798. * write_config() - Write a PCI configuration value
  799. *
  800. * @bus: Bus to write to
  801. * @bdf: Bus, device and function to write
  802. * @offset: Byte offset within the device's configuration space
  803. * @value: Value to write
  804. * @size: Access size
  805. * @return 0 if OK, -ve on error
  806. */
  807. int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
  808. ulong value, enum pci_size_t size);
  809. };
  810. /* Get access to a PCI bus' operations */
  811. #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
  812. /**
  813. * dm_pci_get_bdf() - Get the BDF value for a device
  814. *
  815. * @dev: Device to check
  816. * @return bus/device/function value (see PCI_BDF())
  817. */
  818. pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
  819. /**
  820. * pci_bind_bus_devices() - scan a PCI bus and bind devices
  821. *
  822. * Scan a PCI bus looking for devices. Bind each one that is found. If
  823. * devices are already bound that match the scanned devices, just update the
  824. * child data so that the device can be used correctly (this happens when
  825. * the device tree describes devices we expect to see on the bus).
  826. *
  827. * Devices that are bound in this way will use a generic PCI driver which
  828. * does nothing. The device can still be accessed but will not provide any
  829. * driver interface.
  830. *
  831. * @bus: Bus containing devices to bind
  832. * @return 0 if OK, -ve on error
  833. */
  834. int pci_bind_bus_devices(struct udevice *bus);
  835. /**
  836. * pci_auto_config_devices() - configure bus devices ready for use
  837. *
  838. * This works through all devices on a bus by scanning the driver model
  839. * data structures (normally these have been set up by pci_bind_bus_devices()
  840. * earlier).
  841. *
  842. * Space is allocated for each PCI base address register (BAR) so that the
  843. * devices are mapped into memory and I/O space ready for use.
  844. *
  845. * @bus: Bus containing devices to bind
  846. * @return 0 if OK, -ve on error
  847. */
  848. int pci_auto_config_devices(struct udevice *bus);
  849. /**
  850. * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
  851. *
  852. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  853. * @devp: Returns the device for this address, if found
  854. * @return 0 if OK, -ENODEV if not found
  855. */
  856. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
  857. /**
  858. * pci_bus_find_devfn() - Find a device on a bus
  859. *
  860. * @find_devfn: PCI device address (device and function only)
  861. * @devp: Returns the device for this address, if found
  862. * @return 0 if OK, -ENODEV if not found
  863. */
  864. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  865. struct udevice **devp);
  866. /**
  867. * pci_find_first_device() - return the first available PCI device
  868. *
  869. * This function and pci_find_first_device() allow iteration through all
  870. * available PCI devices on all buses. Assuming there are any, this will
  871. * return the first one.
  872. *
  873. * @devp: Set to the first available device, or NULL if no more are left
  874. * or we got an error
  875. * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  876. */
  877. int pci_find_first_device(struct udevice **devp);
  878. /**
  879. * pci_find_next_device() - return the next available PCI device
  880. *
  881. * Finds the next available PCI device after the one supplied, or sets @devp
  882. * to NULL if there are no more.
  883. *
  884. * @devp: On entry, the last device returned. Set to the next available
  885. * device, or NULL if no more are left or we got an error
  886. * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  887. */
  888. int pci_find_next_device(struct udevice **devp);
  889. /**
  890. * pci_get_ff() - Returns a mask for the given access size
  891. *
  892. * @size: Access size
  893. * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
  894. * PCI_SIZE_32
  895. */
  896. int pci_get_ff(enum pci_size_t size);
  897. /**
  898. * pci_bus_find_devices () - Find devices on a bus
  899. *
  900. * @bus: Bus to search
  901. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  902. * @indexp: Pointer to device index to find. To find the first matching
  903. * device, pass 0; to find the second, pass 1, etc. This
  904. * parameter is decremented for each non-matching device so
  905. * can be called repeatedly.
  906. * @devp: Returns matching device if found
  907. * @return 0 if found, -ENODEV if not
  908. */
  909. int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
  910. int *indexp, struct udevice **devp);
  911. /**
  912. * pci_find_device_id() - Find a device on any bus
  913. *
  914. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  915. * @index: Index number of device to find, 0 for the first match, 1 for
  916. * the second, etc.
  917. * @devp: Returns matching device if found
  918. * @return 0 if found, -ENODEV if not
  919. */
  920. int pci_find_device_id(const struct pci_device_id *ids, int index,
  921. struct udevice **devp);
  922. /**
  923. * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
  924. *
  925. * This probes the given bus which causes it to be scanned for devices. The
  926. * devices will be bound but not probed.
  927. *
  928. * @hose specifies the PCI hose that will be used for the scan. This is
  929. * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
  930. * in @bdf, and is a subordinate bus reachable from @hose.
  931. *
  932. * @hose: PCI hose to scan
  933. * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
  934. * @return 0 if OK, -ve on error
  935. */
  936. int dm_pci_hose_probe_bus(struct udevice *bus);
  937. /**
  938. * pci_bus_read_config() - Read a configuration value from a device
  939. *
  940. * TODO(sjg@chromium.org): We should be able to pass just a device and have
  941. * it do the right thing. It would be good to have that function also.
  942. *
  943. * @bus: Bus to read from
  944. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  945. * @offset: Register offset to read
  946. * @valuep: Place to put the returned value
  947. * @size: Access size
  948. * @return 0 if OK, -ve on error
  949. */
  950. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  951. unsigned long *valuep, enum pci_size_t size);
  952. /**
  953. * pci_bus_write_config() - Write a configuration value to a device
  954. *
  955. * @bus: Bus to write from
  956. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  957. * @offset: Register offset to write
  958. * @value: Value to write
  959. * @size: Access size
  960. * @return 0 if OK, -ve on error
  961. */
  962. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  963. unsigned long value, enum pci_size_t size);
  964. /**
  965. * pci_bus_clrset_config32() - Update a configuration value for a device
  966. *
  967. * The register at @offset is updated to (oldvalue & ~clr) | set.
  968. *
  969. * @bus: Bus to access
  970. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  971. * @offset: Register offset to update
  972. * @clr: Bits to clear
  973. * @set: Bits to set
  974. * @return 0 if OK, -ve on error
  975. */
  976. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  977. u32 clr, u32 set);
  978. /**
  979. * Driver model PCI config access functions. Use these in preference to others
  980. * when you have a valid device
  981. */
  982. int dm_pci_read_config(const struct udevice *dev, int offset,
  983. unsigned long *valuep, enum pci_size_t size);
  984. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
  985. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
  986. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
  987. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  988. enum pci_size_t size);
  989. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
  990. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
  991. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
  992. /**
  993. * These permit convenient read/modify/write on PCI configuration. The
  994. * register is updated to (oldvalue & ~clr) | set.
  995. */
  996. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
  997. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
  998. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
  999. /*
  1000. * The following functions provide access to the above without needing the
  1001. * size parameter. We are trying to encourage the use of the 8/16/32-style
  1002. * functions, rather than byte/word/dword. But both are supported.
  1003. */
  1004. int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
  1005. int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
  1006. int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
  1007. int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
  1008. int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
  1009. int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
  1010. /**
  1011. * pci_generic_mmap_write_config() - Generic helper for writing to
  1012. * memory-mapped PCI configuration space.
  1013. * @bus: Pointer to the PCI bus
  1014. * @addr_f: Callback for calculating the config space address
  1015. * @bdf: Identifies the PCI device to access
  1016. * @offset: The offset into the device's configuration space
  1017. * @value: The value to write
  1018. * @size: Indicates the size of access to perform
  1019. *
  1020. * Write the value @value of size @size from offset @offset within the
  1021. * configuration space of the device identified by the bus, device & function
  1022. * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
  1023. * responsible for calculating the CPU address of the respective configuration
  1024. * space offset.
  1025. *
  1026. * Return: 0 on success, else -EINVAL
  1027. */
  1028. int pci_generic_mmap_write_config(
  1029. const struct udevice *bus,
  1030. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  1031. void **addrp),
  1032. pci_dev_t bdf,
  1033. uint offset,
  1034. ulong value,
  1035. enum pci_size_t size);
  1036. /**
  1037. * pci_generic_mmap_read_config() - Generic helper for reading from
  1038. * memory-mapped PCI configuration space.
  1039. * @bus: Pointer to the PCI bus
  1040. * @addr_f: Callback for calculating the config space address
  1041. * @bdf: Identifies the PCI device to access
  1042. * @offset: The offset into the device's configuration space
  1043. * @valuep: A pointer at which to store the read value
  1044. * @size: Indicates the size of access to perform
  1045. *
  1046. * Read a value of size @size from offset @offset within the configuration
  1047. * space of the device identified by the bus, device & function numbers in @bdf
  1048. * on the PCI bus @bus. The callback function @addr_f is responsible for
  1049. * calculating the CPU address of the respective configuration space offset.
  1050. *
  1051. * Return: 0 on success, else -EINVAL
  1052. */
  1053. int pci_generic_mmap_read_config(
  1054. const struct udevice *bus,
  1055. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  1056. void **addrp),
  1057. pci_dev_t bdf,
  1058. uint offset,
  1059. ulong *valuep,
  1060. enum pci_size_t size);
  1061. #if defined(CONFIG_PCI_SRIOV)
  1062. /**
  1063. * pci_sriov_init() - Scan Virtual Function devices
  1064. *
  1065. * @pdev: Physical Function udevice handle
  1066. * @vf_en: Number of Virtual Function devices to enable
  1067. * @return 0 on success, -ve on error
  1068. */
  1069. int pci_sriov_init(struct udevice *pdev, int vf_en);
  1070. /**
  1071. * pci_sriov_get_totalvfs() - Get total available Virtual Function devices
  1072. *
  1073. * @pdev: Physical Function udevice handle
  1074. * @return count on success, -ve on error
  1075. */
  1076. int pci_sriov_get_totalvfs(struct udevice *pdev);
  1077. #endif
  1078. #ifdef CONFIG_DM_PCI_COMPAT
  1079. /* Compatibility with old naming */
  1080. static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
  1081. u32 value)
  1082. {
  1083. return pci_write_config32(pcidev, offset, value);
  1084. }
  1085. /* Compatibility with old naming */
  1086. static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
  1087. u16 value)
  1088. {
  1089. return pci_write_config16(pcidev, offset, value);
  1090. }
  1091. /* Compatibility with old naming */
  1092. static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
  1093. u8 value)
  1094. {
  1095. return pci_write_config8(pcidev, offset, value);
  1096. }
  1097. /* Compatibility with old naming */
  1098. static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
  1099. u32 *valuep)
  1100. {
  1101. return pci_read_config32(pcidev, offset, valuep);
  1102. }
  1103. /* Compatibility with old naming */
  1104. static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
  1105. u16 *valuep)
  1106. {
  1107. return pci_read_config16(pcidev, offset, valuep);
  1108. }
  1109. /* Compatibility with old naming */
  1110. static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
  1111. u8 *valuep)
  1112. {
  1113. return pci_read_config8(pcidev, offset, valuep);
  1114. }
  1115. #endif /* CONFIG_DM_PCI_COMPAT */
  1116. /**
  1117. * dm_pciauto_config_device() - configure a device ready for use
  1118. *
  1119. * Space is allocated for each PCI base address register (BAR) so that the
  1120. * devices are mapped into memory and I/O space ready for use.
  1121. *
  1122. * @dev: Device to configure
  1123. * @return 0 if OK, -ve on error
  1124. */
  1125. int dm_pciauto_config_device(struct udevice *dev);
  1126. /**
  1127. * pci_conv_32_to_size() - convert a 32-bit read value to the given size
  1128. *
  1129. * Some PCI buses must always perform 32-bit reads. The data must then be
  1130. * shifted and masked to reflect the required access size and offset. This
  1131. * function performs this transformation.
  1132. *
  1133. * @value: Value to transform (32-bit value read from @offset & ~3)
  1134. * @offset: Register offset that was read
  1135. * @size: Required size of the result
  1136. * @return the value that would have been obtained if the read had been
  1137. * performed at the given offset with the correct size
  1138. */
  1139. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
  1140. /**
  1141. * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
  1142. *
  1143. * Some PCI buses must always perform 32-bit writes. To emulate a smaller
  1144. * write the old 32-bit data must be read, updated with the required new data
  1145. * and written back as a 32-bit value. This function performs the
  1146. * transformation from the old value to the new value.
  1147. *
  1148. * @value: Value to transform (32-bit value read from @offset & ~3)
  1149. * @offset: Register offset that should be written
  1150. * @size: Required size of the write
  1151. * @return the value that should be written as a 32-bit access to @offset & ~3.
  1152. */
  1153. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  1154. enum pci_size_t size);
  1155. /**
  1156. * pci_get_controller() - obtain the controller to use for a bus
  1157. *
  1158. * @dev: Device to check
  1159. * @return pointer to the controller device for this bus
  1160. */
  1161. struct udevice *pci_get_controller(struct udevice *dev);
  1162. /**
  1163. * pci_get_regions() - obtain pointers to all the region types
  1164. *
  1165. * @dev: Device to check
  1166. * @iop: Returns a pointer to the I/O region, or NULL if none
  1167. * @memp: Returns a pointer to the memory region, or NULL if none
  1168. * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
  1169. * @return the number of non-NULL regions returned, normally 3
  1170. */
  1171. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  1172. struct pci_region **memp, struct pci_region **prefp);
  1173. int
  1174. pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
  1175. /**
  1176. * dm_pci_write_bar32() - Write the address of a BAR
  1177. *
  1178. * This writes a raw address to a bar
  1179. *
  1180. * @dev: PCI device to update
  1181. * @barnum: BAR number (0-5)
  1182. * @addr: BAR address
  1183. */
  1184. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
  1185. /**
  1186. * dm_pci_read_bar32() - read a base address register from a device
  1187. *
  1188. * @dev: Device to check
  1189. * @barnum: Bar number to read (numbered from 0)
  1190. * @return: value of BAR
  1191. */
  1192. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
  1193. /**
  1194. * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
  1195. *
  1196. * @dev: Device containing the PCI address
  1197. * @addr: PCI address to convert
  1198. * @flags: Flags for the region type (PCI_REGION_...)
  1199. * @return physical address corresponding to that PCI bus address
  1200. */
  1201. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
  1202. unsigned long flags);
  1203. /**
  1204. * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
  1205. *
  1206. * @dev: Device containing the bus address
  1207. * @addr: Physical address to convert
  1208. * @flags: Flags for the region type (PCI_REGION_...)
  1209. * @return PCI bus address corresponding to that physical address
  1210. */
  1211. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
  1212. unsigned long flags);
  1213. /**
  1214. * dm_pci_map_bar() - get a virtual address associated with a BAR region
  1215. *
  1216. * Looks up a base address register and finds the physical memory address
  1217. * that corresponds to it.
  1218. * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
  1219. * type 1 functions.
  1220. * Can also be used on type 0 functions that support Enhanced Allocation for
  1221. * 32b/64b BARs. Note that duplicate BEI entries are not supported.
  1222. *
  1223. * @dev: Device to check
  1224. * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
  1225. * @flags: Flags for the region type (PCI_REGION_...)
  1226. * @return: pointer to the virtual address to use or 0 on error
  1227. */
  1228. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
  1229. /**
  1230. * dm_pci_find_next_capability() - find a capability starting from an offset
  1231. *
  1232. * Tell if a device supports a given PCI capability. Returns the
  1233. * address of the requested capability structure within the device's
  1234. * PCI configuration space or 0 in case the device does not support it.
  1235. *
  1236. * Possible values for @cap:
  1237. *
  1238. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  1239. * %PCI_CAP_ID_PCIX PCI-X
  1240. * %PCI_CAP_ID_EXP PCI Express
  1241. * %PCI_CAP_ID_MSIX MSI-X
  1242. *
  1243. * See PCI_CAP_ID_xxx for the complete capability ID codes.
  1244. *
  1245. * @dev: PCI device to query
  1246. * @start: offset to start from
  1247. * @cap: capability code
  1248. * @return: capability address or 0 if not supported
  1249. */
  1250. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
  1251. /**
  1252. * dm_pci_find_capability() - find a capability
  1253. *
  1254. * Tell if a device supports a given PCI capability. Returns the
  1255. * address of the requested capability structure within the device's
  1256. * PCI configuration space or 0 in case the device does not support it.
  1257. *
  1258. * Possible values for @cap:
  1259. *
  1260. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  1261. * %PCI_CAP_ID_PCIX PCI-X
  1262. * %PCI_CAP_ID_EXP PCI Express
  1263. * %PCI_CAP_ID_MSIX MSI-X
  1264. *
  1265. * See PCI_CAP_ID_xxx for the complete capability ID codes.
  1266. *
  1267. * @dev: PCI device to query
  1268. * @cap: capability code
  1269. * @return: capability address or 0 if not supported
  1270. */
  1271. int dm_pci_find_capability(struct udevice *dev, int cap);
  1272. /**
  1273. * dm_pci_find_next_ext_capability() - find an extended capability
  1274. * starting from an offset
  1275. *
  1276. * Tell if a device supports a given PCI express extended capability.
  1277. * Returns the address of the requested extended capability structure
  1278. * within the device's PCI configuration space or 0 in case the device
  1279. * does not support it.
  1280. *
  1281. * Possible values for @cap:
  1282. *
  1283. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  1284. * %PCI_EXT_CAP_ID_VC Virtual Channel
  1285. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  1286. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  1287. *
  1288. * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
  1289. *
  1290. * @dev: PCI device to query
  1291. * @start: offset to start from
  1292. * @cap: extended capability code
  1293. * @return: extended capability address or 0 if not supported
  1294. */
  1295. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
  1296. /**
  1297. * dm_pci_find_ext_capability() - find an extended capability
  1298. *
  1299. * Tell if a device supports a given PCI express extended capability.
  1300. * Returns the address of the requested extended capability structure
  1301. * within the device's PCI configuration space or 0 in case the device
  1302. * does not support it.
  1303. *
  1304. * Possible values for @cap:
  1305. *
  1306. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  1307. * %PCI_EXT_CAP_ID_VC Virtual Channel
  1308. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  1309. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  1310. *
  1311. * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
  1312. *
  1313. * @dev: PCI device to query
  1314. * @cap: extended capability code
  1315. * @return: extended capability address or 0 if not supported
  1316. */
  1317. int dm_pci_find_ext_capability(struct udevice *dev, int cap);
  1318. /**
  1319. * dm_pci_flr() - Perform FLR if the device suppoorts it
  1320. *
  1321. * @dev: PCI device to reset
  1322. * @return: 0 if OK, -ENOENT if FLR is not supported by dev
  1323. */
  1324. int dm_pci_flr(struct udevice *dev);
  1325. #define dm_pci_virt_to_bus(dev, addr, flags) \
  1326. dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
  1327. #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
  1328. map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
  1329. (len), (map_flags))
  1330. #define dm_pci_phys_to_mem(dev, addr) \
  1331. dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
  1332. #define dm_pci_mem_to_phys(dev, addr) \
  1333. dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
  1334. #define dm_pci_phys_to_io(dev, addr) \
  1335. dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
  1336. #define dm_pci_io_to_phys(dev, addr) \
  1337. dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
  1338. #define dm_pci_virt_to_mem(dev, addr) \
  1339. dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
  1340. #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
  1341. dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
  1342. #define dm_pci_virt_to_io(dev, addr) \
  1343. dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
  1344. #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
  1345. dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
  1346. /**
  1347. * dm_pci_find_device() - find a device by vendor/device ID
  1348. *
  1349. * @vendor: Vendor ID
  1350. * @device: Device ID
  1351. * @index: 0 to find the first match, 1 for second, etc.
  1352. * @devp: Returns pointer to the device, if found
  1353. * @return 0 if found, -ve on error
  1354. */
  1355. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  1356. struct udevice **devp);
  1357. /**
  1358. * dm_pci_find_class() - find a device by class
  1359. *
  1360. * @find_class: 3-byte (24-bit) class value to find
  1361. * @index: 0 to find the first match, 1 for second, etc.
  1362. * @devp: Returns pointer to the device, if found
  1363. * @return 0 if found, -ve on error
  1364. */
  1365. int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
  1366. /**
  1367. * struct pci_emul_uc_priv - holds info about an emulator device
  1368. *
  1369. * There is always at most one emulator per client
  1370. *
  1371. * @client: Client device if any, else NULL
  1372. */
  1373. struct pci_emul_uc_priv {
  1374. struct udevice *client;
  1375. };
  1376. /**
  1377. * struct dm_pci_emul_ops - PCI device emulator operations
  1378. */
  1379. struct dm_pci_emul_ops {
  1380. /**
  1381. * read_config() - Read a PCI configuration value
  1382. *
  1383. * @dev: Emulated device to read from
  1384. * @offset: Byte offset within the device's configuration space
  1385. * @valuep: Place to put the returned value
  1386. * @size: Access size
  1387. * @return 0 if OK, -ve on error
  1388. */
  1389. int (*read_config)(const struct udevice *dev, uint offset,
  1390. ulong *valuep, enum pci_size_t size);
  1391. /**
  1392. * write_config() - Write a PCI configuration value
  1393. *
  1394. * @dev: Emulated device to write to
  1395. * @offset: Byte offset within the device's configuration space
  1396. * @value: Value to write
  1397. * @size: Access size
  1398. * @return 0 if OK, -ve on error
  1399. */
  1400. int (*write_config)(struct udevice *dev, uint offset, ulong value,
  1401. enum pci_size_t size);
  1402. /**
  1403. * read_io() - Read a PCI I/O value
  1404. *
  1405. * @dev: Emulated device to read from
  1406. * @addr: I/O address to read
  1407. * @valuep: Place to put the returned value
  1408. * @size: Access size
  1409. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1410. * other -ve value on error
  1411. */
  1412. int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
  1413. enum pci_size_t size);
  1414. /**
  1415. * write_io() - Write a PCI I/O value
  1416. *
  1417. * @dev: Emulated device to write from
  1418. * @addr: I/O address to write
  1419. * @value: Value to write
  1420. * @size: Access size
  1421. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1422. * other -ve value on error
  1423. */
  1424. int (*write_io)(struct udevice *dev, unsigned int addr,
  1425. ulong value, enum pci_size_t size);
  1426. /**
  1427. * map_physmem() - Map a device into sandbox memory
  1428. *
  1429. * @dev: Emulated device to map
  1430. * @addr: Memory address, normally corresponding to a PCI BAR.
  1431. * The device should have been configured to have a BAR
  1432. * at this address.
  1433. * @lenp: On entry, the size of the area to map, On exit it is
  1434. * updated to the size actually mapped, which may be less
  1435. * if the device has less space
  1436. * @ptrp: Returns a pointer to the mapped address. The device's
  1437. * space can be accessed as @lenp bytes starting here
  1438. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1439. * other -ve value on error
  1440. */
  1441. int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
  1442. unsigned long *lenp, void **ptrp);
  1443. /**
  1444. * unmap_physmem() - undo a memory mapping
  1445. *
  1446. * This must be called after map_physmem() to undo the mapping.
  1447. * Some devices can use this to check what has been written into
  1448. * their mapped memory and perform an operations they require on it.
  1449. * In this way, map/unmap can be used as a sort of handshake between
  1450. * the emulated device and its users.
  1451. *
  1452. * @dev: Emuated device to unmap
  1453. * @vaddr: Mapped memory address, as passed to map_physmem()
  1454. * @len: Size of area mapped, as returned by map_physmem()
  1455. * @return 0 if OK, -ve on error
  1456. */
  1457. int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
  1458. unsigned long len);
  1459. };
  1460. /* Get access to a PCI device emulator's operations */
  1461. #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
  1462. /**
  1463. * sandbox_pci_get_emul() - Get the emulation device for a PCI device
  1464. *
  1465. * Searches for a suitable emulator for the given PCI bus device
  1466. *
  1467. * @bus: PCI bus to search
  1468. * @find_devfn: PCI device and function address (PCI_DEVFN())
  1469. * @containerp: Returns container device if found
  1470. * @emulp: Returns emulated device if found
  1471. * @return 0 if found, -ENODEV if not found
  1472. */
  1473. int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
  1474. struct udevice **containerp, struct udevice **emulp);
  1475. /**
  1476. * sandbox_pci_get_client() - Find the client for an emulation device
  1477. *
  1478. * @emul: Emulation device to check
  1479. * @devp: Returns the client device emulated by this device
  1480. * @return 0 if OK, -ENOENT if the device has no client yet
  1481. */
  1482. int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
  1483. /**
  1484. * board_pci_fixup_dev() - Board callback for PCI device fixups
  1485. *
  1486. * @bus: PCI bus
  1487. * @dev: PCI device
  1488. */
  1489. extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
  1490. /**
  1491. * PCI_DEVICE - macro used to describe a specific pci device
  1492. * @vend: the 16 bit PCI Vendor ID
  1493. * @dev: the 16 bit PCI Device ID
  1494. *
  1495. * This macro is used to create a struct pci_device_id that matches a
  1496. * specific device. The subvendor and subdevice fields will be set to
  1497. * PCI_ANY_ID.
  1498. */
  1499. #define PCI_DEVICE(vend, dev) \
  1500. .vendor = (vend), .device = (dev), \
  1501. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  1502. /**
  1503. * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
  1504. * @vend: the 16 bit PCI Vendor ID
  1505. * @dev: the 16 bit PCI Device ID
  1506. * @subvend: the 16 bit PCI Subvendor ID
  1507. * @subdev: the 16 bit PCI Subdevice ID
  1508. *
  1509. * This macro is used to create a struct pci_device_id that matches a
  1510. * specific device with subsystem information.
  1511. */
  1512. #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
  1513. .vendor = (vend), .device = (dev), \
  1514. .subvendor = (subvend), .subdevice = (subdev)
  1515. /**
  1516. * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
  1517. * @dev_class: the class, subclass, prog-if triple for this device
  1518. * @dev_class_mask: the class mask for this device
  1519. *
  1520. * This macro is used to create a struct pci_device_id that matches a
  1521. * specific PCI class. The vendor, device, subvendor, and subdevice
  1522. * fields will be set to PCI_ANY_ID.
  1523. */
  1524. #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
  1525. .class = (dev_class), .class_mask = (dev_class_mask), \
  1526. .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
  1527. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  1528. /**
  1529. * PCI_VDEVICE - macro used to describe a specific pci device in short form
  1530. * @vend: the vendor name
  1531. * @dev: the 16 bit PCI Device ID
  1532. *
  1533. * This macro is used to create a struct pci_device_id that matches a
  1534. * specific PCI device. The subvendor, and subdevice fields will be set
  1535. * to PCI_ANY_ID. The macro allows the next field to follow as the device
  1536. * private data.
  1537. */
  1538. #define PCI_VDEVICE(vend, dev) \
  1539. .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
  1540. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
  1541. /**
  1542. * struct pci_driver_entry - Matches a driver to its pci_device_id list
  1543. * @driver: Driver to use
  1544. * @match: List of match records for this driver, terminated by {}
  1545. */
  1546. struct pci_driver_entry {
  1547. struct driver *driver;
  1548. const struct pci_device_id *match;
  1549. };
  1550. #define U_BOOT_PCI_DEVICE(__name, __match) \
  1551. ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
  1552. .driver = llsym(struct driver, __name, driver), \
  1553. .match = __match, \
  1554. }
  1555. #endif /* __ASSEMBLY__ */
  1556. #endif /* _PCI_H */