MPC8560ADS.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. * (C) Copyright 2002,2003 Motorola,Inc.
  5. * Xianghua Xiao <X.Xiao@motorola.com>
  6. */
  7. /*
  8. * mpc8560ads board configuration file
  9. *
  10. * Please refer to doc/README.mpc85xx for more info.
  11. *
  12. * Make sure you change the MAC address and other network params first,
  13. * search for CONFIG_SERVERIP, etc. in this file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. #include <linux/delay.h>
  18. /* High Level Configuration Options */
  19. #define CONFIG_CPM2 1 /* has CPM2 */
  20. /*
  21. * default CCARBAR is at 0xff700000
  22. * assume U-Boot is less than 0.5MB
  23. */
  24. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  25. #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  26. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  27. /*
  28. * sysclk for MPC85xx
  29. *
  30. * Two valid values are:
  31. * 33000000
  32. * 66000000
  33. *
  34. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  35. * is likely the desired value here, so that is now the default.
  36. * The board, however, can run at 66MHz. In any event, this value
  37. * must match the settings of some switches. Details can be found
  38. * in the README.mpc85xxads.
  39. */
  40. #ifndef CONFIG_SYS_CLK_FREQ
  41. #define CONFIG_SYS_CLK_FREQ 33000000
  42. #endif
  43. /*
  44. * These can be toggled for performance analysis, otherwise use default.
  45. */
  46. #define CONFIG_L2_CACHE /* toggle L2 cache */
  47. #define CONFIG_BTB /* toggle branch predition */
  48. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  49. #define CONFIG_SYS_CCSRBAR 0xe0000000
  50. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  51. /* DDR Setup */
  52. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  53. #define CONFIG_DDR_SPD
  54. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  55. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  56. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  57. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  58. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  59. /* I2C addresses of SPD EEPROMs */
  60. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  61. /* These are used when DDR doesn't use SPD. */
  62. #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
  63. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  64. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
  65. #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  66. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  67. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  68. #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  69. #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  70. /*
  71. * SDRAM on the Local Bus
  72. */
  73. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  74. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  75. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  76. #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
  77. #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  78. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  79. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  80. #undef CONFIG_SYS_FLASH_CHECKSUM
  81. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  82. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  83. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  84. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  85. #define CONFIG_SYS_RAMBOOT
  86. #else
  87. #undef CONFIG_SYS_RAMBOOT
  88. #endif
  89. #define CONFIG_SYS_FLASH_EMPTY_INFO
  90. /*
  91. * Local Bus Definitions
  92. */
  93. /*
  94. * Base Register 2 and Option Register 2 configure SDRAM.
  95. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  96. *
  97. * For BR2, need:
  98. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  99. * port-size = 32-bits = BR2[19:20] = 11
  100. * no parity checking = BR2[21:22] = 00
  101. * SDRAM for MSEL = BR2[24:26] = 011
  102. * Valid = BR[31] = 1
  103. *
  104. * 0 4 8 12 16 20 24 28
  105. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  106. *
  107. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  108. * FIXME: the top 17 bits of BR2.
  109. */
  110. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  111. /*
  112. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  113. *
  114. * For OR2, need:
  115. * 64MB mask for AM, OR2[0:7] = 1111 1100
  116. * XAM, OR2[17:18] = 11
  117. * 9 columns OR2[19-21] = 010
  118. * 13 rows OR2[23-25] = 100
  119. * EAD set for extra time OR[31] = 1
  120. *
  121. * 0 4 8 12 16 20 24 28
  122. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  123. */
  124. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  125. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  126. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  127. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  128. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  129. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
  130. | LSDMR_RFCR5 \
  131. | LSDMR_PRETOACT3 \
  132. | LSDMR_ACTTORW3 \
  133. | LSDMR_BL8 \
  134. | LSDMR_WRC2 \
  135. | LSDMR_CL3 \
  136. | LSDMR_RFEN \
  137. )
  138. /*
  139. * SDRAM Controller configuration sequence.
  140. */
  141. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  142. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  143. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  144. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  145. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  146. /*
  147. * 32KB, 8-bit wide for ADS config reg
  148. */
  149. #define CONFIG_SYS_BR4_PRELIM 0xf8000801
  150. #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
  151. #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
  152. #define CONFIG_SYS_INIT_RAM_LOCK 1
  153. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  154. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  155. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  156. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  157. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  158. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  159. /* Serial Port */
  160. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  161. #undef CONFIG_CONS_NONE /* define if console on something else */
  162. #define CONFIG_SYS_BAUDRATE_TABLE \
  163. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  164. /*
  165. * I2C
  166. */
  167. #define CONFIG_SYS_I2C_LEGACY
  168. #define CONFIG_SYS_I2C_FSL
  169. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  170. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  171. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  172. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  173. /* RapidIO MMU */
  174. #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  175. #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  176. #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
  177. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  178. /*
  179. * General PCI
  180. * Memory space is mapped 1-1, but I/O space must start from 0.
  181. */
  182. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  183. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  184. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  185. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  186. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  187. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  188. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  189. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  190. #if defined(CONFIG_PCI)
  191. #if !defined(CONFIG_PCI_PNP)
  192. #define PCI_ENET0_IOADDR 0xe0000000
  193. #define PCI_ENET0_MEMADDR 0xe0000000
  194. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  195. #endif
  196. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  197. #endif /* CONFIG_PCI */
  198. #ifdef CONFIG_TSEC_ENET
  199. #define CONFIG_TSEC1 1
  200. #define CONFIG_TSEC1_NAME "TSEC0"
  201. #define CONFIG_TSEC2 1
  202. #define CONFIG_TSEC2_NAME "TSEC1"
  203. #define TSEC1_PHY_ADDR 0
  204. #define TSEC2_PHY_ADDR 1
  205. #define TSEC1_PHYIDX 0
  206. #define TSEC2_PHYIDX 0
  207. #define TSEC1_FLAGS TSEC_GIGABIT
  208. #define TSEC2_FLAGS TSEC_GIGABIT
  209. /* Options are: TSEC[0-1] */
  210. #define CONFIG_ETHPRIME "TSEC0"
  211. #endif /* CONFIG_TSEC_ENET */
  212. #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
  213. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  214. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  215. #if (CONFIG_ETHER_INDEX == 2)
  216. /*
  217. * - Rx-CLK is CLK13
  218. * - Tx-CLK is CLK14
  219. * - Select bus for bd/buffers
  220. * - Full duplex
  221. */
  222. #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  223. #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  224. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  225. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
  226. #define FETH2_RST 0x01
  227. #elif (CONFIG_ETHER_INDEX == 3)
  228. /* need more definitions here for FE3 */
  229. #define FETH3_RST 0x80
  230. #endif /* CONFIG_ETHER_INDEX */
  231. /*
  232. * GPIO pins used for bit-banged MII communications
  233. */
  234. #define MDIO_PORT 2 /* Port C */
  235. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  236. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  237. #define MDC_DECLARE MDIO_DECLARE
  238. #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  239. #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  240. #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  241. #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  242. else iop->pdat &= ~0x00400000
  243. #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
  244. else iop->pdat &= ~0x00200000
  245. #define MIIDELAY udelay(1)
  246. #endif
  247. /*
  248. * Environment
  249. */
  250. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  251. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  252. /*
  253. * BOOTP options
  254. */
  255. #define CONFIG_BOOTP_BOOTFILESIZE
  256. #undef CONFIG_WATCHDOG /* watchdog disabled */
  257. /*
  258. * Miscellaneous configurable options
  259. */
  260. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  261. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  262. /*
  263. * For booting Linux, the board info and command line data
  264. * have to be in the first 64 MB of memory, since this is
  265. * the maximum mapped by the Linux kernel during initialization.
  266. */
  267. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  268. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  269. #if defined(CONFIG_CMD_KGDB)
  270. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  271. #endif
  272. /*
  273. * Environment Configuration
  274. */
  275. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  276. #define CONFIG_HAS_ETH0
  277. #define CONFIG_HAS_ETH1
  278. #define CONFIG_HAS_ETH2
  279. #define CONFIG_HAS_ETH3
  280. #endif
  281. #define CONFIG_IPADDR 192.168.1.253
  282. #define CONFIG_HOSTNAME "unknown"
  283. #define CONFIG_ROOTPATH "/nfsroot"
  284. #define CONFIG_BOOTFILE "your.uImage"
  285. #define CONFIG_SERVERIP 192.168.1.1
  286. #define CONFIG_GATEWAYIP 192.168.1.1
  287. #define CONFIG_NETMASK 255.255.255.0
  288. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  289. #define CONFIG_EXTRA_ENV_SETTINGS \
  290. "netdev=eth0\0" \
  291. "consoledev=ttyCPM\0" \
  292. "ramdiskaddr=1000000\0" \
  293. "ramdiskfile=your.ramdisk.u-boot\0" \
  294. "fdtaddr=400000\0" \
  295. "fdtfile=mpc8560ads.dtb\0"
  296. #define CONFIG_NFSBOOTCOMMAND \
  297. "setenv bootargs root=/dev/nfs rw " \
  298. "nfsroot=$serverip:$rootpath " \
  299. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  300. "console=$consoledev,$baudrate $othbootargs;" \
  301. "tftp $loadaddr $bootfile;" \
  302. "tftp $fdtaddr $fdtfile;" \
  303. "bootm $loadaddr - $fdtaddr"
  304. #define CONFIG_RAMBOOTCOMMAND \
  305. "setenv bootargs root=/dev/ram rw " \
  306. "console=$consoledev,$baudrate $othbootargs;" \
  307. "tftp $ramdiskaddr $ramdiskfile;" \
  308. "tftp $loadaddr $bootfile;" \
  309. "tftp $fdtaddr $fdtfile;" \
  310. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  311. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  312. #endif /* __CONFIG_H */