MPC8540ADS.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. * (C) Copyright 2002,2003 Motorola,Inc.
  5. * Xianghua Xiao <X.Xiao@motorola.com>
  6. */
  7. /*
  8. * mpc8540ads board configuration file
  9. *
  10. * Please refer to doc/README.mpc85xx for more info.
  11. *
  12. * Make sure you change the MAC address and other network params first,
  13. * search for CONFIG_SERVERIP, etc in this file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /*
  18. * default CCARBAR is at 0xff700000
  19. * assume U-Boot is less than 0.5MB
  20. */
  21. #ifndef CONFIG_HAS_FEC
  22. #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
  23. #endif
  24. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  25. /*
  26. * sysclk for MPC85xx
  27. *
  28. * Two valid values are:
  29. * 33000000
  30. * 66000000
  31. *
  32. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  33. * is likely the desired value here, so that is now the default.
  34. * The board, however, can run at 66MHz. In any event, this value
  35. * must match the settings of some switches. Details can be found
  36. * in the README.mpc85xxads.
  37. *
  38. * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
  39. * 33MHz to accommodate, based on a PCI pin.
  40. * Note that PCI-X won't work at 33MHz.
  41. */
  42. #ifndef CONFIG_SYS_CLK_FREQ
  43. #define CONFIG_SYS_CLK_FREQ 33000000
  44. #endif
  45. /*
  46. * These can be toggled for performance analysis, otherwise use default.
  47. */
  48. #define CONFIG_L2_CACHE /* toggle L2 cache */
  49. #define CONFIG_BTB /* toggle branch predition */
  50. #define CONFIG_SYS_CCSRBAR 0xe0000000
  51. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  52. /* DDR Setup */
  53. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  54. #define CONFIG_DDR_SPD
  55. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  56. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  57. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  58. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  59. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  60. /* I2C addresses of SPD EEPROMs */
  61. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  62. /* These are used when DDR doesn't use SPD. */
  63. #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
  64. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  65. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
  66. #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  67. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  68. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  69. #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  70. #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  71. /*
  72. * SDRAM on the Local Bus
  73. */
  74. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  75. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  76. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  77. #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
  78. #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  79. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  80. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  81. #undef CONFIG_SYS_FLASH_CHECKSUM
  82. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  83. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  84. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  85. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  86. #define CONFIG_SYS_RAMBOOT
  87. #else
  88. #undef CONFIG_SYS_RAMBOOT
  89. #endif
  90. #define CONFIG_SYS_FLASH_EMPTY_INFO
  91. /*
  92. * Local Bus Definitions
  93. */
  94. /*
  95. * Base Register 2 and Option Register 2 configure SDRAM.
  96. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  97. *
  98. * For BR2, need:
  99. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  100. * port-size = 32-bits = BR2[19:20] = 11
  101. * no parity checking = BR2[21:22] = 00
  102. * SDRAM for MSEL = BR2[24:26] = 011
  103. * Valid = BR[31] = 1
  104. *
  105. * 0 4 8 12 16 20 24 28
  106. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  107. *
  108. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  109. * FIXME: the top 17 bits of BR2.
  110. */
  111. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  112. /*
  113. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  114. *
  115. * For OR2, need:
  116. * 64MB mask for AM, OR2[0:7] = 1111 1100
  117. * XAM, OR2[17:18] = 11
  118. * 9 columns OR2[19-21] = 010
  119. * 13 rows OR2[23-25] = 100
  120. * EAD set for extra time OR[31] = 1
  121. *
  122. * 0 4 8 12 16 20 24 28
  123. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  124. */
  125. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  126. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  127. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  128. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  129. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  130. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
  131. | LSDMR_RFCR5 \
  132. | LSDMR_PRETOACT3 \
  133. | LSDMR_ACTTORW3 \
  134. | LSDMR_BL8 \
  135. | LSDMR_WRC2 \
  136. | LSDMR_CL3 \
  137. | LSDMR_RFEN \
  138. )
  139. /*
  140. * SDRAM Controller configuration sequence.
  141. */
  142. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  143. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  144. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  145. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  146. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  147. /*
  148. * 32KB, 8-bit wide for ADS config reg
  149. */
  150. #define CONFIG_SYS_BR4_PRELIM 0xf8000801
  151. #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
  152. #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
  153. #define CONFIG_SYS_INIT_RAM_LOCK 1
  154. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  155. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  156. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  157. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  158. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  159. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  160. /* Serial Port */
  161. #define CONFIG_SYS_NS16550_SERIAL
  162. #define CONFIG_SYS_NS16550_REG_SIZE 1
  163. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  164. #define CONFIG_SYS_BAUDRATE_TABLE \
  165. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  166. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  167. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  168. /*
  169. * I2C
  170. */
  171. #define CONFIG_SYS_I2C_LEGACY
  172. #define CONFIG_SYS_I2C_FSL
  173. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  174. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  175. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  176. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  177. /* RapidIO MMU */
  178. #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  179. #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  180. #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
  181. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  182. /*
  183. * General PCI
  184. * Memory space is mapped 1-1, but I/O space must start from 0.
  185. */
  186. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  187. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  188. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  189. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  190. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  191. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  192. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  193. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  194. #if defined(CONFIG_PCI)
  195. #if !defined(CONFIG_PCI_PNP)
  196. #define PCI_ENET0_IOADDR 0xe0000000
  197. #define PCI_ENET0_MEMADDR 0xe0000000
  198. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  199. #endif
  200. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  201. #endif /* CONFIG_PCI */
  202. #if defined(CONFIG_TSEC_ENET)
  203. #define CONFIG_TSEC1 1
  204. #define CONFIG_TSEC1_NAME "TSEC0"
  205. #define CONFIG_TSEC2 1
  206. #define CONFIG_TSEC2_NAME "TSEC1"
  207. #define TSEC1_PHY_ADDR 0
  208. #define TSEC2_PHY_ADDR 1
  209. #define TSEC1_PHYIDX 0
  210. #define TSEC2_PHYIDX 0
  211. #define TSEC1_FLAGS TSEC_GIGABIT
  212. #define TSEC2_FLAGS TSEC_GIGABIT
  213. #if CONFIG_HAS_FEC
  214. #define CONFIG_MPC85XX_FEC 1
  215. #define CONFIG_MPC85XX_FEC_NAME "FEC"
  216. #define FEC_PHY_ADDR 3
  217. #define FEC_PHYIDX 0
  218. #define FEC_FLAGS 0
  219. #endif
  220. /* Options are: TSEC[0-1], FEC */
  221. #define CONFIG_ETHPRIME "TSEC0"
  222. #endif /* CONFIG_TSEC_ENET */
  223. /*
  224. * Environment
  225. */
  226. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  227. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  228. /*
  229. * BOOTP options
  230. */
  231. #define CONFIG_BOOTP_BOOTFILESIZE
  232. #undef CONFIG_WATCHDOG /* watchdog disabled */
  233. /*
  234. * Miscellaneous configurable options
  235. */
  236. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  237. /*
  238. * For booting Linux, the board info and command line data
  239. * have to be in the first 64 MB of memory, since this is
  240. * the maximum mapped by the Linux kernel during initialization.
  241. */
  242. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  243. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  244. #if defined(CONFIG_CMD_KGDB)
  245. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  246. #endif
  247. /*
  248. * Environment Configuration
  249. */
  250. /* The mac addresses for all ethernet interface */
  251. #if defined(CONFIG_TSEC_ENET)
  252. #define CONFIG_HAS_ETH0
  253. #define CONFIG_HAS_ETH1
  254. #define CONFIG_HAS_ETH2
  255. #endif
  256. #define CONFIG_IPADDR 192.168.1.253
  257. #define CONFIG_HOSTNAME "unknown"
  258. #define CONFIG_ROOTPATH "/nfsroot"
  259. #define CONFIG_BOOTFILE "your.uImage"
  260. #define CONFIG_SERVERIP 192.168.1.1
  261. #define CONFIG_GATEWAYIP 192.168.1.1
  262. #define CONFIG_NETMASK 255.255.255.0
  263. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  264. #define CONFIG_EXTRA_ENV_SETTINGS \
  265. "netdev=eth0\0" \
  266. "consoledev=ttyS0\0" \
  267. "ramdiskaddr=1000000\0" \
  268. "ramdiskfile=your.ramdisk.u-boot\0" \
  269. "fdtaddr=400000\0" \
  270. "fdtfile=your.fdt.dtb\0"
  271. #define CONFIG_NFSBOOTCOMMAND \
  272. "setenv bootargs root=/dev/nfs rw " \
  273. "nfsroot=$serverip:$rootpath " \
  274. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  275. "console=$consoledev,$baudrate $othbootargs;" \
  276. "tftp $loadaddr $bootfile;" \
  277. "tftp $fdtaddr $fdtfile;" \
  278. "bootm $loadaddr - $fdtaddr"
  279. #define CONFIG_RAMBOOTCOMMAND \
  280. "setenv bootargs root=/dev/ram rw " \
  281. "console=$consoledev,$baudrate $othbootargs;" \
  282. "tftp $ramdiskaddr $ramdiskfile;" \
  283. "tftp $loadaddr $bootfile;" \
  284. "tftp $fdtaddr $fdtfile;" \
  285. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  286. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  287. #endif /* __CONFIG_H */