MPC837XERDB.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Kevin Lam <kevin.lam@freescale.com>
  5. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <linux/stringify.h>
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. #define CONFIG_HWCONFIG
  15. /*
  16. * On-board devices
  17. */
  18. #define CONFIG_VSC7385_ENET
  19. /* System performance - define the value i.e. CONFIG_SYS_XXX
  20. */
  21. /* System Clock Configuration Register */
  22. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
  23. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
  24. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
  25. /*
  26. * System IO Config
  27. */
  28. #define CONFIG_SYS_SICRH 0x08200000
  29. #define CONFIG_SYS_SICRL 0x00000000
  30. /*
  31. * Output Buffer Impedance
  32. */
  33. #define CONFIG_SYS_OBIR 0x30100000
  34. /*
  35. * Device configurations
  36. */
  37. /* Vitesse 7385 */
  38. #ifdef CONFIG_VSC7385_ENET
  39. #define CONFIG_TSEC2
  40. /* The flash address and size of the VSC7385 firmware image */
  41. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  42. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  43. #endif
  44. /*
  45. * DDR Setup
  46. */
  47. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  48. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
  49. #define CONFIG_SYS_83XX_DDR_USES_CS0
  50. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  51. #undef CONFIG_DDR_ECC /* support DDR ECC function */
  52. #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
  53. #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  54. /*
  55. * Manually set up DDR parameters
  56. */
  57. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  58. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  59. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  60. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  61. | CSCONFIG_ROW_BIT_13 \
  62. | CSCONFIG_COL_BIT_10)
  63. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  64. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  65. | (0 << TIMING_CFG0_WRT_SHIFT) \
  66. | (0 << TIMING_CFG0_RRT_SHIFT) \
  67. | (0 << TIMING_CFG0_WWT_SHIFT) \
  68. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  69. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  70. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  71. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  72. /* 0x00260802 */ /* DDR400 */
  73. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  74. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  75. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  76. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  77. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  78. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  79. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  80. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  81. /* 0x3937d322 */
  82. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  83. | (5 << TIMING_CFG2_CPO_SHIFT) \
  84. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  85. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  86. | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  87. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  88. | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  89. /* 0x02984cc8 */
  90. #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
  91. | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  92. /* 0x06090100 */
  93. #if defined(CONFIG_DDR_2T_TIMING)
  94. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  95. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  96. | SDRAM_CFG_32_BE \
  97. | SDRAM_CFG_2T_EN)
  98. /* 0x43088000 */
  99. #else
  100. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  101. | SDRAM_CFG_SDRAM_TYPE_DDR2)
  102. /* 0x43000000 */
  103. #endif
  104. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  105. #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
  106. | (0x0442 << SDRAM_MODE_SD_SHIFT))
  107. /* 0x04400442 */ /* DDR400 */
  108. #define CONFIG_SYS_DDR_MODE2 0x00000000
  109. /*
  110. * Memory test
  111. */
  112. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  113. /*
  114. * The reserved memory
  115. */
  116. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  117. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  118. #define CONFIG_SYS_RAMBOOT
  119. #else
  120. #undef CONFIG_SYS_RAMBOOT
  121. #endif
  122. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  123. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  124. /*
  125. * Initial RAM Base Address Setup
  126. */
  127. #define CONFIG_SYS_INIT_RAM_LOCK 1
  128. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  129. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  130. #define CONFIG_SYS_GBL_DATA_OFFSET \
  131. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  132. /*
  133. * FLASH on the Local Bus
  134. */
  135. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  136. #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
  137. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  138. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  139. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  140. #undef CONFIG_SYS_FLASH_CHECKSUM
  141. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  142. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  143. /*
  144. * NAND Flash on the Local Bus
  145. */
  146. #define CONFIG_SYS_NAND_BASE 0xE0600000
  147. /* Vitesse 7385 */
  148. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  149. /*
  150. * Serial Port
  151. */
  152. #define CONFIG_SYS_NS16550_SERIAL
  153. #define CONFIG_SYS_NS16550_REG_SIZE 1
  154. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  155. #define CONFIG_SYS_BAUDRATE_TABLE \
  156. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  157. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  158. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  159. /* SERDES */
  160. #define CONFIG_FSL_SERDES
  161. #define CONFIG_FSL_SERDES1 0xe3000
  162. #define CONFIG_FSL_SERDES2 0xe3100
  163. /* I2C */
  164. #define CONFIG_SYS_I2C_LEGACY
  165. #define CONFIG_SYS_I2C_FSL
  166. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  167. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  168. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  169. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  170. /*
  171. * Config on-board RTC
  172. */
  173. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  174. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  175. /*
  176. * General PCI
  177. * Addresses are mapped 1-1.
  178. */
  179. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  180. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  181. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  182. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  183. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  184. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  185. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  186. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  187. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  188. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  189. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  190. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  191. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  192. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  193. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  194. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  195. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  196. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  197. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  198. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  199. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  200. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  201. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  202. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  203. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  204. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  205. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  206. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  207. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  208. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  209. #ifdef CONFIG_PCI
  210. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  211. #endif /* CONFIG_PCI */
  212. /*
  213. * TSEC
  214. */
  215. #ifdef CONFIG_TSEC_ENET
  216. #define CONFIG_GMII /* MII PHY management */
  217. #define CONFIG_TSEC1
  218. #ifdef CONFIG_TSEC1
  219. #define CONFIG_HAS_ETH0
  220. #define CONFIG_TSEC1_NAME "TSEC0"
  221. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  222. #define TSEC1_PHY_ADDR 2
  223. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  224. #define TSEC1_PHYIDX 0
  225. #endif
  226. #ifdef CONFIG_TSEC2
  227. #define CONFIG_HAS_ETH1
  228. #define CONFIG_TSEC2_NAME "TSEC1"
  229. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  230. #define TSEC2_PHY_ADDR 0x1c
  231. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  232. #define TSEC2_PHYIDX 0
  233. #endif
  234. /* Options are: TSEC[0-1] */
  235. #define CONFIG_ETHPRIME "TSEC0"
  236. #endif
  237. /*
  238. * SATA
  239. */
  240. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  241. #define CONFIG_SATA1
  242. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  243. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  244. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  245. #define CONFIG_SATA2
  246. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  247. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  248. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  249. #ifdef CONFIG_FSL_SATA
  250. #define CONFIG_LBA48
  251. #endif
  252. /*
  253. * Environment
  254. */
  255. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  256. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  257. /*
  258. * BOOTP options
  259. */
  260. #define CONFIG_BOOTP_BOOTFILESIZE
  261. #undef CONFIG_WATCHDOG /* watchdog disabled */
  262. #ifdef CONFIG_MMC
  263. #define CONFIG_FSL_ESDHC_PIN_MUX
  264. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  265. #endif
  266. /*
  267. * Miscellaneous configurable options
  268. */
  269. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  270. /*
  271. * For booting Linux, the board info and command line data
  272. * have to be in the first 256 MB of memory, since this is
  273. * the maximum mapped by the Linux kernel during initialization.
  274. */
  275. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  276. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  277. #if defined(CONFIG_CMD_KGDB)
  278. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  279. #endif
  280. /*
  281. * Environment Configuration
  282. */
  283. #define CONFIG_HAS_FSL_DR_USB
  284. #define CONFIG_USB_EHCI_FSL
  285. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  286. #define CONFIG_NETDEV "eth1"
  287. #define CONFIG_HOSTNAME "mpc837x_rdb"
  288. #define CONFIG_ROOTPATH "/nfsroot"
  289. #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
  290. #define CONFIG_BOOTFILE "uImage"
  291. /* U-Boot image on TFTP server */
  292. #define CONFIG_UBOOTPATH "u-boot.bin"
  293. #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
  294. /* default location for tftp and bootm */
  295. #define CONFIG_LOADADDR 800000
  296. #define CONFIG_EXTRA_ENV_SETTINGS \
  297. "netdev=" CONFIG_NETDEV "\0" \
  298. "uboot=" CONFIG_UBOOTPATH "\0" \
  299. "tftpflash=tftp $loadaddr $uboot;" \
  300. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  301. " +$filesize; " \
  302. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  303. " +$filesize; " \
  304. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  305. " $filesize; " \
  306. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  307. " +$filesize; " \
  308. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  309. " $filesize\0" \
  310. "fdtaddr=780000\0" \
  311. "fdtfile=" CONFIG_FDTFILE "\0" \
  312. "ramdiskaddr=1000000\0" \
  313. "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
  314. "console=ttyS0\0" \
  315. "setbootargs=setenv bootargs " \
  316. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  317. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  318. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  319. "$netdev:off " \
  320. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  321. #define CONFIG_NFSBOOTCOMMAND \
  322. "setenv rootdev /dev/nfs;" \
  323. "run setbootargs;" \
  324. "run setipargs;" \
  325. "tftp $loadaddr $bootfile;" \
  326. "tftp $fdtaddr $fdtfile;" \
  327. "bootm $loadaddr - $fdtaddr"
  328. #define CONFIG_RAMBOOTCOMMAND \
  329. "setenv rootdev /dev/ram;" \
  330. "run setbootargs;" \
  331. "tftp $ramdiskaddr $ramdiskfile;" \
  332. "tftp $loadaddr $bootfile;" \
  333. "tftp $fdtaddr $fdtfile;" \
  334. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  335. #endif /* __CONFIG_H */