MPC8349EMDS_SDRAM.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2010
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * mpc8349emds board configuration file
  8. *
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_E300 1 /* E300 Family */
  16. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  17. /*
  18. * DDR Setup
  19. */
  20. #define CONFIG_DDR_ECC /* support DDR ECC function */
  21. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  22. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  23. /*
  24. * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  25. * unselect it to use old spd_sdram.c
  26. */
  27. #define CONFIG_SYS_SPD_BUS_NUM 0
  28. #define SPD_EEPROM_ADDRESS1 0x52
  29. #define SPD_EEPROM_ADDRESS2 0x51
  30. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  31. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  32. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  33. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  34. /*
  35. * 32-bit data path mode.
  36. *
  37. * Please note that using this mode for devices with the real density of 64-bit
  38. * effectively reduces the amount of available memory due to the effect of
  39. * wrapping around while translating address to row/columns, for example in the
  40. * 256MB module the upper 128MB get aliased with contents of the lower
  41. * 128MB); normally this define should be used for devices with real 32-bit
  42. * data path.
  43. */
  44. #undef CONFIG_DDR_32BIT
  45. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  46. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  47. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  48. #undef CONFIG_DDR_2T_TIMING
  49. /*
  50. * DDRCDR - DDR Control Driver Register
  51. */
  52. #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  53. #if defined(CONFIG_SPD_EEPROM)
  54. /*
  55. * Determine DDR configuration from I2C interface.
  56. */
  57. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  58. #else
  59. /*
  60. * Manually set up DDR parameters
  61. */
  62. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  63. #if defined(CONFIG_DDR_II)
  64. #define CONFIG_SYS_DDRCDR 0x80080001
  65. #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
  66. #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
  67. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  68. #define CONFIG_SYS_DDR_TIMING_1 0x38357322
  69. #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
  70. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  71. #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
  72. #define CONFIG_SYS_DDR_MODE 0x47d00432
  73. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  74. #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
  75. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  76. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  77. #else
  78. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  79. | CSCONFIG_ROW_BIT_13 \
  80. | CSCONFIG_COL_BIT_10)
  81. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  82. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  83. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  84. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  85. #if defined(CONFIG_DDR_32BIT)
  86. /* set burst length to 8 for 32-bit data path */
  87. /* DLL,normal,seq,4/2.5, 8 burst len */
  88. #define CONFIG_SYS_DDR_MODE 0x00000023
  89. #else
  90. /* the default burst length is 4 - for 64-bit data path */
  91. /* DLL,normal,seq,4/2.5, 4 burst len */
  92. #define CONFIG_SYS_DDR_MODE 0x00000022
  93. #endif
  94. #endif
  95. #endif
  96. /*
  97. * SDRAM on the Local Bus
  98. */
  99. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  100. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  101. /*
  102. * FLASH on the Local Bus
  103. */
  104. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  105. #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
  106. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  107. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  108. #undef CONFIG_SYS_FLASH_CHECKSUM
  109. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  110. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  111. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  112. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  113. #define CONFIG_SYS_RAMBOOT
  114. #else
  115. #undef CONFIG_SYS_RAMBOOT
  116. #endif
  117. /*
  118. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  119. */
  120. #define CONFIG_SYS_BCSR 0xE2400000
  121. /* Access window base at BCSR base */
  122. #define CONFIG_SYS_INIT_RAM_LOCK 1
  123. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  124. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  125. #define CONFIG_SYS_GBL_DATA_OFFSET \
  126. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  127. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  128. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  129. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  130. /*
  131. * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  132. */
  133. /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
  134. /*
  135. * Base Register 2 and Option Register 2 configure SDRAM.
  136. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  137. *
  138. * For BR2, need:
  139. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  140. * port-size = 32-bits = BR2[19:20] = 11
  141. * no parity checking = BR2[21:22] = 00
  142. * SDRAM for MSEL = BR2[24:26] = 011
  143. * Valid = BR[31] = 1
  144. *
  145. * 0 4 8 12 16 20 24 28
  146. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  147. */
  148. /*
  149. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  150. *
  151. * For OR2, need:
  152. * 64MB mask for AM, OR2[0:7] = 1111 1100
  153. * XAM, OR2[17:18] = 11
  154. * 9 columns OR2[19-21] = 010
  155. * 13 rows OR2[23-25] = 100
  156. * EAD set for extra time OR[31] = 1
  157. *
  158. * 0 4 8 12 16 20 24 28
  159. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  160. */
  161. /* LB sdram refresh timer, about 6us */
  162. #define CONFIG_SYS_LBC_LSRT 0x32000000
  163. /* LB refresh timer prescal, 266MHz/32 */
  164. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  165. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  166. | LSDMR_BSMA1516 \
  167. | LSDMR_RFCR8 \
  168. | LSDMR_PRETOACT6 \
  169. | LSDMR_ACTTORW3 \
  170. | LSDMR_BL8 \
  171. | LSDMR_WRC3 \
  172. | LSDMR_CL3)
  173. /*
  174. * SDRAM Controller configuration sequence.
  175. */
  176. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  177. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  178. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  179. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  180. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  181. /*
  182. * Serial Port
  183. */
  184. #define CONFIG_SYS_NS16550_SERIAL
  185. #define CONFIG_SYS_NS16550_REG_SIZE 1
  186. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  187. #define CONFIG_SYS_BAUDRATE_TABLE \
  188. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  189. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  190. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  191. /* I2C */
  192. #define CONFIG_SYS_I2C_LEGACY
  193. #define CONFIG_SYS_I2C_FSL
  194. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  195. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  196. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  197. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  198. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  199. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  200. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  201. /* SPI */
  202. #undef CONFIG_SOFT_SPI /* SPI bit-banged */
  203. /* GPIOs. Used as SPI chip selects */
  204. #define CONFIG_SYS_GPIO1_PRELIM
  205. #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
  206. #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
  207. /* TSEC */
  208. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  209. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  210. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  211. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  212. /* USB */
  213. #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
  214. /*
  215. * General PCI
  216. * Addresses are mapped 1-1.
  217. */
  218. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  219. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  220. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  221. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  222. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  223. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  224. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  225. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  226. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  227. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  228. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  229. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  230. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  231. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  232. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  233. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  234. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  235. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  236. #if defined(CONFIG_PCI)
  237. #define CONFIG_83XX_PCI_STREAMING
  238. #if !defined(CONFIG_PCI_PNP)
  239. #define PCI_ENET0_IOADDR 0xFIXME
  240. #define PCI_ENET0_MEMADDR 0xFIXME
  241. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  242. #endif
  243. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  244. #endif /* CONFIG_PCI */
  245. /*
  246. * TSEC configuration
  247. */
  248. #if defined(CONFIG_TSEC_ENET)
  249. #define CONFIG_GMII 1 /* MII PHY management */
  250. #define CONFIG_TSEC1 1
  251. #define CONFIG_TSEC1_NAME "TSEC0"
  252. #define CONFIG_TSEC2 1
  253. #define CONFIG_TSEC2_NAME "TSEC1"
  254. #define TSEC1_PHY_ADDR 0
  255. #define TSEC2_PHY_ADDR 1
  256. #define TSEC1_PHYIDX 0
  257. #define TSEC2_PHYIDX 0
  258. #define TSEC1_FLAGS TSEC_GIGABIT
  259. #define TSEC2_FLAGS TSEC_GIGABIT
  260. /* Options are: TSEC[0-1] */
  261. #define CONFIG_ETHPRIME "TSEC0"
  262. #endif /* CONFIG_TSEC_ENET */
  263. /*
  264. * Configure on-board RTC
  265. */
  266. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  267. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  268. /*
  269. * Environment
  270. */
  271. #ifndef CONFIG_SYS_RAMBOOT
  272. /* Address and size of Redundant Environment Sector */
  273. #endif
  274. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  275. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  276. /*
  277. * BOOTP options
  278. */
  279. #define CONFIG_BOOTP_BOOTFILESIZE
  280. #undef CONFIG_WATCHDOG /* watchdog disabled */
  281. /*
  282. * Miscellaneous configurable options
  283. */
  284. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  285. /*
  286. * For booting Linux, the board info and command line data
  287. * have to be in the first 256 MB of memory, since this is
  288. * the maximum mapped by the Linux kernel during initialization.
  289. */
  290. /* Initial Memory map for Linux*/
  291. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  292. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  293. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  294. /*
  295. * System performance
  296. */
  297. #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
  298. #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
  299. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  300. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  301. /* System IO Config */
  302. #define CONFIG_SYS_SICRH 0
  303. #define CONFIG_SYS_SICRL SICRL_LDP_A
  304. #if defined(CONFIG_CMD_KGDB)
  305. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  306. #endif
  307. /*
  308. * Environment Configuration
  309. */
  310. #if defined(CONFIG_TSEC_ENET)
  311. #define CONFIG_HAS_ETH1
  312. #define CONFIG_HAS_ETH0
  313. #endif
  314. #define CONFIG_HOSTNAME "mpc8349emds"
  315. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  316. #define CONFIG_BOOTFILE "uImage"
  317. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  318. #define CONFIG_EXTRA_ENV_SETTINGS \
  319. "netdev=eth0\0" \
  320. "hostname=mpc8349emds\0" \
  321. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  322. "nfsroot=${serverip}:${rootpath}\0" \
  323. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  324. "addip=setenv bootargs ${bootargs} " \
  325. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  326. ":${hostname}:${netdev}:off panic=1\0" \
  327. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  328. "flash_nfs=run nfsargs addip addtty;" \
  329. "bootm ${kernel_addr}\0" \
  330. "flash_self=run ramargs addip addtty;" \
  331. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  332. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  333. "bootm\0" \
  334. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  335. "update=protect off fe000000 fe03ffff; " \
  336. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
  337. "upd=run load update\0" \
  338. "fdtaddr=780000\0" \
  339. "fdtfile=mpc834x_mds.dtb\0" \
  340. ""
  341. #define CONFIG_NFSBOOTCOMMAND \
  342. "setenv bootargs root=/dev/nfs rw " \
  343. "nfsroot=$serverip:$rootpath " \
  344. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  345. "$netdev:off " \
  346. "console=$consoledev,$baudrate $othbootargs;" \
  347. "tftp $loadaddr $bootfile;" \
  348. "tftp $fdtaddr $fdtfile;" \
  349. "bootm $loadaddr - $fdtaddr"
  350. #define CONFIG_RAMBOOTCOMMAND \
  351. "setenv bootargs root=/dev/ram rw " \
  352. "console=$consoledev,$baudrate $othbootargs;" \
  353. "tftp $ramdiskaddr $ramdiskfile;" \
  354. "tftp $loadaddr $bootfile;" \
  355. "tftp $fdtaddr $fdtfile;" \
  356. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  357. #define CONFIG_BOOTCOMMAND "run flash_self"
  358. #endif /* __CONFIG_H */