pcie_xilinx.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx AXI Bridge for PCI Express Driver
  4. *
  5. * Copyright (C) 2016 Imagination Technologies
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <pci.h>
  10. #include <asm/global_data.h>
  11. #include <linux/bitops.h>
  12. #include <asm/io.h>
  13. /**
  14. * struct xilinx_pcie - Xilinx PCIe controller state
  15. * @cfg_base: The base address of memory mapped configuration space
  16. */
  17. struct xilinx_pcie {
  18. void *cfg_base;
  19. };
  20. /* Register definitions */
  21. #define XILINX_PCIE_REG_PSCR 0x144
  22. #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
  23. /**
  24. * pcie_xilinx_link_up() - Check whether the PCIe link is up
  25. * @pcie: Pointer to the PCI controller state
  26. *
  27. * Checks whether the PCIe link for the given device is up or down.
  28. *
  29. * Return: true if the link is up, else false
  30. */
  31. static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
  32. {
  33. uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
  34. return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
  35. }
  36. /**
  37. * pcie_xilinx_config_address() - Calculate the address of a config access
  38. * @udev: Pointer to the PCI bus
  39. * @bdf: Identifies the PCIe device to access
  40. * @offset: The offset into the device's configuration space
  41. * @paddress: Pointer to the pointer to write the calculates address to
  42. *
  43. * Calculates the address that should be accessed to perform a PCIe
  44. * configuration space access for a given device identified by the PCIe
  45. * controller device @pcie and the bus, device & function numbers in @bdf. If
  46. * access to the device is not valid then the function will return an error
  47. * code. Otherwise the address to access will be written to the pointer pointed
  48. * to by @paddress.
  49. *
  50. * Return: 0 on success, else -ENODEV
  51. */
  52. static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
  53. uint offset, void **paddress)
  54. {
  55. struct xilinx_pcie *pcie = dev_get_priv(udev);
  56. unsigned int bus = PCI_BUS(bdf);
  57. unsigned int dev = PCI_DEV(bdf);
  58. unsigned int func = PCI_FUNC(bdf);
  59. void *addr;
  60. if ((bus > 0) && !pcie_xilinx_link_up(pcie))
  61. return -ENODEV;
  62. /*
  63. * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
  64. * limited to a single device each.
  65. */
  66. if ((bus < 2) && (dev > 0))
  67. return -ENODEV;
  68. addr = pcie->cfg_base;
  69. addr += bus << 20;
  70. addr += dev << 15;
  71. addr += func << 12;
  72. addr += offset;
  73. *paddress = addr;
  74. return 0;
  75. }
  76. /**
  77. * pcie_xilinx_read_config() - Read from configuration space
  78. * @bus: Pointer to the PCI bus
  79. * @bdf: Identifies the PCIe device to access
  80. * @offset: The offset into the device's configuration space
  81. * @valuep: A pointer at which to store the read value
  82. * @size: Indicates the size of access to perform
  83. *
  84. * Read a value of size @size from offset @offset within the configuration
  85. * space of the device identified by the bus, device & function numbers in @bdf
  86. * on the PCI bus @bus.
  87. *
  88. * Return: 0 on success, else -ENODEV or -EINVAL
  89. */
  90. static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
  91. uint offset, ulong *valuep,
  92. enum pci_size_t size)
  93. {
  94. return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
  95. bdf, offset, valuep, size);
  96. }
  97. /**
  98. * pcie_xilinx_write_config() - Write to configuration space
  99. * @bus: Pointer to the PCI bus
  100. * @bdf: Identifies the PCIe device to access
  101. * @offset: The offset into the device's configuration space
  102. * @value: The value to write
  103. * @size: Indicates the size of access to perform
  104. *
  105. * Write the value @value of size @size from offset @offset within the
  106. * configuration space of the device identified by the bus, device & function
  107. * numbers in @bdf on the PCI bus @bus.
  108. *
  109. * Return: 0 on success, else -ENODEV or -EINVAL
  110. */
  111. static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
  112. uint offset, ulong value,
  113. enum pci_size_t size)
  114. {
  115. return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
  116. bdf, offset, value, size);
  117. }
  118. /**
  119. * pcie_xilinx_of_to_plat() - Translate from DT to device state
  120. * @dev: A pointer to the device being operated on
  121. *
  122. * Translate relevant data from the device tree pertaining to device @dev into
  123. * state that the driver will later make use of. This state is stored in the
  124. * device's private data structure.
  125. *
  126. * Return: 0 on success, else -EINVAL
  127. */
  128. static int pcie_xilinx_of_to_plat(struct udevice *dev)
  129. {
  130. struct xilinx_pcie *pcie = dev_get_priv(dev);
  131. struct fdt_resource reg_res;
  132. DECLARE_GLOBAL_DATA_PTR;
  133. int err;
  134. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  135. 0, &reg_res);
  136. if (err < 0) {
  137. pr_err("\"reg\" resource not found\n");
  138. return err;
  139. }
  140. pcie->cfg_base = map_physmem(reg_res.start,
  141. fdt_resource_size(&reg_res),
  142. MAP_NOCACHE);
  143. return 0;
  144. }
  145. static const struct dm_pci_ops pcie_xilinx_ops = {
  146. .read_config = pcie_xilinx_read_config,
  147. .write_config = pcie_xilinx_write_config,
  148. };
  149. static const struct udevice_id pcie_xilinx_ids[] = {
  150. { .compatible = "xlnx,axi-pcie-host-1.00.a" },
  151. { }
  152. };
  153. U_BOOT_DRIVER(pcie_xilinx) = {
  154. .name = "pcie_xilinx",
  155. .id = UCLASS_PCI,
  156. .of_match = pcie_xilinx_ids,
  157. .ops = &pcie_xilinx_ops,
  158. .of_to_plat = pcie_xilinx_of_to_plat,
  159. .priv_auto = sizeof(struct xilinx_pcie),
  160. };