pcie_phytium.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Phytium PCIE host driver
  4. *
  5. * Heavily based on drivers/pci/pcie_xilinx.c
  6. *
  7. * Copyright (C) 2019
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <pci.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. /**
  15. * struct phytium_pcie - phytium PCIe controller state
  16. * @cfg_base: The base address of memory mapped configuration space
  17. */
  18. struct phytium_pcie {
  19. void *cfg_base;
  20. };
  21. /*
  22. * phytium_pci_skip_dev()
  23. * @parent: Identifies the PCIe device to access
  24. *
  25. * Checks whether the parent of the PCIe device is bridge
  26. *
  27. * Return: true if it is bridge, else false.
  28. */
  29. static int phytium_pci_skip_dev(pci_dev_t parent)
  30. {
  31. unsigned char pos, id;
  32. unsigned long addr = 0x40000000;
  33. unsigned short capreg;
  34. unsigned char port_type;
  35. addr += PCI_BUS(parent) << 20;
  36. addr += PCI_DEV(parent) << 15;
  37. addr += PCI_FUNC(parent) << 12;
  38. pos = 0x34;
  39. while (1) {
  40. pos = readb(addr + pos);
  41. if (pos < 0x40)
  42. break;
  43. pos &= ~3;
  44. id = readb(addr + pos);
  45. if (id == 0xff)
  46. break;
  47. if (id == 0x10) {
  48. capreg = readw(addr + pos + 2);
  49. port_type = (capreg >> 4) & 0xf;
  50. if (port_type == 0x6 || port_type == 0x4)
  51. return 1;
  52. else
  53. return 0;
  54. }
  55. pos += 1;
  56. }
  57. return 0;
  58. }
  59. /**
  60. * pci_phytium_conf_address() - Calculate the address of a config access
  61. * @bus: Pointer to the PCI bus
  62. * @bdf: Identifies the PCIe device to access
  63. * @offset: The offset into the device's configuration space
  64. * @paddress: Pointer to the pointer to write the calculates address to
  65. *
  66. * Calculates the address that should be accessed to perform a PCIe
  67. * configuration space access for a given device identified by the PCIe
  68. * controller device @pcie and the bus, device & function numbers in @bdf. If
  69. * access to the device is not valid then the function will return an error
  70. * code. Otherwise the address to access will be written to the pointer pointed
  71. * to by @paddress.
  72. */
  73. static int pci_phytium_conf_address(const struct udevice *bus, pci_dev_t bdf,
  74. uint offset, void **paddress)
  75. {
  76. struct phytium_pcie *pcie = dev_get_priv(bus);
  77. void *addr;
  78. pci_dev_t bdf_parent;
  79. unsigned int bus_no = PCI_BUS(bdf);
  80. unsigned int dev_no = PCI_DEV(bdf);
  81. bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
  82. addr = pcie->cfg_base;
  83. addr += PCI_BUS(bdf) << 20;
  84. addr += PCI_DEV(bdf) << 15;
  85. addr += PCI_FUNC(bdf) << 12;
  86. if (bus_no > 0 && dev_no > 0) {
  87. if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
  88. PCI_HEADER_TYPE_BRIDGE)
  89. return -ENODEV;
  90. if (phytium_pci_skip_dev(bdf_parent))
  91. return -ENODEV;
  92. }
  93. addr += offset;
  94. *paddress = addr;
  95. return 0;
  96. }
  97. /**
  98. * pci_phytium_read_config() - Read from configuration space
  99. * @bus: Pointer to the PCI bus
  100. * @bdf: Identifies the PCIe device to access
  101. * @offset: The offset into the device's configuration space
  102. * @valuep: A pointer at which to store the read value
  103. * @size: Indicates the size of access to perform
  104. *
  105. * Read a value of size @size from offset @offset within the configuration
  106. * space of the device identified by the bus, device & function numbers in @bdf
  107. * on the PCI bus @bus.
  108. */
  109. static int pci_phytium_read_config(const struct udevice *bus, pci_dev_t bdf,
  110. uint offset, ulong *valuep,
  111. enum pci_size_t size)
  112. {
  113. return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
  114. bdf, offset, valuep, size);
  115. }
  116. /**
  117. * pci_phytium_write_config() - Write to configuration space
  118. * @bus: Pointer to the PCI bus
  119. * @bdf: Identifies the PCIe device to access
  120. * @offset: The offset into the device's configuration space
  121. * @value: The value to write
  122. * @size: Indicates the size of access to perform
  123. *
  124. * Write the value @value of size @size from offset @offset within the
  125. * configuration space of the device identified by the bus, device & function
  126. * numbers in @bdf on the PCI bus @bus.
  127. */
  128. static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
  129. uint offset, ulong value,
  130. enum pci_size_t size)
  131. {
  132. return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
  133. bdf, offset, value, size);
  134. }
  135. /**
  136. * pci_phytium_of_to_plat() - Translate from DT to device state
  137. * @dev: A pointer to the device being operated on
  138. *
  139. * Translate relevant data from the device tree pertaining to device @dev into
  140. * state that the driver will later make use of. This state is stored in the
  141. * device's private data structure.
  142. *
  143. * Return: 0 on success, else -EINVAL
  144. */
  145. static int pci_phytium_of_to_plat(struct udevice *dev)
  146. {
  147. struct phytium_pcie *pcie = dev_get_priv(dev);
  148. struct fdt_resource reg_res;
  149. DECLARE_GLOBAL_DATA_PTR;
  150. int err;
  151. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  152. 0, &reg_res);
  153. if (err < 0) {
  154. pr_err("\"reg\" resource not found\n");
  155. return err;
  156. }
  157. pcie->cfg_base = map_physmem(reg_res.start,
  158. fdt_resource_size(&reg_res),
  159. MAP_NOCACHE);
  160. return 0;
  161. }
  162. static const struct dm_pci_ops pci_phytium_ops = {
  163. .read_config = pci_phytium_read_config,
  164. .write_config = pci_phytium_write_config,
  165. };
  166. static const struct udevice_id pci_phytium_ids[] = {
  167. { .compatible = "phytium,pcie-host-1.0" },
  168. { }
  169. };
  170. U_BOOT_DRIVER(pci_phytium) = {
  171. .name = "pci_phytium",
  172. .id = UCLASS_PCI,
  173. .of_match = pci_phytium_ids,
  174. .ops = &pci_phytium_ops,
  175. .of_to_plat = pci_phytium_of_to_plat,
  176. .priv_auto = sizeof(struct phytium_pcie),
  177. };