pcie_layerscape_gen4.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2020 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <pci.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <errno.h>
  15. #include <malloc.h>
  16. #include <dm.h>
  17. #include <linux/sizes.h>
  18. #include "pcie_layerscape_gen4.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. LIST_HEAD(ls_pcie_g4_list);
  21. static u64 bar_size[4] = {
  22. PCIE_BAR0_SIZE,
  23. PCIE_BAR1_SIZE,
  24. PCIE_BAR2_SIZE,
  25. PCIE_BAR4_SIZE
  26. };
  27. static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
  28. {
  29. u32 state;
  30. state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
  31. return state;
  32. }
  33. static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
  34. {
  35. int ltssm;
  36. ltssm = ls_pcie_g4_ltssm(pcie);
  37. if (ltssm != LTSSM_PCIE_L0)
  38. return 0;
  39. return 1;
  40. }
  41. static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
  42. {
  43. ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
  44. }
  45. static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
  46. {
  47. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
  48. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
  49. }
  50. static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  51. int type, u64 phys, u64 bus_addr,
  52. pci_size_t size)
  53. {
  54. u32 val;
  55. u32 size_h, size_l;
  56. if (idx >= PAB_WINS_NUM)
  57. return -EINVAL;
  58. size_h = upper_32_bits(~(size - 1));
  59. size_l = lower_32_bits(~(size - 1));
  60. val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
  61. val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
  62. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
  63. AXI_AMAP_CTRL_EN);
  64. val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
  65. ((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
  66. AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
  67. ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
  68. ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  69. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  70. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  71. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  72. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
  73. return 0;
  74. }
  75. static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  76. int type, u64 phys, u64 bus_addr,
  77. pci_size_t size)
  78. {
  79. u32 val;
  80. pci_size_t win_size = ~(size - 1);
  81. val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
  82. val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
  83. val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
  84. val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
  85. val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
  86. ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
  87. val | lower_32_bits(win_size));
  88. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
  89. ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  90. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  91. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  92. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  93. return 0;
  94. }
  95. static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
  96. {
  97. int i;
  98. for (i = 0; i < wins; i++) {
  99. debug("APIO Win%d:\n", i);
  100. debug("\tLOWER PHYS: 0x%08x\n",
  101. ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
  102. debug("\tUPPER PHYS: 0x%08x\n",
  103. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
  104. debug("\tLOWER BUS: 0x%08x\n",
  105. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
  106. debug("\tUPPER BUS: 0x%08x\n",
  107. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
  108. debug("\tSIZE: 0x%08x\n",
  109. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
  110. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
  111. debug("\tEXT_SIZE: 0x%08x\n",
  112. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
  113. debug("\tPARAM: 0x%08x\n",
  114. ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
  115. debug("\tCTRL: 0x%08x\n",
  116. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
  117. }
  118. }
  119. static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
  120. {
  121. struct pci_region *io, *mem, *pref;
  122. int idx = 1;
  123. /* INBOUND WIN */
  124. ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
  125. /* OUTBOUND WIN 0: CFG */
  126. ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
  127. pcie->cfg_res.start, 0,
  128. fdt_resource_size(&pcie->cfg_res));
  129. pci_get_regions(pcie->bus, &io, &mem, &pref);
  130. if (io)
  131. /* OUTBOUND WIN: IO */
  132. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
  133. io->phys_start, io->bus_start,
  134. io->size);
  135. if (mem)
  136. /* OUTBOUND WIN: MEM */
  137. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  138. mem->phys_start, mem->bus_start,
  139. mem->size);
  140. if (pref)
  141. /* OUTBOUND WIN: perf MEM */
  142. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  143. pref->phys_start, pref->bus_start,
  144. pref->size);
  145. ls_pcie_g4_dump_wins(pcie, idx);
  146. }
  147. /* Return 0 if the address is valid, -errno if not valid */
  148. static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
  149. {
  150. struct udevice *bus = pcie->bus;
  151. if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
  152. return -ENODEV;
  153. if (!pcie->enabled)
  154. return -ENXIO;
  155. if (PCI_BUS(bdf) < dev_seq(bus))
  156. return -EINVAL;
  157. if ((PCI_BUS(bdf) > dev_seq(bus)) && (!ls_pcie_g4_link_up(pcie)))
  158. return -EINVAL;
  159. if (PCI_BUS(bdf) <= (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
  160. return -EINVAL;
  161. return 0;
  162. }
  163. void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
  164. int offset)
  165. {
  166. struct udevice *bus = pcie->bus;
  167. u32 target;
  168. if (PCI_BUS(bdf) == dev_seq(bus)) {
  169. if (offset < INDIRECT_ADDR_BNDRY) {
  170. ccsr_set_page(pcie, 0);
  171. return pcie->ccsr + offset;
  172. }
  173. ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
  174. return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
  175. }
  176. target = PAB_TARGET_BUS(PCI_BUS(bdf) - dev_seq(bus)) |
  177. PAB_TARGET_DEV(PCI_DEV(bdf)) |
  178. PAB_TARGET_FUNC(PCI_FUNC(bdf));
  179. ls_pcie_g4_cfg_set_target(pcie, target);
  180. return pcie->cfg + offset;
  181. }
  182. static int ls_pcie_g4_read_config(const struct udevice *bus, pci_dev_t bdf,
  183. uint offset, ulong *valuep,
  184. enum pci_size_t size)
  185. {
  186. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  187. void *address;
  188. int ret = 0;
  189. if (ls_pcie_g4_addr_valid(pcie, bdf)) {
  190. *valuep = pci_get_ff(size);
  191. return 0;
  192. }
  193. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  194. switch (size) {
  195. case PCI_SIZE_8:
  196. *valuep = readb(address);
  197. break;
  198. case PCI_SIZE_16:
  199. *valuep = readw(address);
  200. break;
  201. case PCI_SIZE_32:
  202. *valuep = readl(address);
  203. break;
  204. default:
  205. ret = -EINVAL;
  206. break;
  207. }
  208. return ret;
  209. }
  210. static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
  211. uint offset, ulong value,
  212. enum pci_size_t size)
  213. {
  214. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  215. void *address;
  216. if (ls_pcie_g4_addr_valid(pcie, bdf))
  217. return 0;
  218. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  219. switch (size) {
  220. case PCI_SIZE_8:
  221. writeb(value, address);
  222. return 0;
  223. case PCI_SIZE_16:
  224. writew(value, address);
  225. return 0;
  226. case PCI_SIZE_32:
  227. writel(value, address);
  228. return 0;
  229. default:
  230. return -EINVAL;
  231. }
  232. }
  233. static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
  234. {
  235. u32 val;
  236. /* Fix class code */
  237. val = ccsr_readl(pcie, GPEX_CLASSCODE);
  238. val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
  239. val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
  240. ccsr_writel(pcie, GPEX_CLASSCODE, val);
  241. /* Enable APIO and Memory/IO/CFG Wins */
  242. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  243. val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
  244. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  245. ls_pcie_g4_setup_wins(pcie);
  246. pcie->stream_id_cur = 0;
  247. }
  248. static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
  249. int bar, u64 phys)
  250. {
  251. u32 val;
  252. /* PF BAR1 is for MSI-X and only need to enable */
  253. if (bar == 1) {
  254. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
  255. return;
  256. }
  257. val = upper_32_bits(phys);
  258. ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
  259. val = lower_32_bits(phys) | BAR_AMAP_EN;
  260. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
  261. }
  262. static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
  263. {
  264. u64 phys;
  265. int bar;
  266. u32 val;
  267. if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
  268. return;
  269. phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
  270. for (bar = 0; bar < PF_BAR_NUM; bar++) {
  271. ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
  272. phys += PCIE_BAR_SIZE;
  273. }
  274. /* OUTBOUND: map MEM */
  275. ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
  276. pcie->cfg_res.start +
  277. CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
  278. CONFIG_SYS_PCI_MEMORY_SIZE);
  279. val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
  280. val &= ~FUNC_NUM_PCIE_MASK;
  281. val |= pf;
  282. ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
  283. }
  284. static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
  285. int bar, bool vf_bar, bool enable)
  286. {
  287. u32 val;
  288. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  289. val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
  290. if (enable)
  291. val |= 1 << bar_pos;
  292. else
  293. val &= ~(1 << bar_pos);
  294. ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
  295. }
  296. static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
  297. int bar, bool vf_bar, u64 size)
  298. {
  299. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  300. u32 mask_l = lower_32_bits(~(size - 1));
  301. u32 mask_h = upper_32_bits(~(size - 1));
  302. ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
  303. ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
  304. ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
  305. }
  306. static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
  307. int bar, bool vf_bar, u64 size)
  308. {
  309. bool en = size ? true : false;
  310. ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
  311. ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
  312. }
  313. static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
  314. {
  315. int bar;
  316. /* Setup PF BARs */
  317. for (bar = 0; bar < PF_BAR_NUM; bar++)
  318. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
  319. if (!pcie->sriov_support)
  320. return;
  321. /* Setup VF BARs */
  322. for (bar = 0; bar < VF_BAR_NUM; bar++)
  323. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
  324. }
  325. static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
  326. {
  327. unsigned int val;
  328. val = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
  329. val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
  330. val |= PCIE_VF_NUM << TTL_VF_SHIFT;
  331. val &= ~(INI_VF_MASK << INI_VF_SHIFT);
  332. val |= PCIE_VF_NUM << INI_VF_SHIFT;
  333. ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
  334. val = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
  335. val += PCIE_VF_NUM * pf - pf;
  336. ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
  337. }
  338. static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
  339. {
  340. u32 pf, sriov;
  341. u32 val;
  342. int i;
  343. /* Enable APIO and Memory Win */
  344. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  345. val |= APIO_EN | MEM_WIN_EN;
  346. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  347. sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
  348. if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
  349. pcie->sriov_support = 1;
  350. pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
  351. for (i = 0; i < pf; i++) {
  352. ls_pcie_g4_ep_setup_bars(pcie, i);
  353. ls_pcie_g4_ep_setup_wins(pcie, i);
  354. if (pcie->sriov_support)
  355. ls_pcie_g4_set_sriov(pcie, i);
  356. }
  357. ls_pcie_g4_ep_enable_cfg(pcie);
  358. ls_pcie_g4_dump_wins(pcie, pf);
  359. }
  360. static int ls_pcie_g4_probe(struct udevice *dev)
  361. {
  362. struct ls_pcie_g4 *pcie = dev_get_priv(dev);
  363. const void *fdt = gd->fdt_blob;
  364. int node = dev_of_offset(dev);
  365. u32 link_ctrl_sta;
  366. u32 val;
  367. int ret;
  368. fdt_size_t cfg_size;
  369. pcie->bus = dev;
  370. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  371. "ccsr", &pcie->ccsr_res);
  372. if (ret) {
  373. printf("ls-pcie-g4: resource \"ccsr\" not found\n");
  374. return ret;
  375. }
  376. pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
  377. PCIE_CCSR_SIZE;
  378. list_add(&pcie->list, &ls_pcie_g4_list);
  379. pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
  380. if (!pcie->enabled) {
  381. printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
  382. dev->name);
  383. return 0;
  384. }
  385. pcie->ccsr = map_physmem(pcie->ccsr_res.start,
  386. fdt_resource_size(&pcie->ccsr_res),
  387. MAP_NOCACHE);
  388. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  389. "config", &pcie->cfg_res);
  390. if (ret) {
  391. printf("%s: resource \"config\" not found\n", dev->name);
  392. return ret;
  393. }
  394. cfg_size = fdt_resource_size(&pcie->cfg_res);
  395. if (cfg_size < SZ_4K) {
  396. printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
  397. PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
  398. return 0;
  399. }
  400. pcie->cfg = map_physmem(pcie->cfg_res.start,
  401. fdt_resource_size(&pcie->cfg_res),
  402. MAP_NOCACHE);
  403. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  404. "lut", &pcie->lut_res);
  405. if (ret) {
  406. printf("ls-pcie-g4: resource \"lut\" not found\n");
  407. return ret;
  408. }
  409. pcie->lut = map_physmem(pcie->lut_res.start,
  410. fdt_resource_size(&pcie->lut_res),
  411. MAP_NOCACHE);
  412. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  413. "pf_ctrl", &pcie->pf_ctrl_res);
  414. if (ret) {
  415. printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
  416. return ret;
  417. }
  418. pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
  419. fdt_resource_size(&pcie->pf_ctrl_res),
  420. MAP_NOCACHE);
  421. pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
  422. debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
  423. dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
  424. pcie->big_endian);
  425. pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
  426. if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
  427. printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
  428. "Endpoint");
  429. ls_pcie_g4_setup_ep(pcie);
  430. } else {
  431. printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
  432. "Root Complex");
  433. ls_pcie_g4_setup_ctrl(pcie);
  434. }
  435. /* Enable Amba & PEX PIO */
  436. val = ccsr_readl(pcie, PAB_CTRL);
  437. val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
  438. ccsr_writel(pcie, PAB_CTRL, val);
  439. val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
  440. val |= PPIO_EN;
  441. ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
  442. if (!ls_pcie_g4_link_up(pcie)) {
  443. /* Let the user know there's no PCIe link */
  444. printf(": no link\n");
  445. return 0;
  446. }
  447. /* Print the negotiated PCIe link width */
  448. link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
  449. printf(": x%d gen%d\n",
  450. (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
  451. (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
  452. return 0;
  453. }
  454. static const struct dm_pci_ops ls_pcie_g4_ops = {
  455. .read_config = ls_pcie_g4_read_config,
  456. .write_config = ls_pcie_g4_write_config,
  457. };
  458. static const struct udevice_id ls_pcie_g4_ids[] = {
  459. { .compatible = "fsl,lx2160a-pcie" },
  460. { }
  461. };
  462. U_BOOT_DRIVER(pcie_layerscape_gen4) = {
  463. .name = "pcie_layerscape_gen4",
  464. .id = UCLASS_PCI,
  465. .of_match = ls_pcie_g4_ids,
  466. .ops = &ls_pcie_g4_ops,
  467. .probe = ls_pcie_g4_probe,
  468. .priv_auto = sizeof(struct ls_pcie_g4),
  469. };