pcie_iproc.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Broadcom
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <generic-phy.h>
  10. #include <pci.h>
  11. #include <malloc.h>
  12. #include <asm/io.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/log2.h>
  15. #define EP_PERST_SOURCE_SELECT_SHIFT 2
  16. #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
  17. #define EP_MODE_SURVIVE_PERST_SHIFT 1
  18. #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
  19. #define RC_PCIE_RST_OUTPUT_SHIFT 0
  20. #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
  21. #define CFG_IND_ADDR_MASK 0x00001ffc
  22. #define CFG_ADDR_BUS_NUM_SHIFT 20
  23. #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
  24. #define CFG_ADDR_DEV_NUM_SHIFT 15
  25. #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
  26. #define CFG_ADDR_FUNC_NUM_SHIFT 12
  27. #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
  28. #define CFG_ADDR_REG_NUM_SHIFT 2
  29. #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
  30. #define CFG_ADDR_CFG_TYPE_SHIFT 0
  31. #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
  32. #define IPROC_PCI_PM_CAP 0x48
  33. #define IPROC_PCI_PM_CAP_MASK 0xffff
  34. #define IPROC_PCI_EXP_CAP 0xac
  35. #define IPROC_PCIE_REG_INVALID 0xffff
  36. #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
  37. #define PCI_EXP_RTCTL 28 /* Root Control */
  38. /* CRS Software Visibility capability */
  39. #define PCI_EXP_RTCAP_CRSVIS 0x0001
  40. #define PCI_EXP_LNKSTA 18 /* Link Status */
  41. #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
  42. #define PCIE_PHYLINKUP_SHIFT 3
  43. #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
  44. #define PCIE_DL_ACTIVE_SHIFT 2
  45. #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
  46. /* derive the enum index of the outbound/inbound mapping registers */
  47. #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
  48. /*
  49. * Maximum number of outbound mapping window sizes that can be supported by any
  50. * OARR/OMAP mapping pair
  51. */
  52. #define MAX_NUM_OB_WINDOW_SIZES 4
  53. #define OARR_VALID_SHIFT 0
  54. #define OARR_VALID BIT(OARR_VALID_SHIFT)
  55. #define OARR_SIZE_CFG_SHIFT 1
  56. /*
  57. * Maximum number of inbound mapping region sizes that can be supported by an
  58. * IARR
  59. */
  60. #define MAX_NUM_IB_REGION_SIZES 9
  61. #define IMAP_VALID_SHIFT 0
  62. #define IMAP_VALID BIT(IMAP_VALID_SHIFT)
  63. #define APB_ERR_EN_SHIFT 0
  64. #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
  65. /**
  66. * iProc PCIe host registers
  67. */
  68. enum iproc_pcie_reg {
  69. /* clock/reset signal control */
  70. IPROC_PCIE_CLK_CTRL = 0,
  71. /*
  72. * To allow MSI to be steered to an external MSI controller (e.g., ARM
  73. * GICv3 ITS)
  74. */
  75. IPROC_PCIE_MSI_GIC_MODE,
  76. /*
  77. * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
  78. * window where the MSI posted writes are written, for the writes to be
  79. * interpreted as MSI writes.
  80. */
  81. IPROC_PCIE_MSI_BASE_ADDR,
  82. IPROC_PCIE_MSI_WINDOW_SIZE,
  83. /*
  84. * To hold the address of the register where the MSI writes are
  85. * programed. When ARM GICv3 ITS is used, this should be programmed
  86. * with the address of the GITS_TRANSLATER register.
  87. */
  88. IPROC_PCIE_MSI_ADDR_LO,
  89. IPROC_PCIE_MSI_ADDR_HI,
  90. /* enable MSI */
  91. IPROC_PCIE_MSI_EN_CFG,
  92. /* allow access to root complex configuration space */
  93. IPROC_PCIE_CFG_IND_ADDR,
  94. IPROC_PCIE_CFG_IND_DATA,
  95. /* allow access to device configuration space */
  96. IPROC_PCIE_CFG_ADDR,
  97. IPROC_PCIE_CFG_DATA,
  98. /* enable INTx */
  99. IPROC_PCIE_INTX_EN,
  100. IPROC_PCIE_INTX_CSR,
  101. /* outbound address mapping */
  102. IPROC_PCIE_OARR0,
  103. IPROC_PCIE_OMAP0,
  104. IPROC_PCIE_OARR1,
  105. IPROC_PCIE_OMAP1,
  106. IPROC_PCIE_OARR2,
  107. IPROC_PCIE_OMAP2,
  108. IPROC_PCIE_OARR3,
  109. IPROC_PCIE_OMAP3,
  110. /* inbound address mapping */
  111. IPROC_PCIE_IARR0,
  112. IPROC_PCIE_IMAP0,
  113. IPROC_PCIE_IARR1,
  114. IPROC_PCIE_IMAP1,
  115. IPROC_PCIE_IARR2,
  116. IPROC_PCIE_IMAP2,
  117. IPROC_PCIE_IARR3,
  118. IPROC_PCIE_IMAP3,
  119. IPROC_PCIE_IARR4,
  120. IPROC_PCIE_IMAP4,
  121. /* config read status */
  122. IPROC_PCIE_CFG_RD_STATUS,
  123. /* link status */
  124. IPROC_PCIE_LINK_STATUS,
  125. /* enable APB error for unsupported requests */
  126. IPROC_PCIE_APB_ERR_EN,
  127. /* Ordering Mode configuration registers */
  128. IPROC_PCIE_ORDERING_CFG,
  129. IPROC_PCIE_IMAP0_RO_CONTROL,
  130. IPROC_PCIE_IMAP1_RO_CONTROL,
  131. IPROC_PCIE_IMAP2_RO_CONTROL,
  132. IPROC_PCIE_IMAP3_RO_CONTROL,
  133. IPROC_PCIE_IMAP4_RO_CONTROL,
  134. /* total number of core registers */
  135. IPROC_PCIE_MAX_NUM_REG,
  136. };
  137. /* iProc PCIe PAXB v2 registers */
  138. static const u16 iproc_pcie_reg_paxb_v2[] = {
  139. [IPROC_PCIE_CLK_CTRL] = 0x000,
  140. [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
  141. [IPROC_PCIE_CFG_IND_DATA] = 0x124,
  142. [IPROC_PCIE_CFG_ADDR] = 0x1f8,
  143. [IPROC_PCIE_CFG_DATA] = 0x1fc,
  144. [IPROC_PCIE_INTX_EN] = 0x330,
  145. [IPROC_PCIE_INTX_CSR] = 0x334,
  146. [IPROC_PCIE_OARR0] = 0xd20,
  147. [IPROC_PCIE_OMAP0] = 0xd40,
  148. [IPROC_PCIE_OARR1] = 0xd28,
  149. [IPROC_PCIE_OMAP1] = 0xd48,
  150. [IPROC_PCIE_OARR2] = 0xd60,
  151. [IPROC_PCIE_OMAP2] = 0xd68,
  152. [IPROC_PCIE_OARR3] = 0xdf0,
  153. [IPROC_PCIE_OMAP3] = 0xdf8,
  154. [IPROC_PCIE_IARR0] = 0xd00,
  155. [IPROC_PCIE_IMAP0] = 0xc00,
  156. [IPROC_PCIE_IARR2] = 0xd10,
  157. [IPROC_PCIE_IMAP2] = 0xcc0,
  158. [IPROC_PCIE_IARR3] = 0xe00,
  159. [IPROC_PCIE_IMAP3] = 0xe08,
  160. [IPROC_PCIE_IARR4] = 0xe68,
  161. [IPROC_PCIE_IMAP4] = 0xe70,
  162. [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
  163. [IPROC_PCIE_LINK_STATUS] = 0xf0c,
  164. [IPROC_PCIE_APB_ERR_EN] = 0xf40,
  165. [IPROC_PCIE_ORDERING_CFG] = 0x2000,
  166. [IPROC_PCIE_IMAP0_RO_CONTROL] = 0x201c,
  167. [IPROC_PCIE_IMAP1_RO_CONTROL] = 0x2020,
  168. [IPROC_PCIE_IMAP2_RO_CONTROL] = 0x2024,
  169. [IPROC_PCIE_IMAP3_RO_CONTROL] = 0x2028,
  170. [IPROC_PCIE_IMAP4_RO_CONTROL] = 0x202c,
  171. };
  172. /* iProc PCIe PAXC v2 registers */
  173. static const u16 iproc_pcie_reg_paxc_v2[] = {
  174. [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
  175. [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
  176. [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
  177. [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
  178. [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
  179. [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
  180. [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
  181. [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
  182. [IPROC_PCIE_CFG_ADDR] = 0x1f8,
  183. [IPROC_PCIE_CFG_DATA] = 0x1fc,
  184. };
  185. /**
  186. * List of device IDs of controllers that have corrupted
  187. * capability list that require SW fixup
  188. */
  189. static const u16 iproc_pcie_corrupt_cap_did[] = {
  190. 0x16cd,
  191. 0x16f0,
  192. 0xd802,
  193. 0xd804
  194. };
  195. enum iproc_pcie_type {
  196. IPROC_PCIE_PAXB_V2,
  197. IPROC_PCIE_PAXC,
  198. IPROC_PCIE_PAXC_V2,
  199. };
  200. /**
  201. * struct iproc_pcie_ob - iProc PCIe outbound mapping
  202. *
  203. * @axi_offset: offset from the AXI address to the internal address used by
  204. * the iProc PCIe core
  205. * @nr_windows: total number of supported outbound mapping windows
  206. */
  207. struct iproc_pcie_ob {
  208. resource_size_t axi_offset;
  209. unsigned int nr_windows;
  210. };
  211. /**
  212. * struct iproc_pcie_ib - iProc PCIe inbound mapping
  213. *
  214. * @nr_regions: total number of supported inbound mapping regions
  215. */
  216. struct iproc_pcie_ib {
  217. unsigned int nr_regions;
  218. };
  219. /**
  220. * struct iproc_pcie_ob_map - outbound mapping controller specific parameters
  221. *
  222. * @window_sizes: list of supported outbound mapping window sizes in MB
  223. * @nr_sizes: number of supported outbound mapping window sizes
  224. */
  225. struct iproc_pcie_ob_map {
  226. resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
  227. unsigned int nr_sizes;
  228. };
  229. static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
  230. {
  231. /* OARR0/OMAP0 */
  232. .window_sizes = { 128, 256 },
  233. .nr_sizes = 2,
  234. },
  235. {
  236. /* OARR1/OMAP1 */
  237. .window_sizes = { 128, 256 },
  238. .nr_sizes = 2,
  239. },
  240. {
  241. /* OARR2/OMAP2 */
  242. .window_sizes = { 128, 256, 512, 1024 },
  243. .nr_sizes = 4,
  244. },
  245. {
  246. /* OARR3/OMAP3 */
  247. .window_sizes = { 128, 256, 512, 1024 },
  248. .nr_sizes = 4,
  249. },
  250. };
  251. /**
  252. * iProc PCIe inbound mapping type
  253. */
  254. enum iproc_pcie_ib_map_type {
  255. /* for DDR memory */
  256. IPROC_PCIE_IB_MAP_MEM = 0,
  257. /* for device I/O memory */
  258. IPROC_PCIE_IB_MAP_IO,
  259. /* invalid or unused */
  260. IPROC_PCIE_IB_MAP_INVALID
  261. };
  262. /**
  263. * struct iproc_pcie_ib_map - inbound mapping controller specific parameters
  264. *
  265. * @type: inbound mapping region type
  266. * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or SZ_1G
  267. * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
  268. * GB, depedning on the size unit
  269. * @nr_sizes: number of supported inbound mapping region sizes
  270. * @nr_windows: number of supported inbound mapping windows for the region
  271. * @imap_addr_offset: register offset between the upper and lower 32-bit
  272. * IMAP address registers
  273. * @imap_window_offset: register offset between each IMAP window
  274. */
  275. struct iproc_pcie_ib_map {
  276. enum iproc_pcie_ib_map_type type;
  277. unsigned int size_unit;
  278. resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
  279. unsigned int nr_sizes;
  280. unsigned int nr_windows;
  281. u16 imap_addr_offset;
  282. u16 imap_window_offset;
  283. };
  284. static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
  285. {
  286. /* IARR0/IMAP0 */
  287. .type = IPROC_PCIE_IB_MAP_IO,
  288. .size_unit = SZ_1K,
  289. .region_sizes = { 32 },
  290. .nr_sizes = 1,
  291. .nr_windows = 8,
  292. .imap_addr_offset = 0x40,
  293. .imap_window_offset = 0x4,
  294. },
  295. {
  296. /* IARR1/IMAP1 (currently unused) */
  297. .type = IPROC_PCIE_IB_MAP_INVALID,
  298. },
  299. {
  300. /* IARR2/IMAP2 */
  301. .type = IPROC_PCIE_IB_MAP_MEM,
  302. .size_unit = SZ_1M,
  303. .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
  304. 16384 },
  305. .nr_sizes = 9,
  306. .nr_windows = 1,
  307. .imap_addr_offset = 0x4,
  308. .imap_window_offset = 0x8,
  309. },
  310. {
  311. /* IARR3/IMAP3 */
  312. .type = IPROC_PCIE_IB_MAP_MEM,
  313. .size_unit = SZ_1G,
  314. .region_sizes = { 1, 2, 4, 8, 16, 32 },
  315. .nr_sizes = 6,
  316. .nr_windows = 8,
  317. .imap_addr_offset = 0x4,
  318. .imap_window_offset = 0x8,
  319. },
  320. {
  321. /* IARR4/IMAP4 */
  322. .type = IPROC_PCIE_IB_MAP_MEM,
  323. .size_unit = SZ_1G,
  324. .region_sizes = { 32, 64, 128, 256, 512 },
  325. .nr_sizes = 5,
  326. .nr_windows = 8,
  327. .imap_addr_offset = 0x4,
  328. .imap_window_offset = 0x8,
  329. },
  330. };
  331. /**
  332. * struct iproc_pcie - iproc pcie device instance
  333. *
  334. * @dev: pointer to pcie udevice
  335. * @base: device I/O base address
  336. * @type: pci device type, PAXC or PAXB
  337. * @reg_offsets: pointer to pcie host register
  338. * @fix_paxc_cap: paxc capability
  339. * @need_ob_cfg: outbound mapping status
  340. * @ob: pcie outbound mapping
  341. * @ob_map: pointer to outbound mapping parameters
  342. * @need_ib_cfg: inbound mapping status
  343. * @ib: pcie inbound mapping
  344. * @ib_map: pointer to inbound mapping parameters
  345. * @ep_is_internal: ep status
  346. * @phy: phy device
  347. * @link_is_active: link up status
  348. * @has_apb_err_disable: apb error status
  349. */
  350. struct iproc_pcie {
  351. struct udevice *dev;
  352. void __iomem *base;
  353. enum iproc_pcie_type type;
  354. u16 *reg_offsets;
  355. bool fix_paxc_cap;
  356. bool need_ob_cfg;
  357. struct iproc_pcie_ob ob;
  358. const struct iproc_pcie_ob_map *ob_map;
  359. bool need_ib_cfg;
  360. struct iproc_pcie_ib ib;
  361. const struct iproc_pcie_ib_map *ib_map;
  362. bool ep_is_internal;
  363. struct phy phy;
  364. bool link_is_active;
  365. bool has_apb_err_disable;
  366. };
  367. static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
  368. {
  369. return !!(reg_offset == IPROC_PCIE_REG_INVALID);
  370. }
  371. static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
  372. enum iproc_pcie_reg reg)
  373. {
  374. return pcie->reg_offsets[reg];
  375. }
  376. static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
  377. enum iproc_pcie_reg reg)
  378. {
  379. u16 offset = iproc_pcie_reg_offset(pcie, reg);
  380. if (iproc_pcie_reg_is_invalid(offset))
  381. return 0;
  382. return readl(pcie->base + offset);
  383. }
  384. static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
  385. enum iproc_pcie_reg reg, u32 val)
  386. {
  387. u16 offset = iproc_pcie_reg_offset(pcie, reg);
  388. if (iproc_pcie_reg_is_invalid(offset))
  389. return;
  390. writel(val, pcie->base + offset);
  391. }
  392. static int iproc_pcie_map_ep_cfg_reg(const struct udevice *udev, pci_dev_t bdf,
  393. uint where, void **paddress)
  394. {
  395. struct iproc_pcie *pcie = dev_get_priv(udev);
  396. unsigned int busno = PCI_BUS(bdf);
  397. unsigned int slot = PCI_DEV(bdf);
  398. unsigned int fn = PCI_FUNC(bdf);
  399. u16 offset;
  400. u32 val;
  401. /* root complex access */
  402. if (busno == 0) {
  403. if (slot > 0 || fn > 0)
  404. return -ENODEV;
  405. iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
  406. where & CFG_IND_ADDR_MASK);
  407. offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
  408. if (iproc_pcie_reg_is_invalid(offset))
  409. return -ENODEV;
  410. *paddress = (pcie->base + offset);
  411. return 0;
  412. }
  413. if (!pcie->link_is_active)
  414. return -ENODEV;
  415. /* EP device access */
  416. val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
  417. (slot << CFG_ADDR_DEV_NUM_SHIFT) |
  418. (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
  419. (where & CFG_ADDR_REG_NUM_MASK) |
  420. (1 & CFG_ADDR_CFG_TYPE_MASK);
  421. iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
  422. offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
  423. if (iproc_pcie_reg_is_invalid(offset))
  424. return -ENODEV;
  425. *paddress = (pcie->base + offset);
  426. return 0;
  427. }
  428. static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, ulong *val)
  429. {
  430. u32 i, dev_id;
  431. switch (where & ~0x3) {
  432. case PCI_VENDOR_ID:
  433. dev_id = *val >> 16;
  434. /*
  435. * Activate fixup for those controllers that have corrupted
  436. * capability list registers
  437. */
  438. for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)
  439. if (dev_id == iproc_pcie_corrupt_cap_did[i])
  440. pcie->fix_paxc_cap = true;
  441. break;
  442. case IPROC_PCI_PM_CAP:
  443. if (pcie->fix_paxc_cap) {
  444. /* advertise PM, force next capability to PCIe */
  445. *val &= ~IPROC_PCI_PM_CAP_MASK;
  446. *val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM;
  447. }
  448. break;
  449. case IPROC_PCI_EXP_CAP:
  450. if (pcie->fix_paxc_cap) {
  451. /* advertise root port, version 2, terminate here */
  452. *val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 |
  453. PCI_CAP_ID_EXP;
  454. }
  455. break;
  456. case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL:
  457. /* Don't advertise CRS SV support */
  458. *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
  459. break;
  460. default:
  461. break;
  462. }
  463. }
  464. static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
  465. unsigned int devfn, int where,
  466. int size, u32 *val)
  467. {
  468. void __iomem *addr;
  469. int ret;
  470. ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
  471. if (ret) {
  472. *val = ~0;
  473. return -EINVAL;
  474. }
  475. *val = readl(addr);
  476. if (size <= 2)
  477. *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
  478. return 0;
  479. }
  480. static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
  481. unsigned int devfn, int where,
  482. int size, u32 val)
  483. {
  484. void __iomem *addr;
  485. int ret;
  486. u32 mask, tmp;
  487. ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
  488. if (ret)
  489. return -EINVAL;
  490. if (size == 4) {
  491. writel(val, addr);
  492. return 0;
  493. }
  494. mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
  495. tmp = readl(addr) & mask;
  496. tmp |= val << ((where & 0x3) * 8);
  497. writel(tmp, addr);
  498. return 0;
  499. }
  500. /**
  501. * iproc_pcie_apb_err_disable() - configure apb error
  502. *
  503. * APB error forwarding can be disabled during access of configuration
  504. * registers of the endpoint device, to prevent unsupported requests
  505. * (typically seen during enumeration with multi-function devices) from
  506. * triggering a system exception.
  507. *
  508. * @bus: pcie udevice
  509. * @bdf: pdf value
  510. * @disabled: flag to enable/disabled apb error
  511. */
  512. static inline void iproc_pcie_apb_err_disable(const struct udevice *bus,
  513. pci_dev_t bdf, bool disable)
  514. {
  515. struct iproc_pcie *pcie = dev_get_priv(bus);
  516. u32 val;
  517. if (PCI_BUS(bdf) && pcie->has_apb_err_disable) {
  518. val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
  519. if (disable)
  520. val &= ~APB_ERR_EN;
  521. else
  522. val |= APB_ERR_EN;
  523. iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
  524. }
  525. }
  526. static int iproc_pcie_config_read32(const struct udevice *bus, pci_dev_t bdf,
  527. uint offset, ulong *valuep,
  528. enum pci_size_t size)
  529. {
  530. struct iproc_pcie *pcie = dev_get_priv(bus);
  531. int ret;
  532. ulong data;
  533. iproc_pcie_apb_err_disable(bus, bdf, true);
  534. ret = pci_generic_mmap_read_config(bus, iproc_pcie_map_ep_cfg_reg,
  535. bdf, offset, &data, PCI_SIZE_32);
  536. iproc_pcie_apb_err_disable(bus, bdf, false);
  537. if (size <= PCI_SIZE_16)
  538. *valuep = (data >> (8 * (offset & 3))) &
  539. ((1 << (BIT(size) * 8)) - 1);
  540. else
  541. *valuep = data;
  542. if (!ret && PCI_BUS(bdf) == 0)
  543. iproc_pcie_fix_cap(pcie, offset, valuep);
  544. return ret;
  545. }
  546. static int iproc_pcie_config_write32(struct udevice *bus, pci_dev_t bdf,
  547. uint offset, ulong value,
  548. enum pci_size_t size)
  549. {
  550. void *addr;
  551. ulong mask, tmp;
  552. int ret;
  553. ret = iproc_pcie_map_ep_cfg_reg(bus, bdf, offset, &addr);
  554. if (ret)
  555. return ret;
  556. if (size == PCI_SIZE_32) {
  557. writel(value, addr);
  558. return ret;
  559. }
  560. iproc_pcie_apb_err_disable(bus, bdf, true);
  561. mask = ~(((1 << (BIT(size) * 8)) - 1) << ((offset & 0x3) * 8));
  562. tmp = readl(addr) & mask;
  563. tmp |= (value << ((offset & 0x3) * 8));
  564. writel(tmp, addr);
  565. iproc_pcie_apb_err_disable(bus, bdf, false);
  566. return ret;
  567. }
  568. const static struct dm_pci_ops iproc_pcie_ops = {
  569. .read_config = iproc_pcie_config_read32,
  570. .write_config = iproc_pcie_config_write32,
  571. };
  572. static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
  573. {
  574. unsigned int reg_idx;
  575. const u16 *regs;
  576. u16 num_elements;
  577. switch (pcie->type) {
  578. case IPROC_PCIE_PAXC_V2:
  579. pcie->ep_is_internal = true;
  580. regs = iproc_pcie_reg_paxc_v2;
  581. num_elements = ARRAY_SIZE(iproc_pcie_reg_paxc_v2);
  582. break;
  583. case IPROC_PCIE_PAXB_V2:
  584. regs = iproc_pcie_reg_paxb_v2;
  585. num_elements = ARRAY_SIZE(iproc_pcie_reg_paxb_v2);
  586. pcie->has_apb_err_disable = true;
  587. if (pcie->need_ob_cfg) {
  588. pcie->ob.axi_offset = 0;
  589. pcie->ob_map = paxb_v2_ob_map;
  590. pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
  591. }
  592. pcie->need_ib_cfg = true;
  593. pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
  594. pcie->ib_map = paxb_v2_ib_map;
  595. break;
  596. default:
  597. dev_dbg(pcie->dev, "incompatible iProc PCIe interface\n");
  598. return -EINVAL;
  599. }
  600. pcie->reg_offsets = calloc(IPROC_PCIE_MAX_NUM_REG,
  601. sizeof(*pcie->reg_offsets));
  602. if (!pcie->reg_offsets)
  603. return -ENOMEM;
  604. /* go through the register table and populate all valid registers */
  605. pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
  606. IPROC_PCIE_REG_INVALID : regs[0];
  607. for (reg_idx = 1; reg_idx < num_elements; reg_idx++)
  608. pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
  609. regs[reg_idx] : IPROC_PCIE_REG_INVALID;
  610. return 0;
  611. }
  612. static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
  613. int window_idx)
  614. {
  615. u32 val;
  616. val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
  617. return !!(val & OARR_VALID);
  618. }
  619. static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
  620. int size_idx, u64 axi_addr, u64 pci_addr)
  621. {
  622. u16 oarr_offset, omap_offset;
  623. /*
  624. * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based
  625. * on window index.
  626. */
  627. oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
  628. window_idx));
  629. omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
  630. window_idx));
  631. if (iproc_pcie_reg_is_invalid(oarr_offset) ||
  632. iproc_pcie_reg_is_invalid(omap_offset))
  633. return -EINVAL;
  634. /*
  635. * Program the OARR registers. The upper 32-bit OARR register is
  636. * always right after the lower 32-bit OARR register.
  637. */
  638. writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
  639. OARR_VALID, pcie->base + oarr_offset);
  640. writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
  641. /* now program the OMAP registers */
  642. writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
  643. writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
  644. debug("ob window [%d]: offset 0x%x axi %pap pci %pap\n",
  645. window_idx, oarr_offset, &axi_addr, &pci_addr);
  646. debug("oarr lo 0x%x oarr hi 0x%x\n",
  647. readl(pcie->base + oarr_offset),
  648. readl(pcie->base + oarr_offset + 4));
  649. debug("omap lo 0x%x omap hi 0x%x\n",
  650. readl(pcie->base + omap_offset),
  651. readl(pcie->base + omap_offset + 4));
  652. return 0;
  653. }
  654. /**
  655. * iproc_pcie_setup_ob() - setup outbound address mapping
  656. *
  657. * Some iProc SoCs require the SW to configure the outbound address mapping
  658. * Outbound address translation:
  659. *
  660. * iproc_pcie_address = axi_address - axi_offset
  661. * OARR = iproc_pcie_address
  662. * OMAP = pci_addr
  663. * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
  664. *
  665. * @pcie: pcie device
  666. * @axi_addr: axi address to be translated
  667. * @pci_addr: pci address
  668. * @size: window size
  669. *
  670. * @return: 0 on success and -ve on failure
  671. */
  672. static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
  673. u64 pci_addr, resource_size_t size)
  674. {
  675. struct iproc_pcie_ob *ob = &pcie->ob;
  676. int ret = -EINVAL, window_idx, size_idx;
  677. if (axi_addr < ob->axi_offset) {
  678. pr_err("axi address %pap less than offset %pap\n",
  679. &axi_addr, &ob->axi_offset);
  680. return -EINVAL;
  681. }
  682. /*
  683. * Translate the AXI address to the internal address used by the iProc
  684. * PCIe core before programming the OARR
  685. */
  686. axi_addr -= ob->axi_offset;
  687. /* iterate through all OARR/OMAP mapping windows */
  688. for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
  689. const struct iproc_pcie_ob_map *ob_map =
  690. &pcie->ob_map[window_idx];
  691. /*
  692. * If current outbound window is already in use, move on to the
  693. * next one.
  694. */
  695. if (iproc_pcie_ob_is_valid(pcie, window_idx))
  696. continue;
  697. /*
  698. * Iterate through all supported window sizes within the
  699. * OARR/OMAP pair to find a match. Go through the window sizes
  700. * in a descending order.
  701. */
  702. for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
  703. size_idx--) {
  704. resource_size_t window_size =
  705. ob_map->window_sizes[size_idx] * SZ_1M;
  706. /*
  707. * Keep iterating until we reach the last window and
  708. * with the minimal window size at index zero. In this
  709. * case, we take a compromise by mapping it using the
  710. * minimum window size that can be supported
  711. */
  712. if (size < window_size) {
  713. if (size_idx > 0 || window_idx > 0)
  714. continue;
  715. /*
  716. * For the corner case of reaching the minimal
  717. * window size that can be supported on the
  718. * last window
  719. */
  720. axi_addr = ALIGN_DOWN(axi_addr, window_size);
  721. pci_addr = ALIGN_DOWN(pci_addr, window_size);
  722. size = window_size;
  723. }
  724. if (!IS_ALIGNED(axi_addr, window_size) ||
  725. !IS_ALIGNED(pci_addr, window_size)) {
  726. pr_err("axi %pap or pci %pap not aligned\n",
  727. &axi_addr, &pci_addr);
  728. return -EINVAL;
  729. }
  730. /*
  731. * Match found! Program both OARR and OMAP and mark
  732. * them as a valid entry.
  733. */
  734. ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
  735. axi_addr, pci_addr);
  736. if (ret)
  737. goto err_ob;
  738. size -= window_size;
  739. if (size == 0)
  740. return 0;
  741. /*
  742. * If we are here, we are done with the current window,
  743. * but not yet finished all mappings. Need to move on
  744. * to the next window.
  745. */
  746. axi_addr += window_size;
  747. pci_addr += window_size;
  748. break;
  749. }
  750. }
  751. err_ob:
  752. pr_err("unable to configure outbound mapping\n");
  753. pr_err("axi %pap, axi offset %pap, pci %pap, res size %pap\n",
  754. &axi_addr, &ob->axi_offset, &pci_addr, &size);
  755. return ret;
  756. }
  757. static int iproc_pcie_map_ranges(struct udevice *dev)
  758. {
  759. struct iproc_pcie *pcie = dev_get_priv(dev);
  760. struct udevice *bus = pci_get_controller(dev);
  761. struct pci_controller *hose = dev_get_uclass_priv(bus);
  762. int i, ret;
  763. for (i = 0; i < hose->region_count; i++) {
  764. if (hose->regions[i].flags == PCI_REGION_MEM ||
  765. hose->regions[i].flags == PCI_REGION_PREFETCH) {
  766. debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
  767. i, &hose->regions[i].bus_start,
  768. &hose->regions[i].phys_start,
  769. hose->regions[i].size);
  770. ret = iproc_pcie_setup_ob(pcie,
  771. hose->regions[i].phys_start,
  772. hose->regions[i].bus_start,
  773. hose->regions[i].size);
  774. if (ret)
  775. return ret;
  776. }
  777. }
  778. return 0;
  779. }
  780. static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
  781. int region_idx)
  782. {
  783. const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
  784. u32 val;
  785. val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
  786. return !!(val & (BIT(ib_map->nr_sizes) - 1));
  787. }
  788. static inline bool
  789. iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
  790. enum iproc_pcie_ib_map_type type)
  791. {
  792. return !!(ib_map->type == type);
  793. }
  794. static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
  795. int size_idx, int nr_windows, u64 axi_addr,
  796. u64 pci_addr, resource_size_t size)
  797. {
  798. const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
  799. u16 iarr_offset, imap_offset;
  800. u32 val;
  801. int window_idx;
  802. iarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IARR0,
  803. region_idx));
  804. imap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IMAP0,
  805. region_idx));
  806. if (iproc_pcie_reg_is_invalid(iarr_offset) ||
  807. iproc_pcie_reg_is_invalid(imap_offset))
  808. return -EINVAL;
  809. debug("ib region [%d]: offset 0x%x axi %pap pci %pap\n",
  810. region_idx, iarr_offset, &axi_addr, &pci_addr);
  811. /*
  812. * Program the IARR registers. The upper 32-bit IARR register is
  813. * always right after the lower 32-bit IARR register.
  814. */
  815. writel(lower_32_bits(pci_addr) | BIT(size_idx),
  816. pcie->base + iarr_offset);
  817. writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
  818. debug("iarr lo 0x%x iarr hi 0x%x\n",
  819. readl(pcie->base + iarr_offset),
  820. readl(pcie->base + iarr_offset + 4));
  821. /*
  822. * Now program the IMAP registers. Each IARR region may have one or
  823. * more IMAP windows.
  824. */
  825. size >>= ilog2(nr_windows);
  826. for (window_idx = 0; window_idx < nr_windows; window_idx++) {
  827. val = readl(pcie->base + imap_offset);
  828. val |= lower_32_bits(axi_addr) | IMAP_VALID;
  829. writel(val, pcie->base + imap_offset);
  830. writel(upper_32_bits(axi_addr),
  831. pcie->base + imap_offset + ib_map->imap_addr_offset);
  832. debug("imap window [%d] lo 0x%x hi 0x%x\n",
  833. window_idx, readl(pcie->base + imap_offset),
  834. readl(pcie->base + imap_offset +
  835. ib_map->imap_addr_offset));
  836. imap_offset += ib_map->imap_window_offset;
  837. axi_addr += size;
  838. }
  839. return 0;
  840. }
  841. /**
  842. * iproc_pcie_setup_ib() - setup inbound address mapping
  843. *
  844. * @pcie: pcie device
  845. * @axi_addr: axi address to be translated
  846. * @pci_addr: pci address
  847. * @size: window size
  848. * @type: inbound mapping type
  849. *
  850. * @return: 0 on success and -ve on failure
  851. */
  852. static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, u64 axi_addr,
  853. u64 pci_addr, resource_size_t size,
  854. enum iproc_pcie_ib_map_type type)
  855. {
  856. struct iproc_pcie_ib *ib = &pcie->ib;
  857. int ret;
  858. unsigned int region_idx, size_idx;
  859. /* iterate through all IARR mapping regions */
  860. for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
  861. const struct iproc_pcie_ib_map *ib_map =
  862. &pcie->ib_map[region_idx];
  863. /*
  864. * If current inbound region is already in use or not a
  865. * compatible type, move on to the next.
  866. */
  867. if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
  868. !iproc_pcie_ib_check_type(ib_map, type))
  869. continue;
  870. /* iterate through all supported region sizes to find a match */
  871. for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
  872. resource_size_t region_size =
  873. ib_map->region_sizes[size_idx] * ib_map->size_unit;
  874. if (size != region_size)
  875. continue;
  876. if (!IS_ALIGNED(axi_addr, region_size) ||
  877. !IS_ALIGNED(pci_addr, region_size)) {
  878. pr_err("axi %pap or pci %pap not aligned\n",
  879. &axi_addr, &pci_addr);
  880. return -EINVAL;
  881. }
  882. /* Match found! Program IARR and all IMAP windows. */
  883. ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
  884. ib_map->nr_windows, axi_addr,
  885. pci_addr, size);
  886. if (ret)
  887. goto err_ib;
  888. else
  889. return 0;
  890. }
  891. }
  892. ret = -EINVAL;
  893. err_ib:
  894. pr_err("unable to configure inbound mapping\n");
  895. pr_err("axi %pap, pci %pap, res size %pap\n",
  896. &axi_addr, &pci_addr, &size);
  897. return ret;
  898. }
  899. static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
  900. {
  901. int ret;
  902. struct pci_region regions;
  903. int i = 0;
  904. while (!pci_get_dma_regions(pcie->dev, &regions, i)) {
  905. dev_dbg(pcie->dev,
  906. "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
  907. i, regions.bus_start, regions.phys_start, regions.size);
  908. /* Each range entry corresponds to an inbound mapping region */
  909. ret = iproc_pcie_setup_ib(pcie, regions.phys_start,
  910. regions.bus_start,
  911. regions.size,
  912. IPROC_PCIE_IB_MAP_MEM);
  913. if (ret)
  914. return ret;
  915. i++;
  916. }
  917. return 0;
  918. }
  919. static void iproc_pcie_reset_map_regs(struct iproc_pcie *pcie)
  920. {
  921. struct iproc_pcie_ib *ib = &pcie->ib;
  922. struct iproc_pcie_ob *ob = &pcie->ob;
  923. int window_idx, region_idx;
  924. if (pcie->ep_is_internal)
  925. return;
  926. /* iterate through all OARR mapping regions */
  927. for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
  928. iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_OARR0,
  929. window_idx), 0);
  930. }
  931. /* iterate through all IARR mapping regions */
  932. for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
  933. iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_IARR0,
  934. region_idx), 0);
  935. }
  936. }
  937. static void iproc_pcie_reset(struct iproc_pcie *pcie)
  938. {
  939. u32 val;
  940. /*
  941. * PAXC and the internal emulated endpoint device downstream should not
  942. * be reset. If firmware has been loaded on the endpoint device at an
  943. * earlier boot stage, reset here causes issues.
  944. */
  945. if (pcie->ep_is_internal)
  946. return;
  947. /*
  948. * Select perst_b signal as reset source. Put the device into reset,
  949. * and then bring it out of reset
  950. */
  951. val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
  952. val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
  953. ~RC_PCIE_RST_OUTPUT;
  954. iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
  955. udelay(250);
  956. val |= RC_PCIE_RST_OUTPUT;
  957. iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
  958. mdelay(100);
  959. }
  960. static inline bool iproc_pcie_link_is_active(struct iproc_pcie *pcie)
  961. {
  962. u32 val;
  963. val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
  964. return !!((val & PCIE_PHYLINKUP) && (val & PCIE_DL_ACTIVE));
  965. }
  966. static int iproc_pcie_check_link(struct iproc_pcie *pcie)
  967. {
  968. u32 link_status, class;
  969. pcie->link_is_active = false;
  970. /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
  971. #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
  972. #define PCI_CLASS_BRIDGE_MASK 0xffff00
  973. #define PCI_CLASS_BRIDGE_SHIFT 8
  974. iproc_pci_raw_config_read32(pcie, 0,
  975. PCI_BRIDGE_CTRL_REG_OFFSET,
  976. 4, &class);
  977. class &= ~PCI_CLASS_BRIDGE_MASK;
  978. class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
  979. iproc_pci_raw_config_write32(pcie, 0,
  980. PCI_BRIDGE_CTRL_REG_OFFSET,
  981. 4, class);
  982. /*
  983. * PAXC connects to emulated endpoint devices directly and does not
  984. * have a Serdes. Therefore skip the link detection logic here.
  985. */
  986. if (pcie->ep_is_internal) {
  987. pcie->link_is_active = true;
  988. return 0;
  989. }
  990. if (!iproc_pcie_link_is_active(pcie)) {
  991. pr_err("PHY or data link is INACTIVE!\n");
  992. return -ENODEV;
  993. }
  994. #define PCI_TARGET_LINK_SPEED_MASK 0xf
  995. #define PCI_TARGET_LINK_WIDTH_MASK 0x3f
  996. #define PCI_TARGET_LINK_WIDTH_OFFSET 0x4
  997. /* check link status to see if link is active */
  998. iproc_pci_raw_config_read32(pcie, 0,
  999. IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
  1000. 2, &link_status);
  1001. if (link_status & PCI_EXP_LNKSTA_NLW)
  1002. pcie->link_is_active = true;
  1003. if (pcie->link_is_active)
  1004. pr_info("link UP @ Speed Gen-%d and width-x%d\n",
  1005. link_status & PCI_TARGET_LINK_SPEED_MASK,
  1006. (link_status >> PCI_TARGET_LINK_WIDTH_OFFSET) &
  1007. PCI_TARGET_LINK_WIDTH_MASK);
  1008. else
  1009. pr_info("link DOWN\n");
  1010. return 0;
  1011. }
  1012. static int iproc_pcie_probe(struct udevice *dev)
  1013. {
  1014. struct iproc_pcie *pcie = dev_get_priv(dev);
  1015. int ret;
  1016. pcie->type = (enum iproc_pcie_type)dev_get_driver_data(dev);
  1017. debug("PAX type %d\n", pcie->type);
  1018. pcie->base = dev_read_addr_ptr(dev);
  1019. debug("PAX reg base %p\n", pcie->base);
  1020. if (!pcie->base)
  1021. return -ENODEV;
  1022. if (dev_read_bool(dev, "brcm,pcie-ob"))
  1023. pcie->need_ob_cfg = true;
  1024. pcie->dev = dev;
  1025. ret = iproc_pcie_rev_init(pcie);
  1026. if (ret)
  1027. return ret;
  1028. if (!pcie->ep_is_internal) {
  1029. ret = generic_phy_get_by_name(dev, "pcie-phy", &pcie->phy);
  1030. if (!ret) {
  1031. ret = generic_phy_init(&pcie->phy);
  1032. if (ret) {
  1033. pr_err("failed to init %s PHY\n", dev->name);
  1034. return ret;
  1035. }
  1036. ret = generic_phy_power_on(&pcie->phy);
  1037. if (ret) {
  1038. pr_err("power on %s PHY failed\n", dev->name);
  1039. goto err_exit_phy;
  1040. }
  1041. }
  1042. }
  1043. iproc_pcie_reset(pcie);
  1044. if (pcie->need_ob_cfg) {
  1045. ret = iproc_pcie_map_ranges(dev);
  1046. if (ret) {
  1047. pr_err("outbound map failed\n");
  1048. goto err_power_off_phy;
  1049. }
  1050. }
  1051. if (pcie->need_ib_cfg) {
  1052. ret = iproc_pcie_map_dma_ranges(pcie);
  1053. if (ret) {
  1054. pr_err("inbound map failed\n");
  1055. goto err_power_off_phy;
  1056. }
  1057. }
  1058. if (iproc_pcie_check_link(pcie))
  1059. pr_info("no PCIe EP device detected\n");
  1060. return 0;
  1061. err_power_off_phy:
  1062. generic_phy_power_off(&pcie->phy);
  1063. err_exit_phy:
  1064. generic_phy_exit(&pcie->phy);
  1065. return ret;
  1066. }
  1067. static int iproc_pcie_remove(struct udevice *dev)
  1068. {
  1069. struct iproc_pcie *pcie = dev_get_priv(dev);
  1070. int ret;
  1071. iproc_pcie_reset_map_regs(pcie);
  1072. if (generic_phy_valid(&pcie->phy)) {
  1073. ret = generic_phy_power_off(&pcie->phy);
  1074. if (ret) {
  1075. pr_err("failed to power off PCIe phy\n");
  1076. return ret;
  1077. }
  1078. ret = generic_phy_exit(&pcie->phy);
  1079. if (ret) {
  1080. pr_err("failed to power off PCIe phy\n");
  1081. return ret;
  1082. }
  1083. }
  1084. return 0;
  1085. }
  1086. static const struct udevice_id pci_iproc_ids[] = {
  1087. { .compatible = "brcm,iproc-pcie-paxb-v2",
  1088. .data = IPROC_PCIE_PAXB_V2 },
  1089. { .compatible = "brcm,iproc-pcie-paxc-v2",
  1090. .data = IPROC_PCIE_PAXC_V2 },
  1091. { }
  1092. };
  1093. U_BOOT_DRIVER(pci_iproc) = {
  1094. .name = "pci_iproc",
  1095. .id = UCLASS_PCI,
  1096. .of_match = pci_iproc_ids,
  1097. .ops = &iproc_pcie_ops,
  1098. .probe = iproc_pcie_probe,
  1099. .remove = iproc_pcie_remove,
  1100. .priv_auto = sizeof(struct iproc_pcie),
  1101. .flags = DM_FLAG_OS_PREPARE,
  1102. };