pcie_intel_fpga.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel FPGA PCIe host controller driver
  4. *
  5. * Copyright (C) 2013-2018 Intel Corporation. All rights reserved
  6. *
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <pci.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #define RP_TX_REG0 0x2000
  17. #define RP_TX_CNTRL 0x2004
  18. #define RP_TX_SOP BIT(0)
  19. #define RP_TX_EOP BIT(1)
  20. #define RP_RXCPL_STATUS 0x200C
  21. #define RP_RXCPL_SOP BIT(0)
  22. #define RP_RXCPL_EOP BIT(1)
  23. #define RP_RXCPL_REG 0x2008
  24. #define P2A_INT_STATUS 0x3060
  25. #define P2A_INT_STS_ALL 0xf
  26. #define P2A_INT_ENABLE 0x3070
  27. #define RP_CAP_OFFSET 0x70
  28. /* TLP configuration type 0 and 1 */
  29. #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
  30. #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
  31. #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
  32. #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
  33. #define TLP_PAYLOAD_SIZE 0x01
  34. #define TLP_READ_TAG 0x1d
  35. #define TLP_WRITE_TAG 0x10
  36. #define RP_DEVFN 0
  37. #define RP_CFG_ADDR(pcie, reg) \
  38. ((pcie->hip_base) + (reg) + (1 << 20))
  39. #define RP_SECONDARY(pcie) \
  40. readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
  41. #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
  42. #define TLP_CFGRD_DW0(pcie, bus) \
  43. ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
  44. : TLP_FMTTYPE_CFGRD0) << 24) | \
  45. TLP_PAYLOAD_SIZE)
  46. #define TLP_CFGWR_DW0(pcie, bus) \
  47. ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
  48. : TLP_FMTTYPE_CFGWR0) << 24) | \
  49. TLP_PAYLOAD_SIZE)
  50. #define TLP_CFG_DW1(pcie, tag, be) \
  51. (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
  52. #define TLP_CFG_DW2(bus, dev, fn, offset) \
  53. (((bus) << 24) | ((dev) << 19) | ((fn) << 16) | (offset))
  54. #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
  55. #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
  56. #define TLP_HDR_SIZE 3
  57. #define TLP_LOOP 20000
  58. #define DWORD_MASK 3
  59. #define IS_ROOT_PORT(pcie, bdf) \
  60. ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
  61. /**
  62. * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  63. * @bus: Pointer to the PCI bus
  64. * @cra_base: The base address of CRA register space
  65. * @hip_base: The base address of Rootport configuration space
  66. * @first_busno: This driver supports multiple PCIe controllers.
  67. * first_busno stores the bus number of the PCIe root-port
  68. * number which may vary depending on the PCIe setup.
  69. */
  70. struct intel_fpga_pcie {
  71. struct udevice *bus;
  72. void __iomem *cra_base;
  73. void __iomem *hip_base;
  74. int first_busno;
  75. };
  76. /**
  77. * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
  78. * translation from PCI bus to native BUS. Entire DDR region is mapped
  79. * into PCIe space using these registers, so it can be reached by DMA from
  80. * EP devices.
  81. * The BAR0 of bridge should be hidden during enumeration to avoid the
  82. * sizing and resource allocation by PCIe core.
  83. */
  84. static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie,
  85. pci_dev_t bdf, int offset)
  86. {
  87. if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
  88. PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0)
  89. return true;
  90. return false;
  91. }
  92. static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value,
  93. const u32 reg)
  94. {
  95. writel(value, pcie->cra_base + reg);
  96. }
  97. static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg)
  98. {
  99. return readl(pcie->cra_base + reg);
  100. }
  101. static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie)
  102. {
  103. return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA))
  104. & PCI_EXP_LNKSTA_DLLLA);
  105. }
  106. static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie,
  107. pci_dev_t bdf)
  108. {
  109. /* If there is no link, then there is no device */
  110. if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie))
  111. return false;
  112. /* access only one slot on each root port */
  113. if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0)
  114. return false;
  115. if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)
  116. return false;
  117. return true;
  118. }
  119. static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl)
  120. {
  121. cra_writel(pcie, reg0, RP_TX_REG0);
  122. cra_writel(pcie, ctrl, RP_TX_CNTRL);
  123. }
  124. static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
  125. {
  126. int i;
  127. u32 ctrl;
  128. u32 comp_status;
  129. u32 dw[4];
  130. u32 count = 0;
  131. for (i = 0; i < TLP_LOOP; i++) {
  132. ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
  133. if (!(ctrl & RP_RXCPL_SOP))
  134. continue;
  135. /* read first DW */
  136. dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
  137. /* Poll for EOP */
  138. for (i = 0; i < TLP_LOOP; i++) {
  139. ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
  140. dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
  141. if (ctrl & RP_RXCPL_EOP) {
  142. comp_status = TLP_COMP_STATUS(dw[1]);
  143. if (comp_status) {
  144. *value = pci_get_ff(PCI_SIZE_32);
  145. return 0;
  146. }
  147. if (value &&
  148. TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
  149. count >= 3)
  150. *value = dw[3];
  151. return 0;
  152. }
  153. }
  154. udelay(5);
  155. }
  156. dev_err(pcie->dev, "read TLP packet timed out\n");
  157. return -ENODEV;
  158. }
  159. static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers,
  160. u32 data)
  161. {
  162. tlp_write_tx(pcie, headers[0], RP_TX_SOP);
  163. tlp_write_tx(pcie, headers[1], 0);
  164. tlp_write_tx(pcie, headers[2], 0);
  165. tlp_write_tx(pcie, data, RP_TX_EOP);
  166. }
  167. static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
  168. int offset, u8 byte_en, u32 *value)
  169. {
  170. u32 headers[TLP_HDR_SIZE];
  171. u8 busno = PCI_BUS(bdf);
  172. headers[0] = TLP_CFGRD_DW0(pcie, busno);
  173. headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
  174. headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
  175. tlp_write_packet(pcie, headers, 0);
  176. return tlp_read_packet(pcie, value);
  177. }
  178. static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
  179. int offset, u8 byte_en, u32 value)
  180. {
  181. u32 headers[TLP_HDR_SIZE];
  182. u8 busno = PCI_BUS(bdf);
  183. headers[0] = TLP_CFGWR_DW0(pcie, busno);
  184. headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
  185. headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
  186. tlp_write_packet(pcie, headers, value);
  187. return tlp_read_packet(pcie, NULL);
  188. }
  189. int intel_fpga_rp_conf_addr(const struct udevice *bus, pci_dev_t bdf,
  190. uint offset, void **paddress)
  191. {
  192. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  193. *paddress = RP_CFG_ADDR(pcie, offset);
  194. return 0;
  195. }
  196. static int intel_fpga_pcie_rp_rd_conf(struct udevice *bus, pci_dev_t bdf,
  197. uint offset, ulong *valuep,
  198. enum pci_size_t size)
  199. {
  200. return pci_generic_mmap_read_config(bus, intel_fpga_rp_conf_addr,
  201. bdf, offset, valuep, size);
  202. }
  203. static int intel_fpga_pcie_rp_wr_conf(struct udevice *bus, pci_dev_t bdf,
  204. uint offset, ulong value,
  205. enum pci_size_t size)
  206. {
  207. int ret;
  208. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  209. ret = pci_generic_mmap_write_config(bus, intel_fpga_rp_conf_addr,
  210. bdf, offset, value, size);
  211. if (!ret) {
  212. /* Monitor changes to PCI_PRIMARY_BUS register on root port
  213. * and update local copy of root bus number accordingly.
  214. */
  215. if (offset == PCI_PRIMARY_BUS)
  216. pcie->first_busno = (u8)(value);
  217. }
  218. return ret;
  219. }
  220. static u8 pcie_get_byte_en(uint offset, enum pci_size_t size)
  221. {
  222. switch (size) {
  223. case PCI_SIZE_8:
  224. return 1 << (offset & 3);
  225. case PCI_SIZE_16:
  226. return 3 << (offset & 3);
  227. default:
  228. return 0xf;
  229. }
  230. }
  231. static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie,
  232. pci_dev_t bdf, uint offset,
  233. ulong *valuep, enum pci_size_t size)
  234. {
  235. int ret;
  236. u32 data;
  237. u8 byte_en;
  238. /* Uses memory mapped method to read rootport config registers */
  239. if (IS_ROOT_PORT(pcie, bdf))
  240. return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,
  241. offset, valuep, size);
  242. byte_en = pcie_get_byte_en(offset, size);
  243. ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK,
  244. byte_en, &data);
  245. if (ret)
  246. return ret;
  247. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  248. offset, size, data);
  249. *valuep = pci_conv_32_to_size(data, offset, size);
  250. return 0;
  251. }
  252. static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie,
  253. pci_dev_t bdf, uint offset,
  254. ulong value, enum pci_size_t size)
  255. {
  256. u32 data;
  257. u8 byte_en;
  258. dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",
  259. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  260. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  261. offset, size, value);
  262. /* Uses memory mapped method to read rootport config registers */
  263. if (IS_ROOT_PORT(pcie, bdf))
  264. return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,
  265. value, size);
  266. byte_en = pcie_get_byte_en(offset, size);
  267. data = pci_conv_size_to_32(0, value, offset, size);
  268. return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK,
  269. byte_en, data);
  270. }
  271. static int pcie_intel_fpga_read_config(const struct udevice *bus, pci_dev_t bdf,
  272. uint offset, ulong *valuep,
  273. enum pci_size_t size)
  274. {
  275. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  276. dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n",
  277. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  278. if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) {
  279. *valuep = (u32)pci_get_ff(size);
  280. return 0;
  281. }
  282. if (!intel_fpga_pcie_addr_valid(pcie, bdf)) {
  283. *valuep = (u32)pci_get_ff(size);
  284. return 0;
  285. }
  286. return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size);
  287. }
  288. static int pcie_intel_fpga_write_config(struct udevice *bus, pci_dev_t bdf,
  289. uint offset, ulong value,
  290. enum pci_size_t size)
  291. {
  292. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  293. if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset))
  294. return 0;
  295. if (!intel_fpga_pcie_addr_valid(pcie, bdf))
  296. return 0;
  297. return _pcie_intel_fpga_write_config(pcie, bdf, offset, value,
  298. size);
  299. }
  300. static int pcie_intel_fpga_probe(struct udevice *dev)
  301. {
  302. struct intel_fpga_pcie *pcie = dev_get_priv(dev);
  303. pcie->bus = pci_get_controller(dev);
  304. pcie->first_busno = dev_seq(dev);
  305. /* clear all interrupts */
  306. cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
  307. /* disable all interrupts */
  308. cra_writel(pcie, 0, P2A_INT_ENABLE);
  309. return 0;
  310. }
  311. static int pcie_intel_fpga_of_to_plat(struct udevice *dev)
  312. {
  313. struct intel_fpga_pcie *pcie = dev_get_priv(dev);
  314. struct fdt_resource reg_res;
  315. int node = dev_of_offset(dev);
  316. int ret;
  317. DECLARE_GLOBAL_DATA_PTR;
  318. ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
  319. "Cra", &reg_res);
  320. if (ret) {
  321. dev_err(dev, "resource \"Cra\" not found\n");
  322. return ret;
  323. }
  324. pcie->cra_base = map_physmem(reg_res.start,
  325. fdt_resource_size(&reg_res),
  326. MAP_NOCACHE);
  327. ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
  328. "Hip", &reg_res);
  329. if (ret) {
  330. dev_err(dev, "resource \"Hip\" not found\n");
  331. return ret;
  332. }
  333. pcie->hip_base = map_physmem(reg_res.start,
  334. fdt_resource_size(&reg_res),
  335. MAP_NOCACHE);
  336. return 0;
  337. }
  338. static const struct dm_pci_ops pcie_intel_fpga_ops = {
  339. .read_config = pcie_intel_fpga_read_config,
  340. .write_config = pcie_intel_fpga_write_config,
  341. };
  342. static const struct udevice_id pcie_intel_fpga_ids[] = {
  343. { .compatible = "altr,pcie-root-port-2.0" },
  344. {},
  345. };
  346. U_BOOT_DRIVER(pcie_intel_fpga) = {
  347. .name = "pcie_intel_fpga",
  348. .id = UCLASS_PCI,
  349. .of_match = pcie_intel_fpga_ids,
  350. .ops = &pcie_intel_fpga_ops,
  351. .of_to_plat = pcie_intel_fpga_of_to_plat,
  352. .probe = pcie_intel_fpga_probe,
  353. .priv_auto = sizeof(struct intel_fpga_pcie),
  354. };