pcie_fsl.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2019 NXP
  4. *
  5. * PCIe DM U-Boot driver for Freescale PowerPC SoCs
  6. * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <mapmem.h>
  12. #include <pci.h>
  13. #include <asm/fsl_pci.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <linux/delay.h>
  18. #include "pcie_fsl.h"
  19. #include <dm/device_compat.h>
  20. LIST_HEAD(fsl_pcie_list);
  21. static int fsl_pcie_link_up(struct fsl_pcie *pcie);
  22. static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
  23. {
  24. struct udevice *bus = pcie->bus;
  25. if (!pcie->enabled)
  26. return -ENXIO;
  27. if (PCI_BUS(bdf) < dev_seq(bus))
  28. return -EINVAL;
  29. if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode))
  30. return -EINVAL;
  31. if (PCI_BUS(bdf) == dev_seq(bus) && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
  32. return -EINVAL;
  33. if (PCI_BUS(bdf) == (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
  34. return -EINVAL;
  35. return 0;
  36. }
  37. static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  38. uint offset, ulong *valuep,
  39. enum pci_size_t size)
  40. {
  41. struct fsl_pcie *pcie = dev_get_priv(bus);
  42. ccsr_fsl_pci_t *regs = pcie->regs;
  43. u32 val;
  44. if (fsl_pcie_addr_valid(pcie, bdf)) {
  45. *valuep = pci_get_ff(size);
  46. return 0;
  47. }
  48. bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
  49. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  50. out_be32(&regs->cfg_addr, val);
  51. sync();
  52. switch (size) {
  53. case PCI_SIZE_8:
  54. *valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
  55. break;
  56. case PCI_SIZE_16:
  57. *valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
  58. (offset & 2)));
  59. break;
  60. case PCI_SIZE_32:
  61. *valuep = in_le32(&regs->cfg_data);
  62. break;
  63. }
  64. return 0;
  65. }
  66. static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  67. uint offset, ulong value,
  68. enum pci_size_t size)
  69. {
  70. struct fsl_pcie *pcie = dev_get_priv(bus);
  71. ccsr_fsl_pci_t *regs = pcie->regs;
  72. u32 val;
  73. u8 val_8;
  74. u16 val_16;
  75. u32 val_32;
  76. if (fsl_pcie_addr_valid(pcie, bdf))
  77. return 0;
  78. bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
  79. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  80. out_be32(&regs->cfg_addr, val);
  81. sync();
  82. switch (size) {
  83. case PCI_SIZE_8:
  84. val_8 = value;
  85. out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
  86. break;
  87. case PCI_SIZE_16:
  88. val_16 = value;
  89. out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
  90. break;
  91. case PCI_SIZE_32:
  92. val_32 = value;
  93. out_le32(&regs->cfg_data, val_32);
  94. break;
  95. }
  96. return 0;
  97. }
  98. static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
  99. ulong *valuep, enum pci_size_t size)
  100. {
  101. int ret;
  102. struct udevice *bus = pcie->bus;
  103. ret = fsl_pcie_read_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
  104. offset, valuep, size);
  105. return ret;
  106. }
  107. static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
  108. ulong value, enum pci_size_t size)
  109. {
  110. struct udevice *bus = pcie->bus;
  111. return fsl_pcie_write_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
  112. offset, value, size);
  113. }
  114. static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
  115. u8 *valuep)
  116. {
  117. ulong val;
  118. int ret;
  119. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
  120. *valuep = val;
  121. return ret;
  122. }
  123. static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
  124. u16 *valuep)
  125. {
  126. ulong val;
  127. int ret;
  128. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
  129. *valuep = val;
  130. return ret;
  131. }
  132. static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
  133. u32 *valuep)
  134. {
  135. ulong val;
  136. int ret;
  137. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
  138. *valuep = val;
  139. return ret;
  140. }
  141. static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
  142. u8 value)
  143. {
  144. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
  145. }
  146. static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
  147. u16 value)
  148. {
  149. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
  150. }
  151. static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
  152. u32 value)
  153. {
  154. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
  155. }
  156. static int fsl_pcie_link_up(struct fsl_pcie *pcie)
  157. {
  158. ccsr_fsl_pci_t *regs = pcie->regs;
  159. u16 ltssm;
  160. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  161. ltssm = (in_be32(&regs->pex_csr0)
  162. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  163. return ltssm == LTSSM_L0_REV3;
  164. }
  165. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  166. return ltssm == LTSSM_L0;
  167. }
  168. static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
  169. {
  170. u8 header_type;
  171. fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
  172. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  173. }
  174. static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
  175. {
  176. struct pci_region *io, *mem, *pref;
  177. pci_get_regions(pcie->bus, &io, &mem, &pref);
  178. if (mem)
  179. set_next_law(mem->phys_start,
  180. law_size_bits(mem->size),
  181. pcie->law_trgt_if);
  182. if (io)
  183. set_next_law(io->phys_start,
  184. law_size_bits(io->size),
  185. pcie->law_trgt_if);
  186. return 0;
  187. }
  188. static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
  189. {
  190. ccsr_fsl_pci_t *regs = pcie->regs;
  191. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  192. setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
  193. return;
  194. }
  195. fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
  196. }
  197. static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
  198. int type, u64 phys, u64 bus_addr,
  199. pci_size_t size)
  200. {
  201. ccsr_fsl_pci_t *regs = pcie->regs;
  202. pot_t *po = &regs->pot[idx];
  203. u32 war, sz;
  204. if (idx < 0)
  205. return -EINVAL;
  206. out_be32(&po->powbar, phys >> 12);
  207. out_be32(&po->potar, bus_addr >> 12);
  208. #ifdef CONFIG_SYS_PCI_64BIT
  209. out_be32(&po->potear, bus_addr >> 44);
  210. #else
  211. out_be32(&po->potear, 0);
  212. #endif
  213. sz = (__ilog2_u64((u64)size) - 1);
  214. war = POWAR_EN | sz;
  215. if (type == PCI_REGION_IO)
  216. war |= POWAR_IO_READ | POWAR_IO_WRITE;
  217. else
  218. war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
  219. out_be32(&po->powar, war);
  220. return 0;
  221. }
  222. static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
  223. bool pf, u64 phys, u64 bus_addr,
  224. pci_size_t size)
  225. {
  226. ccsr_fsl_pci_t *regs = pcie->regs;
  227. pit_t *pi = &regs->pit[idx];
  228. u32 sz = (__ilog2_u64(size) - 1);
  229. u32 flag = PIWAR_LOCAL;
  230. if (idx < 0)
  231. return -EINVAL;
  232. out_be32(&pi->pitar, phys >> 12);
  233. out_be32(&pi->piwbar, bus_addr >> 12);
  234. #ifdef CONFIG_SYS_PCI_64BIT
  235. out_be32(&pi->piwbear, bus_addr >> 44);
  236. #else
  237. out_be32(&pi->piwbear, 0);
  238. #endif
  239. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  240. flag = 0;
  241. #endif
  242. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  243. if (pf)
  244. flag |= PIWAR_PF;
  245. out_be32(&pi->piwar, flag | sz);
  246. return 0;
  247. }
  248. static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
  249. {
  250. struct pci_region *io, *mem, *pref;
  251. int idx = 1; /* skip 0 */
  252. pci_get_regions(pcie->bus, &io, &mem, &pref);
  253. if (io)
  254. /* ATU : OUTBOUND : IO */
  255. fsl_pcie_setup_outbound_win(pcie, idx++,
  256. PCI_REGION_IO,
  257. io->phys_start,
  258. io->bus_start,
  259. io->size);
  260. if (mem)
  261. /* ATU : OUTBOUND : MEM */
  262. fsl_pcie_setup_outbound_win(pcie, idx++,
  263. PCI_REGION_MEM,
  264. mem->phys_start,
  265. mem->bus_start,
  266. mem->size);
  267. return 0;
  268. }
  269. static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
  270. {
  271. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  272. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  273. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  274. pci_size_t pci_sz;
  275. int idx;
  276. if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
  277. idx = 2;
  278. else
  279. idx = 3;
  280. pci_sz = 1ull << __ilog2_u64(sz);
  281. dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
  282. (u64)bus_start, (u64)phys_start, (u64)sz);
  283. /* if we aren't an exact power of two match, pci_sz is smaller
  284. * round it up to the next power of two. We report the actual
  285. * size to pci region tracking.
  286. */
  287. if (pci_sz != sz)
  288. sz = 2ull << __ilog2_u64(sz);
  289. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  290. CONFIG_SYS_PCI_MEMORY_PHYS,
  291. CONFIG_SYS_PCI_MEMORY_BUS, sz);
  292. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  293. /*
  294. * On 64-bit capable systems, set up a mapping for all of DRAM
  295. * in high pci address space.
  296. */
  297. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  298. /* round up to the next largest power of two */
  299. if (gd->ram_size > pci_sz)
  300. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  301. dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
  302. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  303. (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
  304. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  305. CONFIG_SYS_PCI_MEMORY_PHYS,
  306. CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
  307. #endif
  308. return 0;
  309. }
  310. static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
  311. {
  312. fsl_pcie_setup_outbound_wins(pcie);
  313. fsl_pcie_setup_inbound_wins(pcie);
  314. return 0;
  315. }
  316. static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
  317. bool enable)
  318. {
  319. u32 val;
  320. fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val);
  321. if (enable)
  322. val |= 1;
  323. else
  324. val &= ~1;
  325. fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
  326. }
  327. static int fsl_pcie_init_port(struct fsl_pcie *pcie)
  328. {
  329. ccsr_fsl_pci_t *regs = pcie->regs;
  330. u32 val_32;
  331. u16 val_16;
  332. fsl_pcie_init_atmu(pcie);
  333. #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
  334. val_32 = 0;
  335. fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
  336. val_32 &= ~0x03;
  337. fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
  338. udelay(1);
  339. #endif
  340. #ifdef CONFIG_FSL_PCIE_RESET
  341. u16 ltssm;
  342. int i;
  343. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  344. /* assert PCIe reset */
  345. setbits_be32(&regs->pdb_stat, 0x08000000);
  346. (void)in_be32(&regs->pdb_stat);
  347. udelay(1000);
  348. /* clear PCIe reset */
  349. clrbits_be32(&regs->pdb_stat, 0x08000000);
  350. asm("sync;isync");
  351. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  352. udelay(1000);
  353. } else {
  354. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  355. if (ltssm == 1) {
  356. /* assert PCIe reset */
  357. setbits_be32(&regs->pdb_stat, 0x08000000);
  358. (void)in_be32(&regs->pdb_stat);
  359. udelay(100);
  360. /* clear PCIe reset */
  361. clrbits_be32(&regs->pdb_stat, 0x08000000);
  362. asm("sync;isync");
  363. for (i = 0; i < 100 &&
  364. !fsl_pcie_link_up(pcie); i++)
  365. udelay(1000);
  366. }
  367. }
  368. #endif
  369. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  370. if (!fsl_pcie_link_up(pcie)) {
  371. serdes_corenet_t *srds_regs;
  372. srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  373. val_32 = in_be32(&srds_regs->srdspccr0);
  374. if ((val_32 >> 28) == 3) {
  375. int i;
  376. out_be32(&srds_regs->srdspccr0, 2 << 28);
  377. setbits_be32(&regs->pdb_stat, 0x08000000);
  378. in_be32(&regs->pdb_stat);
  379. udelay(100);
  380. clrbits_be32(&regs->pdb_stat, 0x08000000);
  381. asm("sync;isync");
  382. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  383. udelay(1000);
  384. }
  385. }
  386. #endif
  387. /*
  388. * The Read-Only Write Enable bit defaults to 1 instead of 0.
  389. * Set to 0 to protect the read-only registers.
  390. */
  391. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  392. fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
  393. #endif
  394. /*
  395. * Enable All Error Interrupts except
  396. * - Master abort (pci)
  397. * - Master PERR (pci)
  398. * - ICCA (PCIe)
  399. */
  400. out_be32(&regs->peer, ~0x20140);
  401. /* set URR, FER, NFER (but not CER) */
  402. fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
  403. val_32 |= 0xf000e;
  404. fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
  405. /* Clear all error indications */
  406. out_be32(&regs->pme_msg_det, 0xffffffff);
  407. out_be32(&regs->pme_msg_int_en, 0xffffffff);
  408. out_be32(&regs->pedr, 0xffffffff);
  409. fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
  410. if (val_16)
  411. fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
  412. fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
  413. if (val_16)
  414. fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
  415. return 0;
  416. }
  417. static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
  418. {
  419. u32 classcode_reg;
  420. u32 val;
  421. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  422. classcode_reg = PCI_CLASS_REVISION;
  423. fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
  424. } else {
  425. classcode_reg = CSR_CLASSCODE;
  426. }
  427. fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
  428. val &= 0xff;
  429. val |= PCI_CLASS_BRIDGE_PCI << 16;
  430. fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
  431. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
  432. fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
  433. return 0;
  434. }
  435. static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
  436. {
  437. return fsl_pcie_fixup_classcode(pcie);
  438. }
  439. static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
  440. {
  441. fsl_pcie_config_ready(pcie);
  442. return 0;
  443. }
  444. static int fsl_pcie_probe(struct udevice *dev)
  445. {
  446. struct fsl_pcie *pcie = dev_get_priv(dev);
  447. ccsr_fsl_pci_t *regs = pcie->regs;
  448. u16 val_16;
  449. pcie->bus = dev;
  450. pcie->block_rev = in_be32(&regs->block_rev1);
  451. list_add(&pcie->list, &fsl_pcie_list);
  452. pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
  453. if (!pcie->enabled) {
  454. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  455. return 0;
  456. }
  457. fsl_pcie_setup_law(pcie);
  458. pcie->mode = fsl_pcie_is_agent(pcie);
  459. fsl_pcie_init_port(pcie);
  460. printf("PCIe%d: %s ", pcie->idx, dev->name);
  461. if (pcie->mode) {
  462. printf("Endpoint");
  463. fsl_pcie_init_ep(pcie);
  464. } else {
  465. printf("Root Complex");
  466. fsl_pcie_init_rc(pcie);
  467. }
  468. if (!fsl_pcie_link_up(pcie)) {
  469. printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
  470. return 0;
  471. }
  472. fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
  473. printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
  474. return 0;
  475. }
  476. static int fsl_pcie_of_to_plat(struct udevice *dev)
  477. {
  478. struct fsl_pcie *pcie = dev_get_priv(dev);
  479. struct fsl_pcie_data *info;
  480. int ret;
  481. pcie->regs = dev_remap_addr(dev);
  482. if (!pcie->regs) {
  483. pr_err("\"reg\" resource not found\n");
  484. return -EINVAL;
  485. }
  486. ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
  487. if (ret < 0) {
  488. pr_err("\"law_trgt_if\" not found\n");
  489. return ret;
  490. }
  491. info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
  492. pcie->info = info;
  493. pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
  494. info->block_offset) / info->stride;
  495. return 0;
  496. }
  497. static const struct dm_pci_ops fsl_pcie_ops = {
  498. .read_config = fsl_pcie_read_config,
  499. .write_config = fsl_pcie_write_config,
  500. };
  501. static struct fsl_pcie_data p1_p2_data = {
  502. .block_offset = 0xa000,
  503. .block_offset_mask = 0xffff,
  504. .stride = 0x1000,
  505. };
  506. static struct fsl_pcie_data p2041_data = {
  507. .block_offset = 0x200000,
  508. .block_offset_mask = 0x3fffff,
  509. .stride = 0x1000,
  510. };
  511. static struct fsl_pcie_data t2080_data = {
  512. .block_offset = 0x240000,
  513. .block_offset_mask = 0x3fffff,
  514. .stride = 0x10000,
  515. };
  516. static const struct udevice_id fsl_pcie_ids[] = {
  517. { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
  518. { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
  519. { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
  520. { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
  521. { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
  522. { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
  523. { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
  524. { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
  525. { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
  526. { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
  527. { }
  528. };
  529. U_BOOT_DRIVER(fsl_pcie) = {
  530. .name = "fsl_pcie",
  531. .id = UCLASS_PCI,
  532. .of_match = fsl_pcie_ids,
  533. .ops = &fsl_pcie_ops,
  534. .of_to_plat = fsl_pcie_of_to_plat,
  535. .probe = fsl_pcie_probe,
  536. .priv_auto = sizeof(struct fsl_pcie),
  537. };