pcie_ecam_synquacer.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SynQuacer PCIE host driver
  4. *
  5. * Based on drivers/pci/pcie_ecam_generic.c
  6. *
  7. * Copyright (C) 2016 Imagination Technologies
  8. * Copyright (C) 2021 Linaro Ltd.
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <pci.h>
  13. #include <log.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. /* iATU registers */
  18. #define IATU_VIEWPORT_OFF 0x900
  19. #define IATU_VIEWPORT_INBOUND BIT(31)
  20. #define IATU_VIEWPORT_OUTBOUND 0
  21. #define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7)
  22. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
  23. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
  24. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
  25. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
  26. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
  27. #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT(12)
  28. #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
  29. #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31)
  30. #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT(28)
  31. #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF
  32. #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF
  33. #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
  34. #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
  35. #define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
  36. #define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
  37. #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
  38. /* Clock and resets */
  39. #define CORE_CONTROL 0x000
  40. #define APP_LTSSM_ENABLE BIT(4)
  41. #define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0))
  42. #define AXI_CLK_STOP 0x004
  43. #define DBI_ACLK_STOP BIT(8)
  44. #define SLV_ACLK_STOP BIT(4)
  45. #define MSTR_ACLK_STOP BIT(0)
  46. #define DBI_CSYSREQ_REG BIT(9)
  47. #define SLV_CSYSREQ_REG BIT(5)
  48. #define MSTR_CSYSREQ_REG BIT(1)
  49. #define RESET_CONTROL_1 0x00C
  50. #define PERST_N_O_REG BIT(5)
  51. #define PERST_N_I_REG BIT(4)
  52. #define BUTTON_RST_N_REG BIT(1)
  53. #define PWUP_RST_N_REG BIT(0)
  54. #define RESET_CONTROL_2 0x010
  55. #define RESET_SELECT_1 0x014
  56. #define SQU_RST_SEL BIT(29)
  57. #define PHY_RST_SEL BIT(28)
  58. #define PWR_RST_SEL BIT(24)
  59. #define STI_RST_SEL BIT(20)
  60. #define N_STI_RST_SEL BIT(16)
  61. #define CORE_RST_SEL BIT(12)
  62. #define PERST_SEL BIT(4)
  63. #define BUTTON_RST_SEL BIT(1)
  64. #define PWUP_RST_SEL BIT(0)
  65. #define RESET_SELECT_2 0x018
  66. #define DBI_ARST_SEL BIT(8)
  67. #define SLV_ARST_SEL BIT(4)
  68. #define MSTR_ARST_SEL BIT(0)
  69. #define EM_CONTROL 0x030
  70. #define PRE_DET_STT_REG BIT(4)
  71. #define EM_SELECT 0x034
  72. #define PRE_DET_STT_SEL BIT(4)
  73. #define PM_CONTROL_2 0x050
  74. #define SYS_AUX_PWR_DET BIT(8)
  75. #define PHY_CONFIG_COM_6 0x114
  76. #define PIPE_PORT_SEL GENMASK(1, 0)
  77. #define LINK_MONITOR 0x210
  78. #define SMLH_LINK_UP BIT(0)
  79. #define LINK_CAPABILITIES_REG 0x07C
  80. #define PCIE_CAP_MAX_LINK_WIDTH GENMASK(7, 4)
  81. #define PCIE_CAP_MAX_LINK_SPEED GENMASK(3, 0)
  82. #define LINK_CONTROL_LINK_STATUS_REG 0x080
  83. #define PCIE_CAP_NEGO_LINK_WIDTH GENMASK(23, 20)
  84. #define PCIE_CAP_LINK_SPEED GENMASK(19, 16)
  85. #define TYPE1_CLASS_CODE_REV_ID_REG 0x008
  86. #define BASE_CLASS_CODE 0xFF000000
  87. #define BASE_CLASS_CODE_VALUE 0x06
  88. #define SUBCLASS_CODE 0x00FF0000
  89. #define SUBCLASS_CODE_VALUE 0x04
  90. #define PROGRAM_INTERFACE 0x0000FF00
  91. #define PROGRAM_INTERFACE_VALUE 0x00
  92. #define GEN2_CONTROL_OFF 0x80c
  93. #define DIRECT_SPEED_CHANGE BIT(17)
  94. #define MISC_CONTROL_1_OFF 0x8BC
  95. #define DBI_RO_WR_EN BIT(0)
  96. static void or_writel(void *base, u32 offs, u32 val)
  97. {
  98. writel(readl(base + offs) | val, base + offs);
  99. }
  100. static void masked_writel(void *base, u32 offs, u32 mask, u32 val)
  101. {
  102. u32 data;
  103. int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
  104. if (val && shift > 1)
  105. val <<= shift - 1;
  106. if (mask != ~0)
  107. data = (readl(base + offs) & ~mask) | val;
  108. else
  109. data = val;
  110. writel(data, base + offs);
  111. }
  112. static u32 masked_readl(void *base, u32 offs, u32 mask)
  113. {
  114. u32 data;
  115. int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
  116. data = readl(base + offs);
  117. if (mask != ~0)
  118. data &= mask;
  119. if (shift > 1)
  120. data >>= shift - 1;
  121. return data;
  122. }
  123. /*
  124. * Since SynQuacer's PCIe RC is expected to be initialized in the
  125. * firmware (including U-Boot), devicetree doesn't have control
  126. * blocks.
  127. *
  128. * Thus, this will initialize the PCIe RC with fixed addresses.
  129. */
  130. #define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
  131. #define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
  132. #define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
  133. #define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
  134. #define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
  135. #define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
  136. #define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
  137. #define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
  138. #define SIZE_16KB 0x00004000
  139. #define SIZE_64KB 0x00010000
  140. #define SIZE_1MB 0x00100000
  141. #define SYNQUACER_PCI_DBI_SIZE SIZE_16KB
  142. #define SYNQUACER_PCI_EXS_SIZE SIZE_64KB
  143. #define NUM_SQ_PCI_RC 2
  144. static const struct synquacer_pcie_base {
  145. phys_addr_t cfg_base;
  146. phys_addr_t dbi_base;
  147. phys_addr_t exs_base;
  148. } synquacer_pci_bases[NUM_SQ_PCI_RC] = {
  149. {
  150. .cfg_base = SYNQUACER_PCI_SEG0_CONFIG_BASE,
  151. .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE,
  152. .exs_base = SYNQUACER_PCI_SEG0_EXS_BASE,
  153. }, {
  154. .cfg_base = SYNQUACER_PCI_SEG1_CONFIG_BASE,
  155. .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE,
  156. .exs_base = SYNQUACER_PCI_SEG1_EXS_BASE,
  157. },
  158. };
  159. /**
  160. * struct synquacer_ecam_pcie - synquacer_ecam PCIe controller state
  161. * @cfg_base: The base address of memory mapped configuration space
  162. */
  163. struct synquacer_ecam_pcie {
  164. void *cfg_base;
  165. pci_size_t size;
  166. void *dbi_base;
  167. void *exs_base;
  168. int first_busno;
  169. struct pci_region mem;
  170. struct pci_region io;
  171. struct pci_region mem64;
  172. };
  173. DECLARE_GLOBAL_DATA_PTR;
  174. /**
  175. * pci_synquacer_ecam_conf_address() - Calculate the address of a config access
  176. * @bus: Pointer to the PCI bus
  177. * @bdf: Identifies the PCIe device to access
  178. * @offset: The offset into the device's configuration space
  179. * @paddress: Pointer to the pointer to write the calculates address to
  180. *
  181. * Calculates the address that should be accessed to perform a PCIe
  182. * configuration space access for a given device identified by the PCIe
  183. * controller device @pcie and the bus, device & function numbers in @bdf. If
  184. * access to the device is not valid then the function will return an error
  185. * code. Otherwise the address to access will be written to the pointer pointed
  186. * to by @paddress.
  187. */
  188. static int pci_synquacer_ecam_conf_address(const struct udevice *bus,
  189. pci_dev_t bdf, uint offset,
  190. void **paddress)
  191. {
  192. struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
  193. void *addr;
  194. addr = pcie->cfg_base;
  195. addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
  196. addr += PCI_DEV(bdf) << 15;
  197. addr += PCI_FUNC(bdf) << 12;
  198. addr += offset;
  199. *paddress = addr;
  200. return 0;
  201. }
  202. static bool pci_synquacer_ecam_addr_valid(const struct udevice *bus,
  203. pci_dev_t bdf)
  204. {
  205. struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
  206. int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
  207. /*
  208. * The Synopsys DesignWare PCIe controller in ECAM mode will not filter
  209. * type 0 config TLPs sent to devices 1 and up on its downstream port,
  210. * resulting in devices appearing multiple times on bus 0 unless we
  211. * filter out those accesses here.
  212. */
  213. if (PCI_BUS(bdf) == pcie->first_busno && PCI_DEV(bdf) > 0)
  214. return false;
  215. return (PCI_BUS(bdf) >= pcie->first_busno &&
  216. PCI_BUS(bdf) < pcie->first_busno + num_buses);
  217. }
  218. /**
  219. * pci_synquacer_ecam_read_config() - Read from configuration space
  220. * @bus: Pointer to the PCI bus
  221. * @bdf: Identifies the PCIe device to access
  222. * @offset: The offset into the device's configuration space
  223. * @valuep: A pointer at which to store the read value
  224. * @size: Indicates the size of access to perform
  225. *
  226. * Read a value of size @size from offset @offset within the configuration
  227. * space of the device identified by the bus, device & function numbers in @bdf
  228. * on the PCI bus @bus.
  229. */
  230. static int pci_synquacer_ecam_read_config(const struct udevice *bus,
  231. pci_dev_t bdf, uint offset,
  232. ulong *valuep, enum pci_size_t size)
  233. {
  234. if (!pci_synquacer_ecam_addr_valid(bus, bdf)) {
  235. *valuep = pci_get_ff(size);
  236. return 0;
  237. }
  238. return pci_generic_mmap_read_config(bus, pci_synquacer_ecam_conf_address,
  239. bdf, offset, valuep, size);
  240. }
  241. /**
  242. * pci_synquacer_ecam_write_config() - Write to configuration space
  243. * @bus: Pointer to the PCI bus
  244. * @bdf: Identifies the PCIe device to access
  245. * @offset: The offset into the device's configuration space
  246. * @value: The value to write
  247. * @size: Indicates the size of access to perform
  248. *
  249. * Write the value @value of size @size from offset @offset within the
  250. * configuration space of the device identified by the bus, device & function
  251. * numbers in @bdf on the PCI bus @bus.
  252. */
  253. static int pci_synquacer_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
  254. uint offset, ulong value,
  255. enum pci_size_t size)
  256. {
  257. if (!pci_synquacer_ecam_addr_valid(bus, bdf))
  258. return 0;
  259. return pci_generic_mmap_write_config(bus, pci_synquacer_ecam_conf_address,
  260. bdf, offset, value, size);
  261. }
  262. /**
  263. * pci_synquacer_ecam_of_to_plat() - Translate from DT to device state
  264. * @dev: A pointer to the device being operated on
  265. *
  266. * Translate relevant data from the device tree pertaining to device @dev into
  267. * state that the driver will later make use of. This state is stored in the
  268. * device's private data structure.
  269. *
  270. * Return: 0 on success, else -EINVAL
  271. */
  272. static int pci_synquacer_ecam_of_to_plat(struct udevice *dev)
  273. {
  274. struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
  275. struct fdt_resource reg_res;
  276. int i, err;
  277. debug("%s: called for %s\n", __func__, dev->name);
  278. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  279. 0, &reg_res);
  280. if (err < 0) {
  281. pr_err("\"reg\" resource not found\n");
  282. return err;
  283. }
  284. /* Find the correct pair of the DBI/EXS base address */
  285. for (i = 0; i < NUM_SQ_PCI_RC; i++) {
  286. if (synquacer_pci_bases[i].cfg_base == reg_res.start)
  287. break;
  288. }
  289. if (i == NUM_SQ_PCI_RC) {
  290. pr_err("Unknown ECAM base address %lx.\n",
  291. (unsigned long)reg_res.start);
  292. return -ENOENT;
  293. }
  294. pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base,
  295. SYNQUACER_PCI_DBI_SIZE, MAP_NOCACHE);
  296. if (!pcie->dbi_base) {
  297. pr_err("Failed to map DBI for %s\n", dev->name);
  298. return -ENOMEM;
  299. }
  300. pcie->exs_base = map_physmem(synquacer_pci_bases[i].exs_base,
  301. SYNQUACER_PCI_EXS_SIZE, MAP_NOCACHE);
  302. if (!pcie->exs_base) {
  303. pr_err("Failed to map EXS for %s\n", dev->name);
  304. return -ENOMEM;
  305. }
  306. pcie->size = fdt_resource_size(&reg_res);
  307. pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
  308. if (!pcie->cfg_base) {
  309. pr_err("Failed to map config space for %s\n", dev->name);
  310. return -ENOMEM;
  311. }
  312. debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base);
  313. return 0;
  314. }
  315. static void pci_synquacer_pre_init(struct synquacer_ecam_pcie *pcie)
  316. {
  317. void *base = pcie->exs_base;
  318. masked_writel(base, EM_SELECT, PRE_DET_STT_SEL, 0);
  319. masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 0);
  320. masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 1);
  321. /* 1: Assert all PHY / LINK resets */
  322. masked_writel(base, RESET_SELECT_1, PERST_SEL, 0);
  323. masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 0);
  324. masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 0);
  325. /* Device Reset(PERST#) is effective afrer Set device_type (RC) */
  326. masked_writel(base, RESET_SELECT_1, PWUP_RST_SEL, 0);
  327. masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
  328. masked_writel(base, RESET_SELECT_1, BUTTON_RST_SEL, 0);
  329. masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
  330. masked_writel(base, RESET_SELECT_1, PWR_RST_SEL, 1);
  331. masked_writel(base, RESET_SELECT_2, MSTR_ARST_SEL, 1);
  332. masked_writel(base, RESET_SELECT_2, SLV_ARST_SEL, 1);
  333. masked_writel(base, RESET_SELECT_2, DBI_ARST_SEL, 1);
  334. masked_writel(base, RESET_SELECT_1, CORE_RST_SEL, 1);
  335. masked_writel(base, RESET_SELECT_1, STI_RST_SEL, 1);
  336. masked_writel(base, RESET_SELECT_1, N_STI_RST_SEL, 1);
  337. masked_writel(base, RESET_SELECT_1, SQU_RST_SEL, 1);
  338. masked_writel(base, RESET_SELECT_1, PHY_RST_SEL, 1);
  339. /* 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup. */
  340. masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
  341. /* 3: Set device_type (RC) */
  342. masked_writel(base, CORE_CONTROL, DEVICE_TYPE, 4);
  343. }
  344. static void pci_synquacer_dbi_init(void *dbi_base)
  345. {
  346. masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
  347. /* 4 Lanes */
  348. masked_writel(dbi_base, LINK_CAPABILITIES_REG,
  349. PCIE_CAP_MAX_LINK_WIDTH, 4);
  350. /* Gen 2 */
  351. masked_writel(dbi_base, LINK_CAPABILITIES_REG,
  352. PCIE_CAP_MAX_LINK_SPEED, 2);
  353. masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
  354. BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
  355. masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
  356. SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
  357. masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
  358. PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
  359. masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
  360. }
  361. static void pcie_sq_prog_outbound_atu(void *dbi_base, int index,
  362. u64 cpu_base, u64 pci_base, u64 size,
  363. u32 type, u32 flags)
  364. {
  365. debug("%s: %p, %d, %llx, %llx, %llx, %x, %x\n", __func__,
  366. dbi_base, index, cpu_base, pci_base, size, type, flags);
  367. writel(IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX(index),
  368. dbi_base + IATU_VIEWPORT_OFF);
  369. writel((u32)(cpu_base & 0xffffffff),
  370. dbi_base + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0);
  371. writel((u32)(cpu_base >> 32),
  372. dbi_base + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0);
  373. writel((u32)(cpu_base + size - 1),
  374. dbi_base + IATU_LIMIT_ADDR_OFF_OUTBOUND_0);
  375. writel((u32)(pci_base & 0xffffffff),
  376. dbi_base + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0);
  377. writel((u32)(pci_base >> 32),
  378. dbi_base + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0);
  379. writel(type, dbi_base + IATU_REGION_CTRL_1_OFF_OUTBOUND_0);
  380. writel(IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | flags,
  381. dbi_base + IATU_REGION_CTRL_2_OFF_OUTBOUND_0);
  382. }
  383. static void pci_synquacer_post_init(struct synquacer_ecam_pcie *pcie)
  384. {
  385. void *base = pcie->exs_base;
  386. /*
  387. * 4: Set Bifurcation 1=disable 4=able
  388. * 5: Supply Reference (It has executed)
  389. * 6: Wait for 10usec (Reference Clocks is stable)
  390. * 7: De assert PERST#
  391. */
  392. masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 1);
  393. masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 1);
  394. /* 8: Assert SYS_AUX_PWR_DET */
  395. masked_writel(base, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
  396. /* 9: Supply following clocks */
  397. masked_writel(base, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
  398. masked_writel(base, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
  399. masked_writel(base, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
  400. masked_writel(base, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
  401. masked_writel(base, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
  402. masked_writel(base, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
  403. /*
  404. * 10: De assert PHY reset
  405. * 11: De assert LINK's PMC reset
  406. */
  407. masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
  408. masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
  409. /* 12: PHY auto
  410. * 13: Wrapper auto
  411. * 14-17: PHY auto
  412. * 18: Wrapper auto
  413. * 19: Update registers through DBI AXI Slave interface
  414. */
  415. pci_synquacer_dbi_init(pcie->dbi_base);
  416. or_writel(pcie->dbi_base, PCI_COMMAND,
  417. PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  418. /* Force link speed change to Gen2 at link up */
  419. or_writel(pcie->dbi_base, GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
  420. /* Region 0: MMIO32 range */
  421. pcie_sq_prog_outbound_atu(pcie->dbi_base, 0,
  422. pcie->mem.phys_start,
  423. pcie->mem.bus_start,
  424. pcie->mem.size,
  425. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
  426. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
  427. IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
  428. /* Region 1: Type 0 config space */
  429. pcie_sq_prog_outbound_atu(pcie->dbi_base, 1,
  430. (u64)pcie->cfg_base,
  431. 0,
  432. SIZE_64KB,
  433. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
  434. IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
  435. /* Region 2: Type 1 config space */
  436. pcie_sq_prog_outbound_atu(pcie->dbi_base, 2,
  437. (u64)pcie->cfg_base + SIZE_64KB,
  438. 0,
  439. (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB,
  440. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
  441. IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
  442. /* Region 3: port I/O range */
  443. pcie_sq_prog_outbound_atu(pcie->dbi_base, 3,
  444. pcie->io.phys_start,
  445. pcie->io.bus_start,
  446. pcie->io.size,
  447. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
  448. 0);
  449. /* Region 4: MMIO64 range */
  450. pcie_sq_prog_outbound_atu(pcie->dbi_base, 4,
  451. pcie->mem64.phys_start,
  452. pcie->mem64.bus_start,
  453. pcie->mem64.size,
  454. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
  455. IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
  456. IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
  457. /* enable link */
  458. if (masked_readl(base, CORE_CONTROL, APP_LTSSM_ENABLE) == 0)
  459. masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
  460. }
  461. static int pci_synquacer_ecam_probe(struct udevice *dev)
  462. {
  463. struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
  464. struct udevice *ctlr = pci_get_controller(dev);
  465. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  466. debug("Probe synquacer pcie for bus %d\n", dev_seq(dev));
  467. pcie->first_busno = dev_seq(dev);
  468. /* Store the IO and MEM windows settings for configuring ATU */
  469. pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
  470. pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
  471. pcie->io.size = hose->regions[0].size; /* IO size */
  472. pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
  473. pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
  474. pcie->mem.size = hose->regions[1].size; /* MEM size */
  475. pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */
  476. pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */
  477. pcie->mem64.size = hose->regions[2].size; /* MEM64 size */
  478. pci_synquacer_pre_init(pcie);
  479. mdelay(150);
  480. pci_synquacer_post_init(pcie);
  481. /* It takes a while to stabilize the PCIe bus for scanning */
  482. mdelay(100);
  483. return 0;
  484. }
  485. static const struct dm_pci_ops pci_synquacer_ecam_ops = {
  486. .read_config = pci_synquacer_ecam_read_config,
  487. .write_config = pci_synquacer_ecam_write_config,
  488. };
  489. static const struct udevice_id pci_synquacer_ecam_ids[] = {
  490. { .compatible = "socionext,synquacer-pcie-ecam" },
  491. { }
  492. };
  493. U_BOOT_DRIVER(pci_synquacer_ecam) = {
  494. .name = "pci_synquacer_ecam",
  495. .id = UCLASS_PCI,
  496. .of_match = pci_synquacer_ecam_ids,
  497. .ops = &pci_synquacer_ecam_ops,
  498. .probe = pci_synquacer_ecam_probe,
  499. .of_to_plat = pci_synquacer_ecam_of_to_plat,
  500. .priv_auto = sizeof(struct synquacer_ecam_pcie),
  501. };