pcie_dw_sifive.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SiFive FU740 DesignWare PCIe Controller
  4. *
  5. * Copyright (C) 2020-2021 SiFive, Inc.
  6. *
  7. * Based in early part on the i.MX6 PCIe host controller shim which is:
  8. *
  9. * Copyright (C) 2013 Kosagi
  10. * http://www.kosagi.com
  11. *
  12. * Based on driver from author: Alan Mikhak <amikhak@wirelessfabric.com>
  13. */
  14. #include <asm/io.h>
  15. #include <asm-generic/gpio.h>
  16. #include <clk.h>
  17. #include <common.h>
  18. #include <dm.h>
  19. #include <dm/device_compat.h>
  20. #include <generic-phy.h>
  21. #include <linux/bitops.h>
  22. #include <linux/log2.h>
  23. #include <pci.h>
  24. #include <pci_ep.h>
  25. #include <pci_ids.h>
  26. #include <regmap.h>
  27. #include <reset.h>
  28. #include <syscon.h>
  29. #include "pcie_dw_common.h"
  30. struct pcie_sifive {
  31. /* Must be first member of the struct */
  32. struct pcie_dw dw;
  33. /* private control regs */
  34. void __iomem *priv_base;
  35. /* reset, power, clock resources */
  36. int sys_int_pin;
  37. struct gpio_desc pwren_gpio;
  38. struct gpio_desc reset_gpio;
  39. struct clk aux_ck;
  40. struct reset_ctl reset;
  41. };
  42. enum pcie_sifive_devtype {
  43. SV_PCIE_UNKNOWN_TYPE = 0,
  44. SV_PCIE_ENDPOINT_TYPE = 1,
  45. SV_PCIE_HOST_TYPE = 3
  46. };
  47. #define ASSERTION_DELAY 100
  48. #define PCIE_PERST_ASSERT 0x0
  49. #define PCIE_PERST_DEASSERT 0x1
  50. #define PCIE_PHY_RESET 0x1
  51. #define PCIE_PHY_RESET_DEASSERT 0x0
  52. #define GPIO_LOW 0x0
  53. #define GPIO_HIGH 0x1
  54. #define PCIE_PHY_SEL 0x1
  55. #define sv_info(sv, fmt, arg...) printf(fmt, ## arg)
  56. #define sv_warn(sv, fmt, arg...) printf(fmt, ## arg)
  57. #define sv_debug(sv, fmt, arg...) debug(fmt, ## arg)
  58. #define sv_err(sv, fmt, arg...) printf(fmt, ## arg)
  59. /* Doorbell Interface */
  60. #define DBI_OFFSET 0x0
  61. #define DBI_SIZE 0x1000
  62. #define PL_OFFSET 0x700
  63. #define PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  64. #define PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  65. #define PHY_DEBUG_R1_LINK_UP (0x1 << 4)
  66. #define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
  67. #define PCIE_MISC_CONTROL_1 0x8bc
  68. #define DBI_RO_WR_EN BIT(0)
  69. /* pcie reset */
  70. #define PCIEX8MGMT_PERST_N 0x0
  71. /* LTSSM */
  72. #define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
  73. #define LTSSM_ENABLE_BIT BIT(0)
  74. /* phy reset */
  75. #define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
  76. /* device type */
  77. #define PCIEX8MGMT_DEVICE_TYPE 0x708
  78. #define DEVICE_TYPE_EP 0x0
  79. #define DEVICE_TYPE_RC 0x4
  80. /* phy control registers*/
  81. #define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
  82. #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
  83. #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
  84. #define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
  85. #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
  86. #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
  87. #define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
  88. #define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
  89. #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
  90. #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
  91. #define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
  92. #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
  93. #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
  94. #define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
  95. #define PCIEX8MGMT_LANE_NUM 8
  96. #define PCIEX8MGMT_LANE 0x1008
  97. #define PCIEX8MGMT_LANE_OFF 0x100
  98. #define PCIEX8MGMT_TERM_MODE 0x0e21
  99. #define PCIE_CAP_BASE 0x70
  100. #define PCI_CONFIG(r) (DBI_OFFSET + (r))
  101. #define PCIE_CAPABILITIES(r) PCI_CONFIG(PCIE_CAP_BASE + (r))
  102. /* Link capability */
  103. #define PF0_PCIE_CAP_LINK_CAP PCIE_CAPABILITIES(0xc)
  104. #define PCIE_LINK_CAP_MAX_SPEED_MASK 0xf
  105. #define PCIE_LINK_CAP_MAX_SPEED_GEN1 BIT(0)
  106. #define PCIE_LINK_CAP_MAX_SPEED_GEN2 BIT(1)
  107. #define PCIE_LINK_CAP_MAX_SPEED_GEN3 BIT(2)
  108. #define PCIE_LINK_CAP_MAX_SPEED_GEN4 BIT(3)
  109. static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv)
  110. {
  111. u32 val;
  112. val = readl(sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
  113. switch (val) {
  114. case DEVICE_TYPE_RC:
  115. return SV_PCIE_HOST_TYPE;
  116. case DEVICE_TYPE_EP:
  117. return SV_PCIE_ENDPOINT_TYPE;
  118. default:
  119. return SV_PCIE_UNKNOWN_TYPE;
  120. }
  121. }
  122. static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg,
  123. u32 bits, int state)
  124. {
  125. u32 val;
  126. val = readl(sv->priv_base + reg);
  127. val = state ? (val | bits) : (val & !bits);
  128. writel(val, sv->priv_base + reg);
  129. }
  130. static void pcie_sifive_assert_reset(struct pcie_sifive *sv)
  131. {
  132. dm_gpio_set_value(&sv->reset_gpio, GPIO_LOW);
  133. writel(PCIE_PERST_ASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
  134. mdelay(ASSERTION_DELAY);
  135. }
  136. static void pcie_sifive_power_on(struct pcie_sifive *sv)
  137. {
  138. dm_gpio_set_value(&sv->pwren_gpio, GPIO_HIGH);
  139. mdelay(ASSERTION_DELAY);
  140. }
  141. static void pcie_sifive_deassert_reset(struct pcie_sifive *sv)
  142. {
  143. writel(PCIE_PERST_DEASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
  144. dm_gpio_set_value(&sv->reset_gpio, GPIO_HIGH);
  145. mdelay(ASSERTION_DELAY);
  146. }
  147. static int pcie_sifive_setphy(const u8 phy, const u8 write,
  148. const u16 addr, const u16 wrdata,
  149. u16 *rddata, struct pcie_sifive *sv)
  150. {
  151. unsigned char ack = 0;
  152. if (!(phy == 0 || phy == 1))
  153. return -2;
  154. /* setup phy para */
  155. writel(addr, sv->priv_base +
  156. (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR :
  157. PCIEX8MGMT_PHY0_CR_PARA_ADDR));
  158. if (write)
  159. writel(wrdata, sv->priv_base +
  160. (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA :
  161. PCIEX8MGMT_PHY0_CR_PARA_WR_DATA));
  162. /* enable access if write */
  163. if (write)
  164. writel(1, sv->priv_base +
  165. (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
  166. PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
  167. else
  168. writel(1, sv->priv_base +
  169. (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
  170. PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
  171. /* wait for wait_idle */
  172. do {
  173. u32 val;
  174. val = readl(sv->priv_base +
  175. (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
  176. PCIEX8MGMT_PHY0_CR_PARA_ACK));
  177. if (val) {
  178. ack = 1;
  179. if (!write)
  180. readl(sv->priv_base +
  181. (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_DATA :
  182. PCIEX8MGMT_PHY0_CR_PARA_RD_DATA));
  183. mdelay(1);
  184. }
  185. } while (!ack);
  186. /* clear */
  187. if (write)
  188. writel(0, sv->priv_base +
  189. (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
  190. PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
  191. else
  192. writel(0, sv->priv_base +
  193. (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
  194. PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
  195. while (readl(sv->priv_base +
  196. (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
  197. PCIEX8MGMT_PHY0_CR_PARA_ACK))) {
  198. /* wait for ~wait_idle */
  199. }
  200. return 0;
  201. }
  202. static void pcie_sifive_init_phy(struct pcie_sifive *sv)
  203. {
  204. int lane;
  205. /* enable phy cr_para_sel interfaces */
  206. writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
  207. writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
  208. mdelay(1);
  209. /* set PHY AC termination mode */
  210. for (lane = 0; lane < PCIEX8MGMT_LANE_NUM; lane++) {
  211. pcie_sifive_setphy(0, 1,
  212. PCIEX8MGMT_LANE +
  213. (PCIEX8MGMT_LANE_OFF * lane),
  214. PCIEX8MGMT_TERM_MODE, NULL, sv);
  215. pcie_sifive_setphy(1, 1,
  216. PCIEX8MGMT_LANE +
  217. (PCIEX8MGMT_LANE_OFF * lane),
  218. PCIEX8MGMT_TERM_MODE, NULL, sv);
  219. }
  220. }
  221. static int pcie_sifive_check_link(struct pcie_sifive *sv)
  222. {
  223. u32 val;
  224. val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
  225. return (val & PHY_DEBUG_R1_LINK_UP) &&
  226. !(val & PHY_DEBUG_R1_LINK_IN_TRAINING);
  227. }
  228. static void pcie_sifive_force_gen1(struct pcie_sifive *sv)
  229. {
  230. u32 val, linkcap;
  231. /*
  232. * Force Gen1 operation when starting the link. In case the link is
  233. * started in Gen2 mode, there is a possibility the devices on the
  234. * bus will not be detected at all. This happens with PCIe switches.
  235. */
  236. /* ctrl_ro_wr_enable */
  237. val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
  238. val |= DBI_RO_WR_EN;
  239. writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
  240. /* configure link cap */
  241. linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
  242. linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK;
  243. writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
  244. /* ctrl_ro_wr_disable */
  245. val &= ~DBI_RO_WR_EN;
  246. writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
  247. }
  248. static void pcie_sifive_print_phy_debug(struct pcie_sifive *sv)
  249. {
  250. sv_err(sv, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
  251. readl(sv->dw.dbi_base + PHY_DEBUG_R0),
  252. readl(sv->dw.dbi_base + PHY_DEBUG_R1));
  253. }
  254. static int pcie_sifive_wait_for_link(struct pcie_sifive *sv)
  255. {
  256. u32 val;
  257. int timeout;
  258. /* Wait for the link to train */
  259. mdelay(20);
  260. timeout = 20;
  261. do {
  262. mdelay(1);
  263. } while (--timeout && !pcie_sifive_check_link(sv));
  264. val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
  265. if (!(val & PHY_DEBUG_R1_LINK_UP) ||
  266. (val & PHY_DEBUG_R1_LINK_IN_TRAINING)) {
  267. sv_info(sv, "Failed to negotiate PCIe link!\n");
  268. pcie_sifive_print_phy_debug(sv);
  269. writel(PCIE_PHY_RESET,
  270. sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
  271. return -ETIMEDOUT;
  272. }
  273. return 0;
  274. }
  275. static int pcie_sifive_start_link(struct pcie_sifive *sv)
  276. {
  277. if (pcie_sifive_check_link(sv))
  278. return -EALREADY;
  279. pcie_sifive_force_gen1(sv);
  280. /* set ltssm */
  281. pcie_sifive_priv_set_state(sv, PCIEX8MGMT_APP_LTSSM_ENABLE,
  282. LTSSM_ENABLE_BIT, 1);
  283. return 0;
  284. }
  285. static int pcie_sifive_init_port(struct udevice *dev,
  286. enum pcie_sifive_devtype mode)
  287. {
  288. struct pcie_sifive *sv = dev_get_priv(dev);
  289. int ret;
  290. /* Power on reset */
  291. pcie_sifive_assert_reset(sv);
  292. pcie_sifive_power_on(sv);
  293. pcie_sifive_deassert_reset(sv);
  294. /* Enable pcieauxclk */
  295. ret = clk_enable(&sv->aux_ck);
  296. if (ret)
  297. dev_err(dev, "unable to enable pcie_aux clock\n");
  298. /*
  299. * assert hold_phy_rst (hold the controller LTSSM in reset
  300. * after power_up_rst_n for register programming with cr_para)
  301. */
  302. writel(PCIE_PHY_RESET, sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
  303. /* deassert power_up_rst_n */
  304. ret = reset_deassert(&sv->reset);
  305. if (ret < 0) {
  306. dev_err(dev, "failed to deassert reset");
  307. return -EINVAL;
  308. }
  309. pcie_sifive_init_phy(sv);
  310. /* disable pcieauxclk */
  311. clk_disable(&sv->aux_ck);
  312. /* deassert hold_phy_rst */
  313. writel(PCIE_PHY_RESET_DEASSERT,
  314. sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
  315. /* enable pcieauxclk */
  316. clk_enable(&sv->aux_ck);
  317. /* Set desired mode while core is not operational */
  318. if (mode == SV_PCIE_HOST_TYPE)
  319. writel(DEVICE_TYPE_RC,
  320. sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
  321. else
  322. writel(DEVICE_TYPE_EP,
  323. sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
  324. /* Confirm desired mode from operational core */
  325. if (pcie_sifive_get_devtype(sv) != mode)
  326. return -EINVAL;
  327. pcie_dw_setup_host(&sv->dw);
  328. if (pcie_sifive_start_link(sv) == -EALREADY)
  329. sv_info(sv, "PCIe link is already up\n");
  330. else if (pcie_sifive_wait_for_link(sv) == -ETIMEDOUT)
  331. return -ETIMEDOUT;
  332. return 0;
  333. }
  334. static int pcie_sifive_probe(struct udevice *dev)
  335. {
  336. struct pcie_sifive *sv = dev_get_priv(dev);
  337. struct udevice *parent = pci_get_controller(dev);
  338. struct pci_controller *hose = dev_get_uclass_priv(parent);
  339. int err;
  340. sv->dw.first_busno = dev_seq(dev);
  341. sv->dw.dev = dev;
  342. err = pcie_sifive_init_port(dev, SV_PCIE_HOST_TYPE);
  343. if (err) {
  344. sv_info(sv, "Failed to init port.\n");
  345. return err;
  346. }
  347. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
  348. dev_seq(dev), pcie_dw_get_link_speed(&sv->dw),
  349. pcie_dw_get_link_width(&sv->dw),
  350. hose->first_busno);
  351. return pcie_dw_prog_outbound_atu_unroll(&sv->dw,
  352. PCIE_ATU_REGION_INDEX0,
  353. PCIE_ATU_TYPE_MEM,
  354. sv->dw.mem.phys_start,
  355. sv->dw.mem.bus_start,
  356. sv->dw.mem.size);
  357. }
  358. static void __iomem *get_fdt_addr(struct udevice *dev, const char *name)
  359. {
  360. fdt_addr_t addr;
  361. addr = dev_read_addr_name(dev, name);
  362. return (addr == FDT_ADDR_T_NONE) ? NULL : (void __iomem *)addr;
  363. }
  364. static int pcie_sifive_of_to_plat(struct udevice *dev)
  365. {
  366. struct pcie_sifive *sv = dev_get_priv(dev);
  367. int err;
  368. /* get designware DBI base addr */
  369. sv->dw.dbi_base = get_fdt_addr(dev, "dbi");
  370. if (!sv->dw.dbi_base)
  371. return -EINVAL;
  372. /* get private control base addr */
  373. sv->priv_base = get_fdt_addr(dev, "mgmt");
  374. if (!sv->priv_base)
  375. return -EINVAL;
  376. gpio_request_by_name(dev, "pwren-gpios", 0, &sv->pwren_gpio,
  377. GPIOD_IS_OUT);
  378. if (!dm_gpio_is_valid(&sv->pwren_gpio)) {
  379. sv_info(sv, "pwren_gpio is invalid\n");
  380. return -EINVAL;
  381. }
  382. gpio_request_by_name(dev, "reset-gpios", 0, &sv->reset_gpio,
  383. GPIOD_IS_OUT);
  384. if (!dm_gpio_is_valid(&sv->reset_gpio)) {
  385. sv_info(sv, "reset_gpio is invalid\n");
  386. return -EINVAL;
  387. }
  388. err = clk_get_by_index(dev, 0, &sv->aux_ck);
  389. if (err) {
  390. sv_info(sv, "clk_get_by_index(aux_ck) failed: %d\n", err);
  391. return err;
  392. }
  393. err = reset_get_by_index(dev, 0, &sv->reset);
  394. if (err) {
  395. sv_info(sv, "reset_get_by_index(reset) failed: %d\n", err);
  396. return err;
  397. }
  398. return 0;
  399. }
  400. static const struct dm_pci_ops pcie_sifive_ops = {
  401. .read_config = pcie_dw_read_config,
  402. .write_config = pcie_dw_write_config,
  403. };
  404. static const struct udevice_id pcie_sifive_ids[] = {
  405. { .compatible = "sifive,fu740-pcie" },
  406. {}
  407. };
  408. U_BOOT_DRIVER(pcie_sifive) = {
  409. .name = "pcie_sifive",
  410. .id = UCLASS_PCI,
  411. .of_match = pcie_sifive_ids,
  412. .ops = &pcie_sifive_ops,
  413. .of_to_plat = pcie_sifive_of_to_plat,
  414. .probe = pcie_sifive_probe,
  415. .priv_auto = sizeof(struct pcie_sifive),
  416. };