pcie_dw_mvebu.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. *
  5. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  6. *
  7. * Based on:
  8. * - drivers/pci/pcie_imx.c
  9. * - drivers/pci/pci_mvebu.c
  10. * - drivers/pci/pcie_xilinx.c
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <pci.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm-generic/gpio.h>
  19. #include <linux/delay.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* PCI Config space registers */
  22. #define PCIE_CONFIG_BAR0 0x10
  23. #define PCIE_LINK_STATUS_REG 0x80
  24. #define PCIE_LINK_STATUS_SPEED_OFF 16
  25. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  26. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  27. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  28. /* Resizable bar capability registers */
  29. #define RESIZABLE_BAR_CAP 0x250
  30. #define RESIZABLE_BAR_CTL0 0x254
  31. #define RESIZABLE_BAR_CTL1 0x258
  32. /* iATU registers */
  33. #define PCIE_ATU_VIEWPORT 0x900
  34. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  35. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  36. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  37. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  38. #define PCIE_ATU_CR1 0x904
  39. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  40. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  41. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  42. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  43. #define PCIE_ATU_CR2 0x908
  44. #define PCIE_ATU_ENABLE (0x1 << 31)
  45. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  46. #define PCIE_ATU_LOWER_BASE 0x90C
  47. #define PCIE_ATU_UPPER_BASE 0x910
  48. #define PCIE_ATU_LIMIT 0x914
  49. #define PCIE_ATU_LOWER_TARGET 0x918
  50. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  51. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  52. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  53. #define PCIE_ATU_UPPER_TARGET 0x91C
  54. #define PCIE_LINK_CAPABILITY 0x7C
  55. #define PCIE_LINK_CTL_2 0xA0
  56. #define TARGET_LINK_SPEED_MASK 0xF
  57. #define LINK_SPEED_GEN_1 0x1
  58. #define LINK_SPEED_GEN_2 0x2
  59. #define LINK_SPEED_GEN_3 0x3
  60. #define PCIE_GEN3_RELATED 0x890
  61. #define GEN3_EQU_DISABLE (1 << 16)
  62. #define GEN3_ZRXDC_NON_COMP (1 << 0)
  63. #define PCIE_GEN3_EQU_CTRL 0x8A8
  64. #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
  65. #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
  66. #define PCIE_LINK_UP_TIMEOUT_MS 100
  67. #define PCIE_GLOBAL_CONTROL 0x8000
  68. #define PCIE_APP_LTSSM_EN (1 << 2)
  69. #define PCIE_DEVICE_TYPE_OFFSET (4)
  70. #define PCIE_DEVICE_TYPE_MASK (0xF)
  71. #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
  72. #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
  73. #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
  74. #define PCIE_GLOBAL_STATUS 0x8008
  75. #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
  76. #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
  77. #define PCIE_ARCACHE_TRC 0x8050
  78. #define PCIE_AWCACHE_TRC 0x8054
  79. #define ARCACHE_SHAREABLE_CACHEABLE 0x3511
  80. #define AWCACHE_SHAREABLE_CACHEABLE 0x5311
  81. #define LINK_SPEED_GEN_1 0x1
  82. #define LINK_SPEED_GEN_2 0x2
  83. #define LINK_SPEED_GEN_3 0x3
  84. /**
  85. * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
  86. *
  87. * @ctrl_base: The base address of the register space
  88. * @cfg_base: The base address of the configuration space
  89. * @cfg_size: The size of the configuration space which is needed
  90. * as it gets written into the PCIE_ATU_LIMIT register
  91. * @first_busno: This driver supports multiple PCIe controllers.
  92. * first_busno stores the bus number of the PCIe root-port
  93. * number which may vary depending on the PCIe setup
  94. * (PEX switches etc).
  95. */
  96. struct pcie_dw_mvebu {
  97. void *ctrl_base;
  98. void *cfg_base;
  99. fdt_size_t cfg_size;
  100. int first_busno;
  101. /* IO and MEM PCI regions */
  102. int region_count;
  103. struct pci_region io;
  104. struct pci_region mem;
  105. };
  106. static int pcie_dw_get_link_speed(const void *regs_base)
  107. {
  108. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  109. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  110. }
  111. static int pcie_dw_get_link_width(const void *regs_base)
  112. {
  113. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  114. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  115. }
  116. /**
  117. * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
  118. *
  119. * @pcie: Pointer to the PCI controller state
  120. * @index: ATU region index
  121. * @type: ATU accsess type
  122. * @cpu_addr: the physical address for the translation entry
  123. * @pci_addr: the pcie bus address for the translation entry
  124. * @size: the size of the translation entry
  125. */
  126. static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
  127. int type, u64 cpu_addr, u64 pci_addr,
  128. u32 size)
  129. {
  130. writel(PCIE_ATU_REGION_OUTBOUND | index,
  131. pcie->ctrl_base + PCIE_ATU_VIEWPORT);
  132. writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
  133. writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
  134. writel(lower_32_bits(cpu_addr + size - 1),
  135. pcie->ctrl_base + PCIE_ATU_LIMIT);
  136. writel(lower_32_bits(pci_addr),
  137. pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
  138. writel(upper_32_bits(pci_addr),
  139. pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
  140. writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
  141. writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
  142. }
  143. /**
  144. * set_cfg_address() - Configure the PCIe controller config space access
  145. *
  146. * @pcie: Pointer to the PCI controller state
  147. * @d: PCI device to access
  148. * @where: Offset in the configuration space
  149. *
  150. * Configures the PCIe controller to access the configuration space of
  151. * a specific PCIe device and returns the address to use for this
  152. * access.
  153. *
  154. * Return: Address that can be used to access the configation space
  155. * of the requested device / offset
  156. */
  157. static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
  158. pci_dev_t d, uint where)
  159. {
  160. uintptr_t va_address;
  161. u32 atu_type;
  162. /*
  163. * Region #0 is used for Outbound CFG space access.
  164. * Direction = Outbound
  165. * Region Index = 0
  166. */
  167. if (PCI_BUS(d) == (pcie->first_busno + 1))
  168. /* For local bus, change TLP Type field to 4. */
  169. atu_type = PCIE_ATU_TYPE_CFG0;
  170. else
  171. /* Otherwise, change TLP Type field to 5. */
  172. atu_type = PCIE_ATU_TYPE_CFG1;
  173. if (PCI_BUS(d) == pcie->first_busno) {
  174. /* Accessing root port configuration space. */
  175. va_address = (uintptr_t)pcie->ctrl_base;
  176. } else {
  177. d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
  178. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  179. atu_type, (u64)pcie->cfg_base,
  180. d << 8, pcie->cfg_size);
  181. va_address = (uintptr_t)pcie->cfg_base;
  182. }
  183. va_address += where & ~0x3;
  184. return va_address;
  185. }
  186. /**
  187. * pcie_dw_addr_valid() - Check for valid bus address
  188. *
  189. * @d: The PCI device to access
  190. * @first_busno: Bus number of the PCIe controller root complex
  191. *
  192. * Return 1 (true) if the PCI device can be accessed by this controller.
  193. *
  194. * Return: 1 on valid, 0 on invalid
  195. */
  196. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  197. {
  198. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  199. return 0;
  200. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  201. return 0;
  202. return 1;
  203. }
  204. /**
  205. * pcie_dw_mvebu_read_config() - Read from configuration space
  206. *
  207. * @bus: Pointer to the PCI bus
  208. * @bdf: Identifies the PCIe device to access
  209. * @offset: The offset into the device's configuration space
  210. * @valuep: A pointer at which to store the read value
  211. * @size: Indicates the size of access to perform
  212. *
  213. * Read a value of size @size from offset @offset within the configuration
  214. * space of the device identified by the bus, device & function numbers in @bdf
  215. * on the PCI bus @bus.
  216. *
  217. * Return: 0 on success
  218. */
  219. static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
  220. uint offset, ulong *valuep,
  221. enum pci_size_t size)
  222. {
  223. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  224. uintptr_t va_address;
  225. ulong value;
  226. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  227. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  228. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  229. debug("- out of range\n");
  230. *valuep = pci_get_ff(size);
  231. return 0;
  232. }
  233. va_address = set_cfg_address(pcie, bdf, offset);
  234. value = readl(va_address);
  235. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  236. *valuep = pci_conv_32_to_size(value, offset, size);
  237. if (pcie->region_count > 1)
  238. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  239. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  240. pcie->io.bus_start, pcie->io.size);
  241. return 0;
  242. }
  243. /**
  244. * pcie_dw_mvebu_write_config() - Write to configuration space
  245. *
  246. * @bus: Pointer to the PCI bus
  247. * @bdf: Identifies the PCIe device to access
  248. * @offset: The offset into the device's configuration space
  249. * @value: The value to write
  250. * @size: Indicates the size of access to perform
  251. *
  252. * Write the value @value of size @size from offset @offset within the
  253. * configuration space of the device identified by the bus, device & function
  254. * numbers in @bdf on the PCI bus @bus.
  255. *
  256. * Return: 0 on success
  257. */
  258. static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
  259. uint offset, ulong value,
  260. enum pci_size_t size)
  261. {
  262. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  263. uintptr_t va_address;
  264. ulong old;
  265. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  266. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  267. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  268. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  269. debug("- out of range\n");
  270. return 0;
  271. }
  272. va_address = set_cfg_address(pcie, bdf, offset);
  273. old = readl(va_address);
  274. value = pci_conv_size_to_32(old, value, offset, size);
  275. writel(value, va_address);
  276. if (pcie->region_count > 1)
  277. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  278. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  279. pcie->io.bus_start, pcie->io.size);
  280. return 0;
  281. }
  282. /**
  283. * pcie_dw_configure() - Configure link capabilities and speed
  284. *
  285. * @regs_base: A pointer to the PCIe controller registers
  286. * @cap_speed: The capabilities and speed to configure
  287. *
  288. * Configure the link capabilities and speed in the PCIe root complex.
  289. */
  290. static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
  291. {
  292. /*
  293. * TODO (shadi@marvell.com, sr@denx.de):
  294. * Need to read the serdes speed from the dts and according to it
  295. * configure the PCIe gen
  296. */
  297. /* Set link to GEN 3 */
  298. clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
  299. TARGET_LINK_SPEED_MASK, cap_speed);
  300. clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
  301. TARGET_LINK_SPEED_MASK, cap_speed);
  302. setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
  303. }
  304. /**
  305. * is_link_up() - Return the link state
  306. *
  307. * @regs_base: A pointer to the PCIe controller registers
  308. *
  309. * Return: 1 (true) for active line and 0 (false) for no link
  310. */
  311. static int is_link_up(const void *regs_base)
  312. {
  313. u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
  314. u32 reg;
  315. reg = readl(regs_base + PCIE_GLOBAL_STATUS);
  316. if ((reg & mask) == mask)
  317. return 1;
  318. return 0;
  319. }
  320. /**
  321. * wait_link_up() - Wait for the link to come up
  322. *
  323. * @regs_base: A pointer to the PCIe controller registers
  324. *
  325. * Return: 1 (true) for active line and 0 (false) for no link (timeout)
  326. */
  327. static int wait_link_up(const void *regs_base)
  328. {
  329. unsigned long timeout;
  330. timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
  331. while (!is_link_up(regs_base)) {
  332. if (get_timer(0) > timeout)
  333. return 0;
  334. };
  335. return 1;
  336. }
  337. /**
  338. * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
  339. *
  340. * @regs_base: A pointer to the PCIe controller registers
  341. * @cap_speed: The capabilities and speed to configure
  342. *
  343. * Configure the PCIe controller root complex depending on the
  344. * requested link capabilities and speed.
  345. *
  346. * Return: 1 (true) for active line and 0 (false) for no link
  347. */
  348. static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
  349. {
  350. if (!is_link_up(regs_base)) {
  351. /* Disable LTSSM state machine to enable configuration */
  352. clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  353. PCIE_APP_LTSSM_EN);
  354. }
  355. clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  356. PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
  357. PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
  358. /* Set the PCIe master AXI attributes */
  359. writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
  360. writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
  361. /* DW pre link configurations */
  362. pcie_dw_configure(regs_base, cap_speed);
  363. if (!is_link_up(regs_base)) {
  364. /* Configuration done. Start LTSSM */
  365. setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  366. PCIE_APP_LTSSM_EN);
  367. }
  368. /* Check that link was established */
  369. if (!wait_link_up(regs_base))
  370. return 0;
  371. /*
  372. * Link can be established in Gen 1. still need to wait
  373. * till MAC nagaotiation is completed
  374. */
  375. udelay(100);
  376. return 1;
  377. }
  378. /**
  379. * pcie_dw_set_host_bars() - Configure the host BARs
  380. *
  381. * @regs_base: A pointer to the PCIe controller registers
  382. *
  383. * Configure the host BARs of the PCIe controller root port so that
  384. * PCI(e) devices may access the system memory.
  385. */
  386. static void pcie_dw_set_host_bars(const void *regs_base)
  387. {
  388. u32 size = gd->ram_size;
  389. u64 max_size;
  390. u32 reg;
  391. u32 bar0;
  392. /* Verify the maximal BAR size */
  393. reg = readl(regs_base + RESIZABLE_BAR_CAP);
  394. max_size = 1ULL << (5 + (reg + (1 << 4)));
  395. if (size > max_size) {
  396. size = max_size;
  397. printf("Warning: PCIe BARs can't map all DRAM space\n");
  398. }
  399. /* Set the BAR base and size towards DDR */
  400. bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
  401. bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
  402. writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
  403. reg = ((size >> 20) - 1) << 12;
  404. writel(size, regs_base + RESIZABLE_BAR_CTL0);
  405. }
  406. /**
  407. * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
  408. *
  409. * @dev: A pointer to the device being operated on
  410. *
  411. * Probe for an active link on the PCIe bus and configure the controller
  412. * to enable this port.
  413. *
  414. * Return: 0 on success, else -ENODEV
  415. */
  416. static int pcie_dw_mvebu_probe(struct udevice *dev)
  417. {
  418. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  419. struct udevice *ctlr = pci_get_controller(dev);
  420. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  421. #if CONFIG_IS_ENABLED(DM_GPIO)
  422. struct gpio_desc reset_gpio;
  423. gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
  424. GPIOD_IS_OUT);
  425. /*
  426. * Issue reset to add-in card trough the dedicated GPIO.
  427. * Some boards are connecting the card reset pin to common system
  428. * reset wire and others are using separate GPIO port.
  429. * In the last case we have to release a reset of the addon card
  430. * using this GPIO.
  431. */
  432. if (dm_gpio_is_valid(&reset_gpio)) {
  433. dm_gpio_set_value(&reset_gpio, 1); /* assert */
  434. mdelay(200);
  435. dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
  436. mdelay(200);
  437. }
  438. #else
  439. debug("PCIE Reset on GPIO support is missing\n");
  440. #endif /* DM_GPIO */
  441. pcie->first_busno = dev_seq(dev);
  442. /* Don't register host if link is down */
  443. if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
  444. printf("PCIE-%d: Link down\n", dev_seq(dev));
  445. } else {
  446. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
  447. pcie_dw_get_link_speed(pcie->ctrl_base),
  448. pcie_dw_get_link_width(pcie->ctrl_base),
  449. hose->first_busno);
  450. }
  451. pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS;
  452. /* Store the IO and MEM windows settings for future use by the ATU */
  453. if (pcie->region_count > 1) {
  454. /* IO base */
  455. pcie->io.phys_start = hose->regions[0].phys_start;
  456. /* IO_bus_addr */
  457. pcie->io.bus_start = hose->regions[0].bus_start;
  458. /* IO size */
  459. pcie->io.size = hose->regions[0].size;
  460. }
  461. /* MEM base */
  462. pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start;
  463. /* MEM_bus_addr */
  464. pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start;
  465. /* MEM size */
  466. pcie->mem.size = hose->regions[pcie->region_count - 1].size;
  467. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
  468. PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
  469. pcie->mem.bus_start, pcie->mem.size);
  470. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  471. clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
  472. 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
  473. pcie_dw_set_host_bars(pcie->ctrl_base);
  474. return 0;
  475. }
  476. /**
  477. * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
  478. *
  479. * @dev: A pointer to the device being operated on
  480. *
  481. * Translate relevant data from the device tree pertaining to device @dev into
  482. * state that the driver will later make use of. This state is stored in the
  483. * device's private data structure.
  484. *
  485. * Return: 0 on success, else -EINVAL
  486. */
  487. static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
  488. {
  489. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  490. /* Get the controller base address */
  491. pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
  492. if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
  493. return -EINVAL;
  494. /* Get the config space base address and size */
  495. pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
  496. &pcie->cfg_size);
  497. if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
  498. return -EINVAL;
  499. return 0;
  500. }
  501. static const struct dm_pci_ops pcie_dw_mvebu_ops = {
  502. .read_config = pcie_dw_mvebu_read_config,
  503. .write_config = pcie_dw_mvebu_write_config,
  504. };
  505. static const struct udevice_id pcie_dw_mvebu_ids[] = {
  506. { .compatible = "marvell,armada8k-pcie" },
  507. { }
  508. };
  509. U_BOOT_DRIVER(pcie_dw_mvebu) = {
  510. .name = "pcie_dw_mvebu",
  511. .id = UCLASS_PCI,
  512. .of_match = pcie_dw_mvebu_ids,
  513. .ops = &pcie_dw_mvebu_ops,
  514. .of_to_plat = pcie_dw_mvebu_of_to_plat,
  515. .probe = pcie_dw_mvebu_probe,
  516. .priv_auto = sizeof(struct pcie_dw_mvebu),
  517. };