pcie_brcmstb.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Broadcom STB PCIe controller driver
  4. *
  5. * Copyright (C) 2020 Samsung Electronics Co., Ltd.
  6. *
  7. * Based on upstream Linux kernel driver:
  8. * drivers/pci/controller/pcie-brcmstb.c
  9. * Copyright (C) 2009 - 2017 Broadcom
  10. *
  11. * Based driver by Nicolas Saenz Julienne
  12. * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  13. */
  14. #include <common.h>
  15. #include <errno.h>
  16. #include <dm.h>
  17. #include <dm/ofnode.h>
  18. #include <pci.h>
  19. #include <asm/io.h>
  20. #include <linux/bitfield.h>
  21. #include <linux/log2.h>
  22. #include <linux/iopoll.h>
  23. /* Offset of the mandatory PCIe capability config registers */
  24. #define BRCM_PCIE_CAP_REGS 0x00ac
  25. /* The PCIe controller register offsets */
  26. #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
  27. #define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
  28. #define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
  29. #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
  30. #define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
  31. #define PCIE_RC_DL_MDIO_ADDR 0x1100
  32. #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
  33. #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
  34. #define PCIE_MISC_MISC_CTRL 0x4008
  35. #define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
  36. #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
  37. #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
  38. #define MISC_CTRL_MAX_BURST_SIZE_128 0x0
  39. #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
  40. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
  41. #define PCIE_MEM_WIN0_LO(win) \
  42. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
  43. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
  44. #define PCIE_MEM_WIN0_HI(win) \
  45. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
  46. #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
  47. #define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
  48. #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
  49. #define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
  50. #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
  51. #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
  52. #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
  53. #define PCIE_MISC_PCIE_STATUS 0x4068
  54. #define STATUS_PCIE_PORT_MASK 0x80
  55. #define STATUS_PCIE_PORT_SHIFT 7
  56. #define STATUS_PCIE_DL_ACTIVE_MASK 0x20
  57. #define STATUS_PCIE_DL_ACTIVE_SHIFT 5
  58. #define STATUS_PCIE_PHYLINKUP_MASK 0x10
  59. #define STATUS_PCIE_PHYLINKUP_SHIFT 4
  60. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
  61. #define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
  62. #define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
  63. #define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
  64. #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
  65. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
  66. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
  67. #define MEM_WIN0_BASE_HI_BASE_MASK 0xff
  68. #define PCIE_MEM_WIN0_BASE_HI(win) \
  69. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
  70. #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
  71. #define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
  72. #define PCIE_MEM_WIN0_LIMIT_HI(win) \
  73. PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
  74. #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
  75. #define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
  76. #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
  77. #define PCIE_MSI_INTR2_CLR 0x4508
  78. #define PCIE_MSI_INTR2_MASK_SET 0x4510
  79. #define PCIE_EXT_CFG_DATA 0x8000
  80. #define PCIE_EXT_CFG_INDEX 0x9000
  81. #define PCIE_EXT_BUSNUM_SHIFT 20
  82. #define PCIE_EXT_SLOT_SHIFT 15
  83. #define PCIE_EXT_FUNC_SHIFT 12
  84. #define PCIE_RGR1_SW_INIT_1 0x9210
  85. #define RGR1_SW_INIT_1_PERST_MASK 0x1
  86. #define RGR1_SW_INIT_1_INIT_MASK 0x2
  87. /* PCIe parameters */
  88. #define BRCM_NUM_PCIE_OUT_WINS 4
  89. /* MDIO registers */
  90. #define MDIO_PORT0 0x0
  91. #define MDIO_DATA_MASK 0x7fffffff
  92. #define MDIO_DATA_SHIFT 0
  93. #define MDIO_PORT_MASK 0xf0000
  94. #define MDIO_PORT_SHIFT 16
  95. #define MDIO_REGAD_MASK 0xffff
  96. #define MDIO_REGAD_SHIFT 0
  97. #define MDIO_CMD_MASK 0xfff00000
  98. #define MDIO_CMD_SHIFT 20
  99. #define MDIO_CMD_READ 0x1
  100. #define MDIO_CMD_WRITE 0x0
  101. #define MDIO_DATA_DONE_MASK 0x80000000
  102. #define SSC_REGS_ADDR 0x1100
  103. #define SET_ADDR_OFFSET 0x1f
  104. #define SSC_CNTL_OFFSET 0x2
  105. #define SSC_CNTL_OVRD_EN_MASK 0x8000
  106. #define SSC_CNTL_OVRD_VAL_MASK 0x4000
  107. #define SSC_STATUS_OFFSET 0x1
  108. #define SSC_STATUS_SSC_MASK 0x400
  109. #define SSC_STATUS_SSC_SHIFT 10
  110. #define SSC_STATUS_PLL_LOCK_MASK 0x800
  111. #define SSC_STATUS_PLL_LOCK_SHIFT 11
  112. /**
  113. * struct brcm_pcie - the PCIe controller state
  114. * @base: Base address of memory mapped IO registers of the controller
  115. * @gen: Non-zero value indicates limitation of the PCIe controller operation
  116. * to a specific generation (1, 2 or 3)
  117. * @ssc: true indicates active Spread Spectrum Clocking operation
  118. */
  119. struct brcm_pcie {
  120. void __iomem *base;
  121. int gen;
  122. bool ssc;
  123. };
  124. /**
  125. * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
  126. * @size: The inbound region size
  127. *
  128. * This function converts size of the inbound "BAR" region to the non-linear
  129. * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
  130. *
  131. * Return: The encoded inbound region size
  132. */
  133. static int brcm_pcie_encode_ibar_size(u64 size)
  134. {
  135. int log2_in = ilog2(size);
  136. if (log2_in >= 12 && log2_in <= 15)
  137. /* Covers 4KB to 32KB (inclusive) */
  138. return (log2_in - 12) + 0x1c;
  139. else if (log2_in >= 16 && log2_in <= 37)
  140. /* Covers 64KB to 32GB, (inclusive) */
  141. return log2_in - 15;
  142. /* Something is awry so disable */
  143. return 0;
  144. }
  145. /**
  146. * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
  147. * @pcie: Pointer to the PCIe controller state
  148. *
  149. * The controller is capable of serving in both RC and EP roles.
  150. *
  151. * Return: true for RC mode, false for EP mode.
  152. */
  153. static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
  154. {
  155. u32 val;
  156. val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
  157. return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
  158. }
  159. /**
  160. * brcm_pcie_link_up() - Check whether the PCIe link is up
  161. * @pcie: Pointer to the PCIe controller state
  162. *
  163. * Return: true if the link is up, false otherwise.
  164. */
  165. static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
  166. {
  167. u32 val, dla, plu;
  168. val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
  169. dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
  170. plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
  171. return dla && plu;
  172. }
  173. static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
  174. uint offset, void **paddress)
  175. {
  176. struct brcm_pcie *pcie = dev_get_priv(dev);
  177. unsigned int pci_bus = PCI_BUS(bdf);
  178. unsigned int pci_dev = PCI_DEV(bdf);
  179. unsigned int pci_func = PCI_FUNC(bdf);
  180. int idx;
  181. /*
  182. * Busses 0 (host PCIe bridge) and 1 (its immediate child)
  183. * are limited to a single device each
  184. */
  185. if (pci_bus < 2 && pci_dev > 0)
  186. return -EINVAL;
  187. /* Accesses to the RC go right to the RC registers */
  188. if (pci_bus == 0) {
  189. *paddress = pcie->base + offset;
  190. return 0;
  191. }
  192. /* For devices, write to the config space index register */
  193. idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
  194. | (pci_dev << PCIE_EXT_SLOT_SHIFT)
  195. | (pci_func << PCIE_EXT_FUNC_SHIFT);
  196. writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
  197. *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
  198. return 0;
  199. }
  200. static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  201. uint offset, ulong *valuep,
  202. enum pci_size_t size)
  203. {
  204. return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
  205. bdf, offset, valuep, size);
  206. }
  207. static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  208. uint offset, ulong value,
  209. enum pci_size_t size)
  210. {
  211. return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
  212. bdf, offset, value, size);
  213. }
  214. static const char *link_speed_to_str(unsigned int cls)
  215. {
  216. switch (cls) {
  217. case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
  218. case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
  219. case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
  220. default:
  221. break;
  222. }
  223. return "??";
  224. }
  225. static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
  226. unsigned int cmd)
  227. {
  228. u32 pkt;
  229. pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
  230. pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
  231. pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
  232. return pkt;
  233. }
  234. /**
  235. * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
  236. * @base: Pointer to the PCIe controller IO registers
  237. * @port: The MDIO port number
  238. * @regad: The register address
  239. * @val: A pointer at which to store the read value
  240. *
  241. * Return: 0 on success and register value in @val, negative error value
  242. * on failure.
  243. */
  244. static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
  245. unsigned int regad, u32 *val)
  246. {
  247. u32 data, addr;
  248. int ret;
  249. addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
  250. writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
  251. readl(base + PCIE_RC_DL_MDIO_ADDR);
  252. ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
  253. (data & MDIO_DATA_DONE_MASK), 100);
  254. *val = data & MDIO_DATA_MASK;
  255. return ret;
  256. }
  257. /**
  258. * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
  259. * @base: Pointer to the PCIe controller IO registers
  260. * @port: The MDIO port number
  261. * @regad: Address of the register
  262. * @wrdata: The value to write
  263. *
  264. * Return: 0 on success, negative error value on failure.
  265. */
  266. static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
  267. unsigned int regad, u16 wrdata)
  268. {
  269. u32 data, addr;
  270. addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
  271. writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
  272. readl(base + PCIE_RC_DL_MDIO_ADDR);
  273. writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
  274. return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
  275. !(data & MDIO_DATA_DONE_MASK), 100);
  276. }
  277. /**
  278. * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
  279. * @base: pointer to the PCIe controller IO registers
  280. *
  281. * Return: 0 on success, negative error value on failure.
  282. */
  283. static int brcm_pcie_set_ssc(void __iomem *base)
  284. {
  285. int pll, ssc;
  286. int ret;
  287. u32 tmp;
  288. ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
  289. SSC_REGS_ADDR);
  290. if (ret < 0)
  291. return ret;
  292. ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
  293. if (ret < 0)
  294. return ret;
  295. tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
  296. ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
  297. if (ret < 0)
  298. return ret;
  299. udelay(1000);
  300. ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
  301. if (ret < 0)
  302. return ret;
  303. ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
  304. pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
  305. return ssc && pll ? 0 : -EIO;
  306. }
  307. /**
  308. * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
  309. * @pcie: pointer to the PCIe controller state
  310. * @gen: PCIe generation to limit the controller's operation to
  311. */
  312. static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
  313. {
  314. void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
  315. u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
  316. u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
  317. lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
  318. writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
  319. lnkctl2 = (lnkctl2 & ~0xf) | gen;
  320. writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
  321. }
  322. static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
  323. unsigned int win, u64 phys_addr,
  324. u64 pcie_addr, u64 size)
  325. {
  326. void __iomem *base = pcie->base;
  327. u32 phys_addr_mb_high, limit_addr_mb_high;
  328. phys_addr_t phys_addr_mb, limit_addr_mb;
  329. int high_addr_shift;
  330. u32 tmp;
  331. /* Set the base of the pcie_addr window */
  332. writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
  333. writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
  334. /* Write the addr base & limit lower bits (in MBs) */
  335. phys_addr_mb = phys_addr / SZ_1M;
  336. limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
  337. tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
  338. u32p_replace_bits(&tmp, phys_addr_mb,
  339. MEM_WIN0_BASE_LIMIT_BASE_MASK);
  340. u32p_replace_bits(&tmp, limit_addr_mb,
  341. MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
  342. writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
  343. /* Write the cpu & limit addr upper bits */
  344. high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
  345. phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
  346. tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
  347. u32p_replace_bits(&tmp, phys_addr_mb_high,
  348. MEM_WIN0_BASE_HI_BASE_MASK);
  349. writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
  350. limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
  351. tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
  352. u32p_replace_bits(&tmp, limit_addr_mb_high,
  353. PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
  354. writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
  355. }
  356. static int brcm_pcie_probe(struct udevice *dev)
  357. {
  358. struct udevice *ctlr = pci_get_controller(dev);
  359. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  360. struct brcm_pcie *pcie = dev_get_priv(dev);
  361. void __iomem *base = pcie->base;
  362. struct pci_region region;
  363. bool ssc_good = false;
  364. int num_out_wins = 0;
  365. u64 rc_bar2_offset, rc_bar2_size;
  366. unsigned int scb_size_val;
  367. int i, ret;
  368. u16 nlw, cls, lnksta;
  369. u32 tmp;
  370. /*
  371. * Reset the bridge, assert the fundamental reset. Note for some SoCs,
  372. * e.g. BCM7278, the fundamental reset should not be asserted here.
  373. * This will need to be changed when support for other SoCs is added.
  374. */
  375. setbits_le32(base + PCIE_RGR1_SW_INIT_1,
  376. RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
  377. /*
  378. * The delay is a safety precaution to preclude the reset signal
  379. * from looking like a glitch.
  380. */
  381. udelay(100);
  382. /* Take the bridge out of reset */
  383. clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
  384. clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
  385. PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
  386. /* Wait for SerDes to be stable */
  387. udelay(100);
  388. /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
  389. clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
  390. MISC_CTRL_MAX_BURST_SIZE_MASK,
  391. MISC_CTRL_SCB_ACCESS_EN_MASK |
  392. MISC_CTRL_CFG_READ_UR_MODE_MASK |
  393. MISC_CTRL_MAX_BURST_SIZE_128);
  394. pci_get_dma_regions(dev, &region, 0);
  395. rc_bar2_offset = region.bus_start - region.phys_start;
  396. rc_bar2_size = 1ULL << fls64(region.size - 1);
  397. tmp = lower_32_bits(rc_bar2_offset);
  398. u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
  399. RC_BAR2_CONFIG_LO_SIZE_MASK);
  400. writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
  401. writel(upper_32_bits(rc_bar2_offset),
  402. base + PCIE_MISC_RC_BAR2_CONFIG_HI);
  403. scb_size_val = rc_bar2_size ?
  404. ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
  405. tmp = readl(base + PCIE_MISC_MISC_CTRL);
  406. u32p_replace_bits(&tmp, scb_size_val,
  407. MISC_CTRL_SCB0_SIZE_MASK);
  408. writel(tmp, base + PCIE_MISC_MISC_CTRL);
  409. /* Disable the PCIe->GISB memory window (RC_BAR1) */
  410. clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
  411. RC_BAR1_CONFIG_LO_SIZE_MASK);
  412. /* Disable the PCIe->SCB memory window (RC_BAR3) */
  413. clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
  414. RC_BAR3_CONFIG_LO_SIZE_MASK);
  415. /* Mask all interrupts since we are not handling any yet */
  416. writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
  417. /* Clear any interrupts we find on boot */
  418. writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
  419. if (pcie->gen)
  420. brcm_pcie_set_gen(pcie, pcie->gen);
  421. /* Unassert the fundamental reset */
  422. clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
  423. RGR1_SW_INIT_1_PERST_MASK);
  424. /* Give the RC/EP time to wake up, before trying to configure RC.
  425. * Intermittently check status for link-up, up to a total of 100ms.
  426. */
  427. for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
  428. mdelay(5);
  429. if (!brcm_pcie_link_up(pcie)) {
  430. printf("PCIe BRCM: link down\n");
  431. return -EINVAL;
  432. }
  433. if (!brcm_pcie_rc_mode(pcie)) {
  434. printf("PCIe misconfigured; is in EP mode\n");
  435. return -EINVAL;
  436. }
  437. for (i = 0; i < hose->region_count; i++) {
  438. struct pci_region *reg = &hose->regions[i];
  439. if (reg->flags != PCI_REGION_MEM)
  440. continue;
  441. if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
  442. return -EINVAL;
  443. brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
  444. reg->bus_start, reg->size);
  445. num_out_wins++;
  446. }
  447. /*
  448. * For config space accesses on the RC, show the right class for
  449. * a PCIe-PCIe bridge (the default setting is to be EP mode).
  450. */
  451. clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
  452. CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
  453. if (pcie->ssc) {
  454. ret = brcm_pcie_set_ssc(pcie->base);
  455. if (!ret)
  456. ssc_good = true;
  457. else
  458. printf("PCIe BRCM: failed attempt to enter SSC mode\n");
  459. }
  460. lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
  461. cls = lnksta & PCI_EXP_LNKSTA_CLS;
  462. nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
  463. printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
  464. nlw, ssc_good ? "(SSC)" : "(!SSC)");
  465. /* PCIe->SCB endian mode for BAR */
  466. clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
  467. VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
  468. VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
  469. /*
  470. * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
  471. * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
  472. */
  473. setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
  474. PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
  475. return 0;
  476. }
  477. static int brcm_pcie_remove(struct udevice *dev)
  478. {
  479. struct brcm_pcie *pcie = dev_get_priv(dev);
  480. void __iomem *base = pcie->base;
  481. /* Assert fundamental reset */
  482. setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
  483. /* Turn off SerDes */
  484. setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
  485. PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
  486. /* Shutdown bridge */
  487. setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
  488. return 0;
  489. }
  490. static int brcm_pcie_of_to_plat(struct udevice *dev)
  491. {
  492. struct brcm_pcie *pcie = dev_get_priv(dev);
  493. ofnode dn = dev_ofnode(dev);
  494. u32 max_link_speed;
  495. int ret;
  496. /* Get the controller base address */
  497. pcie->base = dev_read_addr_ptr(dev);
  498. if (!pcie->base)
  499. return -EINVAL;
  500. pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
  501. ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
  502. if (ret < 0 || max_link_speed > 4)
  503. pcie->gen = 0;
  504. else
  505. pcie->gen = max_link_speed;
  506. return 0;
  507. }
  508. static const struct dm_pci_ops brcm_pcie_ops = {
  509. .read_config = brcm_pcie_read_config,
  510. .write_config = brcm_pcie_write_config,
  511. };
  512. static const struct udevice_id brcm_pcie_ids[] = {
  513. { .compatible = "brcm,bcm2711-pcie" },
  514. { }
  515. };
  516. U_BOOT_DRIVER(pcie_brcm_base) = {
  517. .name = "pcie_brcm",
  518. .id = UCLASS_PCI,
  519. .ops = &brcm_pcie_ops,
  520. .of_match = brcm_pcie_ids,
  521. .probe = brcm_pcie_probe,
  522. .remove = brcm_pcie_remove,
  523. .of_to_plat = brcm_pcie_of_to_plat,
  524. .priv_auto = sizeof(struct brcm_pcie),
  525. .flags = DM_FLAG_OS_PREPARE,
  526. };