pci_mvebu.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe driver for Marvell MVEBU SoCs
  4. *
  5. * Based on Barebox drivers/pci/pci-mvebu.c
  6. *
  7. * Ported to U-Boot by:
  8. * Anton Schubert <anton.schubert@gmx.de>
  9. * Stefan Roese <sr@denx.de>
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <asm/global_data.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/lists.h>
  18. #include <dm/of_access.h>
  19. #include <pci.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/cpu.h>
  22. #include <asm/arch/soc.h>
  23. #include <linux/bitops.h>
  24. #include <linux/errno.h>
  25. #include <linux/ioport.h>
  26. #include <linux/mbus.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /* PCIe unit register offsets */
  29. #define SELECT(x, n) ((x >> n) & 1UL)
  30. #define PCIE_DEV_ID_OFF 0x0000
  31. #define PCIE_CMD_OFF 0x0004
  32. #define PCIE_DEV_REV_OFF 0x0008
  33. #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
  34. #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
  35. #define PCIE_CAPAB_OFF 0x0060
  36. #define PCIE_CTRL_STAT_OFF 0x0068
  37. #define PCIE_HEADER_LOG_4_OFF 0x0128
  38. #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
  39. #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
  40. #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
  41. #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  42. #define PCIE_WIN5_CTRL_OFF 0x1880
  43. #define PCIE_WIN5_BASE_OFF 0x1884
  44. #define PCIE_WIN5_REMAP_OFF 0x188c
  45. #define PCIE_CONF_ADDR_OFF 0x18f8
  46. #define PCIE_CONF_ADDR_EN BIT(31)
  47. #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  48. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
  49. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
  50. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
  51. #define PCIE_CONF_ADDR(dev, reg) \
  52. (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
  53. PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
  54. PCIE_CONF_ADDR_EN)
  55. #define PCIE_CONF_DATA_OFF 0x18fc
  56. #define PCIE_MASK_OFF 0x1910
  57. #define PCIE_MASK_ENABLE_INTS (0xf << 24)
  58. #define PCIE_CTRL_OFF 0x1a00
  59. #define PCIE_CTRL_X1_MODE BIT(0)
  60. #define PCIE_STAT_OFF 0x1a04
  61. #define PCIE_STAT_BUS (0xff << 8)
  62. #define PCIE_STAT_DEV (0x1f << 16)
  63. #define PCIE_STAT_LINK_DOWN BIT(0)
  64. #define PCIE_DEBUG_CTRL 0x1a60
  65. #define PCIE_DEBUG_SOFT_RESET BIT(20)
  66. struct mvebu_pcie {
  67. struct pci_controller hose;
  68. void __iomem *base;
  69. void __iomem *membase;
  70. struct resource mem;
  71. void __iomem *iobase;
  72. struct resource io;
  73. u32 port;
  74. u32 lane;
  75. int devfn;
  76. u32 lane_mask;
  77. int first_busno;
  78. int local_dev;
  79. char name[16];
  80. unsigned int mem_target;
  81. unsigned int mem_attr;
  82. unsigned int io_target;
  83. unsigned int io_attr;
  84. };
  85. /*
  86. * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
  87. * into SoCs address space. Each controller will map 128M of MEM
  88. * and 64K of I/O space when registered.
  89. */
  90. static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
  91. #define PCIE_MEM_SIZE (128 << 20)
  92. static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
  93. static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
  94. {
  95. u32 val;
  96. val = readl(pcie->base + PCIE_STAT_OFF);
  97. return !(val & PCIE_STAT_LINK_DOWN);
  98. }
  99. static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
  100. {
  101. u32 stat;
  102. stat = readl(pcie->base + PCIE_STAT_OFF);
  103. stat &= ~PCIE_STAT_BUS;
  104. stat |= busno << 8;
  105. writel(stat, pcie->base + PCIE_STAT_OFF);
  106. }
  107. static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
  108. {
  109. u32 stat;
  110. stat = readl(pcie->base + PCIE_STAT_OFF);
  111. stat &= ~PCIE_STAT_DEV;
  112. stat |= devno << 16;
  113. writel(stat, pcie->base + PCIE_STAT_OFF);
  114. }
  115. static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
  116. {
  117. u32 stat;
  118. stat = readl(pcie->base + PCIE_STAT_OFF);
  119. return (stat & PCIE_STAT_BUS) >> 8;
  120. }
  121. static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
  122. {
  123. u32 stat;
  124. stat = readl(pcie->base + PCIE_STAT_OFF);
  125. return (stat & PCIE_STAT_DEV) >> 16;
  126. }
  127. static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
  128. {
  129. return container_of(hose, struct mvebu_pcie, hose);
  130. }
  131. static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
  132. {
  133. /*
  134. * There are two devices visible on local bus:
  135. * * on slot configured by function mvebu_pcie_set_local_dev_nr()
  136. * (by default this register is set to 0) there is a
  137. * "Marvell Memory controller", which isn't useful in root complex
  138. * mode,
  139. * * on all other slots the real PCIe card connected to the PCIe slot.
  140. *
  141. * We therefore allow access only to the real PCIe card.
  142. */
  143. if (PCI_BUS(bdf) == pcie->first_busno &&
  144. PCI_DEV(bdf) != !pcie->local_dev)
  145. return 0;
  146. return 1;
  147. }
  148. static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  149. uint offset, ulong *valuep,
  150. enum pci_size_t size)
  151. {
  152. struct mvebu_pcie *pcie = dev_get_plat(bus);
  153. u32 data;
  154. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  155. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  156. if (!mvebu_pcie_valid_addr(pcie, bdf)) {
  157. debug("- out of range\n");
  158. *valuep = pci_get_ff(size);
  159. return 0;
  160. }
  161. /* write address */
  162. writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
  163. /* read data */
  164. data = readl(pcie->base + PCIE_CONF_DATA_OFF);
  165. debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
  166. *valuep = pci_conv_32_to_size(data, offset, size);
  167. return 0;
  168. }
  169. static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  170. uint offset, ulong value,
  171. enum pci_size_t size)
  172. {
  173. struct mvebu_pcie *pcie = dev_get_plat(bus);
  174. u32 data;
  175. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  176. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  177. debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
  178. if (!mvebu_pcie_valid_addr(pcie, bdf)) {
  179. debug("- out of range\n");
  180. return 0;
  181. }
  182. /* write address */
  183. writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
  184. /* write data */
  185. data = pci_conv_size_to_32(0, value, offset, size);
  186. writel(data, pcie->base + PCIE_CONF_DATA_OFF);
  187. return 0;
  188. }
  189. /*
  190. * Setup PCIE BARs and Address Decode Wins:
  191. * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  192. * WIN[0-3] -> DRAM bank[0-3]
  193. */
  194. static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
  195. {
  196. const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
  197. u32 size;
  198. int i;
  199. /* First, disable and clear BARs and windows. */
  200. for (i = 1; i < 3; i++) {
  201. writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
  202. writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
  203. writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
  204. }
  205. for (i = 0; i < 5; i++) {
  206. writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
  207. writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
  208. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  209. }
  210. writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
  211. writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
  212. writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
  213. /* Setup windows for DDR banks. Count total DDR size on the fly. */
  214. size = 0;
  215. for (i = 0; i < dram->num_cs; i++) {
  216. const struct mbus_dram_window *cs = dram->cs + i;
  217. writel(cs->base & 0xffff0000,
  218. pcie->base + PCIE_WIN04_BASE_OFF(i));
  219. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  220. writel(((cs->size - 1) & 0xffff0000) |
  221. (cs->mbus_attr << 8) |
  222. (dram->mbus_dram_target_id << 4) | 1,
  223. pcie->base + PCIE_WIN04_CTRL_OFF(i));
  224. size += cs->size;
  225. }
  226. /* Round up 'size' to the nearest power of two. */
  227. if ((size & (size - 1)) != 0)
  228. size = 1 << fls(size);
  229. /* Setup BAR[1] to all DRAM banks. */
  230. writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
  231. writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
  232. writel(((size - 1) & 0xffff0000) | 0x1,
  233. pcie->base + PCIE_BAR_CTRL_OFF(1));
  234. }
  235. static int mvebu_pcie_probe(struct udevice *dev)
  236. {
  237. struct mvebu_pcie *pcie = dev_get_plat(dev);
  238. struct udevice *ctlr = pci_get_controller(dev);
  239. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  240. int bus = dev_seq(dev);
  241. u32 reg;
  242. debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
  243. pcie->port, pcie->lane, (u32)pcie->base);
  244. /* Read Id info and local bus/dev */
  245. debug("direct conf read %08x, local bus %d, local dev %d\n",
  246. readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
  247. mvebu_pcie_get_local_dev_nr(pcie));
  248. pcie->first_busno = bus;
  249. pcie->local_dev = 1;
  250. mvebu_pcie_set_local_bus_nr(pcie, bus);
  251. mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
  252. pcie->mem.start = (u32)mvebu_pcie_membase;
  253. pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
  254. mvebu_pcie_membase += PCIE_MEM_SIZE;
  255. if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
  256. (phys_addr_t)pcie->mem.start,
  257. PCIE_MEM_SIZE)) {
  258. printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
  259. (u32)pcie->mem.start, PCIE_MEM_SIZE);
  260. }
  261. pcie->io.start = (u32)mvebu_pcie_iobase;
  262. pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
  263. mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
  264. if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
  265. (phys_addr_t)pcie->io.start,
  266. MBUS_PCI_IO_SIZE)) {
  267. printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
  268. (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
  269. }
  270. /* Setup windows and configure host bridge */
  271. mvebu_pcie_setup_wins(pcie);
  272. /* Master + slave enable. */
  273. reg = readl(pcie->base + PCIE_CMD_OFF);
  274. reg |= PCI_COMMAND_MEMORY;
  275. reg |= PCI_COMMAND_IO;
  276. reg |= PCI_COMMAND_MASTER;
  277. reg |= BIT(10); /* disable interrupts */
  278. writel(reg, pcie->base + PCIE_CMD_OFF);
  279. /* PCI memory space */
  280. pci_set_region(hose->regions + 0, pcie->mem.start,
  281. pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
  282. pci_set_region(hose->regions + 1,
  283. 0, 0,
  284. gd->ram_size,
  285. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  286. pci_set_region(hose->regions + 2, pcie->io.start,
  287. pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
  288. hose->region_count = 3;
  289. /* Set BAR0 to internal registers */
  290. writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
  291. writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
  292. return 0;
  293. }
  294. static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
  295. {
  296. const u32 *addr;
  297. int len;
  298. addr = ofnode_get_property(node, "assigned-addresses", &len);
  299. if (!addr) {
  300. pr_err("property \"assigned-addresses\" not found");
  301. return -FDT_ERR_NOTFOUND;
  302. }
  303. pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
  304. return 0;
  305. }
  306. #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
  307. #define DT_TYPE_IO 0x1
  308. #define DT_TYPE_MEM32 0x2
  309. #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
  310. #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
  311. static int mvebu_get_tgt_attr(ofnode node, int devfn,
  312. unsigned long type,
  313. unsigned int *tgt,
  314. unsigned int *attr)
  315. {
  316. const int na = 3, ns = 2;
  317. const __be32 *range;
  318. int rlen, nranges, rangesz, pna, i;
  319. *tgt = -1;
  320. *attr = -1;
  321. range = ofnode_get_property(node, "ranges", &rlen);
  322. if (!range)
  323. return -EINVAL;
  324. /*
  325. * Linux uses of_n_addr_cells() to get the number of address cells
  326. * here. Currently this function is only available in U-Boot when
  327. * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
  328. * general, lets't hardcode the "pna" value in the U-Boot code.
  329. */
  330. pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
  331. rangesz = pna + na + ns;
  332. nranges = rlen / sizeof(__be32) / rangesz;
  333. for (i = 0; i < nranges; i++, range += rangesz) {
  334. u32 flags = of_read_number(range, 1);
  335. u32 slot = of_read_number(range + 1, 1);
  336. u64 cpuaddr = of_read_number(range + na, pna);
  337. unsigned long rtype;
  338. if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
  339. rtype = IORESOURCE_IO;
  340. else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
  341. rtype = IORESOURCE_MEM;
  342. else
  343. continue;
  344. /*
  345. * The Linux code used PCI_SLOT() here, which expects devfn
  346. * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
  347. * only expects devfn in 15..8, where its saved in this driver.
  348. */
  349. if (slot == PCI_DEV(devfn) && type == rtype) {
  350. *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
  351. *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
  352. return 0;
  353. }
  354. }
  355. return -ENOENT;
  356. }
  357. static int mvebu_pcie_of_to_plat(struct udevice *dev)
  358. {
  359. struct mvebu_pcie *pcie = dev_get_plat(dev);
  360. int ret = 0;
  361. /* Get port number, lane number and memory target / attr */
  362. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
  363. &pcie->port)) {
  364. ret = -ENODEV;
  365. goto err;
  366. }
  367. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
  368. pcie->lane = 0;
  369. sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
  370. /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
  371. pcie->devfn = pci_get_devfn(dev);
  372. if (pcie->devfn < 0) {
  373. ret = -ENODEV;
  374. goto err;
  375. }
  376. ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
  377. IORESOURCE_MEM,
  378. &pcie->mem_target, &pcie->mem_attr);
  379. if (ret < 0) {
  380. printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
  381. goto err;
  382. }
  383. ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
  384. IORESOURCE_IO,
  385. &pcie->io_target, &pcie->io_attr);
  386. if (ret < 0) {
  387. printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
  388. goto err;
  389. }
  390. /* Parse PCIe controller register base from DT */
  391. ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
  392. if (ret < 0)
  393. goto err;
  394. /* Check link and skip ports that have no link */
  395. if (!mvebu_pcie_link_up(pcie)) {
  396. debug("%s: %s - down\n", __func__, pcie->name);
  397. ret = -ENODEV;
  398. goto err;
  399. }
  400. return 0;
  401. err:
  402. return ret;
  403. }
  404. static const struct dm_pci_ops mvebu_pcie_ops = {
  405. .read_config = mvebu_pcie_read_config,
  406. .write_config = mvebu_pcie_write_config,
  407. };
  408. static struct driver pcie_mvebu_drv = {
  409. .name = "pcie_mvebu",
  410. .id = UCLASS_PCI,
  411. .ops = &mvebu_pcie_ops,
  412. .probe = mvebu_pcie_probe,
  413. .of_to_plat = mvebu_pcie_of_to_plat,
  414. .plat_auto = sizeof(struct mvebu_pcie),
  415. };
  416. /*
  417. * Use a MISC device to bind the n instances (child nodes) of the
  418. * PCIe base controller in UCLASS_PCI.
  419. */
  420. static int mvebu_pcie_bind(struct udevice *parent)
  421. {
  422. struct mvebu_pcie *pcie;
  423. struct uclass_driver *drv;
  424. struct udevice *dev;
  425. ofnode subnode;
  426. /* Lookup eth driver */
  427. drv = lists_uclass_lookup(UCLASS_PCI);
  428. if (!drv) {
  429. puts("Cannot find PCI driver\n");
  430. return -ENOENT;
  431. }
  432. ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
  433. if (!ofnode_is_available(subnode))
  434. continue;
  435. pcie = calloc(1, sizeof(*pcie));
  436. if (!pcie)
  437. return -ENOMEM;
  438. /* Create child device UCLASS_PCI and bind it */
  439. device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
  440. &dev);
  441. }
  442. return 0;
  443. }
  444. static const struct udevice_id mvebu_pcie_ids[] = {
  445. { .compatible = "marvell,armada-xp-pcie" },
  446. { .compatible = "marvell,armada-370-pcie" },
  447. { }
  448. };
  449. U_BOOT_DRIVER(pcie_mvebu_base) = {
  450. .name = "pcie_mvebu_base",
  451. .id = UCLASS_MISC,
  452. .of_match = mvebu_pcie_ids,
  453. .bind = mvebu_pcie_bind,
  454. };