pci_auto.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI autoconfiguration library
  4. *
  5. * Author: Matt Porter <mporter@mvista.com>
  6. *
  7. * Copyright 2000 MontaVista Software Inc.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <pci.h>
  14. /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  15. #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  16. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  17. #endif
  18. static void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
  19. struct pci_region *mem,
  20. struct pci_region *prefetch,
  21. struct pci_region *io)
  22. {
  23. u32 bar_response;
  24. pci_size_t bar_size;
  25. u16 cmdstat = 0;
  26. int bar, bar_nr = 0;
  27. u8 header_type;
  28. int rom_addr;
  29. pci_addr_t bar_value;
  30. struct pci_region *bar_res = NULL;
  31. int found_mem64 = 0;
  32. u16 class;
  33. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  34. cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
  35. PCI_COMMAND_MASTER;
  36. for (bar = PCI_BASE_ADDRESS_0;
  37. bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  38. int ret = 0;
  39. /* Tickle the BAR and get the response */
  40. dm_pci_write_config32(dev, bar, 0xffffffff);
  41. dm_pci_read_config32(dev, bar, &bar_response);
  42. /* If BAR is not implemented (or invalid) go to the next BAR */
  43. if (!bar_response || bar_response == 0xffffffff)
  44. continue;
  45. found_mem64 = 0;
  46. /* Check the BAR type and set our address mask */
  47. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  48. bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
  49. bar_size &= ~(bar_size - 1);
  50. bar_res = io;
  51. debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  52. bar_nr, (unsigned long long)bar_size);
  53. } else {
  54. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  55. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  56. u32 bar_response_upper;
  57. u64 bar64;
  58. dm_pci_write_config32(dev, bar + 4, 0xffffffff);
  59. dm_pci_read_config32(dev, bar + 4,
  60. &bar_response_upper);
  61. bar64 = ((u64)bar_response_upper << 32) |
  62. bar_response;
  63. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
  64. + 1;
  65. found_mem64 = 1;
  66. } else {
  67. bar_size = (u32)(~(bar_response &
  68. PCI_BASE_ADDRESS_MEM_MASK) + 1);
  69. }
  70. if (prefetch &&
  71. (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
  72. bar_res = prefetch;
  73. else
  74. bar_res = mem;
  75. debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
  76. bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  77. found_mem64 ? "64" : "",
  78. (unsigned long long)bar_size);
  79. }
  80. ret = pciauto_region_allocate(bar_res, bar_size,
  81. &bar_value, found_mem64);
  82. if (ret)
  83. printf("PCI: Failed autoconfig bar %x\n", bar);
  84. if (!ret) {
  85. /* Write it out and update our limit */
  86. dm_pci_write_config32(dev, bar, (u32)bar_value);
  87. if (found_mem64) {
  88. bar += 4;
  89. #ifdef CONFIG_SYS_PCI_64BIT
  90. dm_pci_write_config32(dev, bar,
  91. (u32)(bar_value >> 32));
  92. #else
  93. /*
  94. * If we are a 64-bit decoder then increment to
  95. * the upper 32 bits of the bar and force it to
  96. * locate in the lower 4GB of memory.
  97. */
  98. dm_pci_write_config32(dev, bar, 0x00000000);
  99. #endif
  100. }
  101. }
  102. cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
  103. PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
  104. debug("\n");
  105. bar_nr++;
  106. }
  107. /* Configure the expansion ROM address */
  108. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  109. header_type &= 0x7f;
  110. if (header_type != PCI_HEADER_TYPE_CARDBUS) {
  111. rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
  112. PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
  113. dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
  114. dm_pci_read_config32(dev, rom_addr, &bar_response);
  115. if (bar_response) {
  116. bar_size = -(bar_response & ~1);
  117. debug("PCI Autoconfig: ROM, size=%#x, ",
  118. (unsigned int)bar_size);
  119. if (pciauto_region_allocate(mem, bar_size, &bar_value,
  120. false) == 0) {
  121. dm_pci_write_config32(dev, rom_addr, bar_value);
  122. }
  123. cmdstat |= PCI_COMMAND_MEMORY;
  124. debug("\n");
  125. }
  126. }
  127. /* PCI_COMMAND_IO must be set for VGA device */
  128. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  129. if (class == PCI_CLASS_DISPLAY_VGA)
  130. cmdstat |= PCI_COMMAND_IO;
  131. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
  132. dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
  133. CONFIG_SYS_PCI_CACHE_LINE_SIZE);
  134. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
  135. }
  136. void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
  137. {
  138. struct pci_region *pci_mem;
  139. struct pci_region *pci_prefetch;
  140. struct pci_region *pci_io;
  141. u16 cmdstat, prefechable_64;
  142. struct udevice *ctlr = pci_get_controller(dev);
  143. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  144. pci_mem = ctlr_hose->pci_mem;
  145. pci_prefetch = ctlr_hose->pci_prefetch;
  146. pci_io = ctlr_hose->pci_io;
  147. dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  148. dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
  149. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  150. /* Configure bus number registers */
  151. dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
  152. PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
  153. dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
  154. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
  155. if (pci_mem) {
  156. /* Round memory allocator to 1MB boundary */
  157. pciauto_region_align(pci_mem, 0x100000);
  158. /*
  159. * Set up memory and I/O filter limits, assume 32-bit
  160. * I/O space
  161. */
  162. dm_pci_write_config16(dev, PCI_MEMORY_BASE,
  163. (pci_mem->bus_lower & 0xfff00000) >> 16);
  164. cmdstat |= PCI_COMMAND_MEMORY;
  165. }
  166. if (pci_prefetch) {
  167. /* Round memory allocator to 1MB boundary */
  168. pciauto_region_align(pci_prefetch, 0x100000);
  169. /*
  170. * Set up memory and I/O filter limits, assume 32-bit
  171. * I/O space
  172. */
  173. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
  174. (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  175. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  176. #ifdef CONFIG_SYS_PCI_64BIT
  177. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
  178. pci_prefetch->bus_lower >> 32);
  179. #else
  180. dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
  181. #endif
  182. cmdstat |= PCI_COMMAND_MEMORY;
  183. } else {
  184. /* We don't support prefetchable memory for now, so disable */
  185. dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
  186. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  187. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  188. dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
  189. dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  190. }
  191. }
  192. if (pci_io) {
  193. /* Round I/O allocator to 4KB boundary */
  194. pciauto_region_align(pci_io, 0x1000);
  195. dm_pci_write_config8(dev, PCI_IO_BASE,
  196. (pci_io->bus_lower & 0x0000f000) >> 8);
  197. dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
  198. (pci_io->bus_lower & 0xffff0000) >> 16);
  199. cmdstat |= PCI_COMMAND_IO;
  200. }
  201. /* Enable memory and I/O accesses, enable bus master */
  202. dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
  203. }
  204. void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
  205. {
  206. struct pci_region *pci_mem;
  207. struct pci_region *pci_prefetch;
  208. struct pci_region *pci_io;
  209. struct udevice *ctlr = pci_get_controller(dev);
  210. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  211. pci_mem = ctlr_hose->pci_mem;
  212. pci_prefetch = ctlr_hose->pci_prefetch;
  213. pci_io = ctlr_hose->pci_io;
  214. /* Configure bus number registers */
  215. dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
  216. if (pci_mem) {
  217. /* Round memory allocator to 1MB boundary */
  218. pciauto_region_align(pci_mem, 0x100000);
  219. dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
  220. (pci_mem->bus_lower - 1) >> 16);
  221. }
  222. if (pci_prefetch) {
  223. u16 prefechable_64;
  224. dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
  225. &prefechable_64);
  226. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  227. /* Round memory allocator to 1MB boundary */
  228. pciauto_region_align(pci_prefetch, 0x100000);
  229. dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
  230. (pci_prefetch->bus_lower - 1) >> 16);
  231. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  232. #ifdef CONFIG_SYS_PCI_64BIT
  233. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
  234. (pci_prefetch->bus_lower - 1) >> 32);
  235. #else
  236. dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  237. #endif
  238. }
  239. if (pci_io) {
  240. /* Round I/O allocator to 4KB boundary */
  241. pciauto_region_align(pci_io, 0x1000);
  242. dm_pci_write_config8(dev, PCI_IO_LIMIT,
  243. ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
  244. dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
  245. ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
  246. }
  247. }
  248. /*
  249. * HJF: Changed this to return int. I think this is required
  250. * to get the correct result when scanning bridges
  251. */
  252. int dm_pciauto_config_device(struct udevice *dev)
  253. {
  254. struct pci_region *pci_mem;
  255. struct pci_region *pci_prefetch;
  256. struct pci_region *pci_io;
  257. unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
  258. unsigned short class;
  259. struct udevice *ctlr = pci_get_controller(dev);
  260. struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
  261. int ret;
  262. pci_mem = ctlr_hose->pci_mem;
  263. pci_prefetch = ctlr_hose->pci_prefetch;
  264. pci_io = ctlr_hose->pci_io;
  265. dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
  266. switch (class) {
  267. case PCI_CLASS_BRIDGE_PCI:
  268. debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  269. PCI_DEV(dm_pci_get_bdf(dev)));
  270. dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io);
  271. ret = dm_pci_hose_probe_bus(dev);
  272. if (ret < 0)
  273. return log_msg_ret("probe", ret);
  274. sub_bus = ret;
  275. break;
  276. case PCI_CLASS_BRIDGE_CARDBUS:
  277. /*
  278. * just do a minimal setup of the bridge,
  279. * let the OS take care of the rest
  280. */
  281. dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io);
  282. debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
  283. PCI_DEV(dm_pci_get_bdf(dev)));
  284. break;
  285. #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
  286. case PCI_CLASS_BRIDGE_OTHER:
  287. debug("PCI Autoconfig: Skipping bridge device %d\n",
  288. PCI_DEV(dm_pci_get_bdf(dev)));
  289. break;
  290. #endif
  291. #if defined(CONFIG_ARCH_MPC834X)
  292. case PCI_CLASS_BRIDGE_OTHER:
  293. /*
  294. * The host/PCI bridge 1 seems broken in 8349 - it presents
  295. * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
  296. * device claiming resources io/mem/irq.. we only allow for
  297. * the PIMMR window to be allocated (BAR0 - 1MB size)
  298. */
  299. debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
  300. dm_pciauto_setup_device(dev, 0, hose->pci_mem,
  301. hose->pci_prefetch, hose->pci_io);
  302. break;
  303. #endif
  304. case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
  305. debug("PCI AutoConfig: Found PowerPC device\n");
  306. /* fall through */
  307. default:
  308. dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io);
  309. break;
  310. }
  311. return sub_bus;
  312. }